2 * linux/arch/arm/plat-mxc/time.c
4 * Copyright (C) 2000-2001 Deep Blue Solutions
5 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
6 * Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
7 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/clockchips.h>
27 #include <linux/clk.h>
29 #include <mach/hardware.h>
30 #include <asm/mach/time.h>
31 #include <mach/common.h>
34 * There are 2 versions of the timer hardware on Freescale MXC hardware.
35 * Version 1: MX1/MXL, MX21, MX27.
36 * Version 2: MX25, MX31, MX35, MX37, MX51
39 /* defines common for all i.MX */
41 #define MXC_TCTL_TEN (1 << 0) /* Enable module */
42 #define MXC_TPRER 0x04
45 #define MX1_2_TCTL_CLK_PCLK1 (1 << 1)
46 #define MX1_2_TCTL_IRQEN (1 << 4)
47 #define MX1_2_TCTL_FRR (1 << 8)
48 #define MX1_2_TCMP 0x08
49 #define MX1_2_TCN 0x10
50 #define MX1_2_TSTAT 0x14
53 #define MX2_TSTAT_CAPT (1 << 1)
54 #define MX2_TSTAT_COMP (1 << 0)
56 /* MX31, MX35, MX25, MXC91231, MX5 */
57 #define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */
58 #define V2_TCTL_CLK_IPG (1 << 6)
59 #define V2_TCTL_FRR (1 << 9)
62 #define V2_TSTAT_OF1 (1 << 0)
66 #define timer_is_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
67 #define timer_is_v2() (!timer_is_v1())
69 static struct clock_event_device clockevent_mxc;
70 static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
72 static void __iomem *timer_base;
74 static inline void gpt_irq_disable(void)
79 __raw_writel(0, timer_base + V2_IR);
81 tmp = __raw_readl(timer_base + MXC_TCTL);
82 __raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL);
86 static inline void gpt_irq_enable(void)
89 __raw_writel(1<<0, timer_base + V2_IR);
91 __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN,
92 timer_base + MXC_TCTL);
96 static void gpt_irq_acknowledge(void)
100 __raw_writel(0, timer_base + MX1_2_TSTAT);
102 __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP,
103 timer_base + MX1_2_TSTAT);
104 } else if (timer_is_v2())
105 __raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT);
108 static cycle_t dummy_get_cycles(struct clocksource *cs)
113 static cycle_t mx1_2_get_cycles(struct clocksource *cs)
115 return __raw_readl(timer_base + MX1_2_TCN);
118 static cycle_t v2_get_cycles(struct clocksource *cs)
120 return __raw_readl(timer_base + V2_TCN);
123 static struct clocksource clocksource_mxc = {
124 .name = "mxc_timer1",
126 .read = dummy_get_cycles,
127 .mask = CLOCKSOURCE_MASK(32),
128 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
131 static int __init mxc_clocksource_init(struct clk *timer_clk)
133 unsigned int c = clk_get_rate(timer_clk);
136 clocksource_mxc.read = v2_get_cycles;
138 clocksource_mxc.read = mx1_2_get_cycles;
140 clocksource_register_hz(&clocksource_mxc, c);
147 static int mx1_2_set_next_event(unsigned long evt,
148 struct clock_event_device *unused)
152 tcmp = __raw_readl(timer_base + MX1_2_TCN) + evt;
154 __raw_writel(tcmp, timer_base + MX1_2_TCMP);
156 return (int)(tcmp - __raw_readl(timer_base + MX1_2_TCN)) < 0 ?
160 static int v2_set_next_event(unsigned long evt,
161 struct clock_event_device *unused)
165 tcmp = __raw_readl(timer_base + V2_TCN) + evt;
167 __raw_writel(tcmp, timer_base + V2_TCMP);
169 return (int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ?
174 static const char *clock_event_mode_label[] = {
175 [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
176 [CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT",
177 [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
178 [CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED"
182 static void mxc_set_mode(enum clock_event_mode mode,
183 struct clock_event_device *evt)
188 * The timer interrupt generation is disabled at least
189 * for enough time to call mxc_set_next_event()
191 local_irq_save(flags);
193 /* Disable interrupt in GPT module */
196 if (mode != clockevent_mode) {
197 /* Set event time into far-far future */
199 __raw_writel(__raw_readl(timer_base + V2_TCN) - 3,
200 timer_base + V2_TCMP);
202 __raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3,
203 timer_base + MX1_2_TCMP);
205 /* Clear pending interrupt */
206 gpt_irq_acknowledge();
210 printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n",
211 clock_event_mode_label[clockevent_mode],
212 clock_event_mode_label[mode]);
215 /* Remember timer mode */
216 clockevent_mode = mode;
217 local_irq_restore(flags);
220 case CLOCK_EVT_MODE_PERIODIC:
221 printk(KERN_ERR"mxc_set_mode: Periodic mode is not "
222 "supported for i.MX\n");
224 case CLOCK_EVT_MODE_ONESHOT:
226 * Do not put overhead of interrupt enable/disable into
227 * mxc_set_next_event(), the core has about 4 minutes
228 * to call mxc_set_next_event() or shutdown clock after
231 local_irq_save(flags);
233 local_irq_restore(flags);
235 case CLOCK_EVT_MODE_SHUTDOWN:
236 case CLOCK_EVT_MODE_UNUSED:
237 case CLOCK_EVT_MODE_RESUME:
238 /* Left event sources disabled, no more interrupts appear */
244 * IRQ handler for the timer
246 static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
248 struct clock_event_device *evt = &clockevent_mxc;
252 tstat = __raw_readl(timer_base + V2_TSTAT);
254 tstat = __raw_readl(timer_base + MX1_2_TSTAT);
256 gpt_irq_acknowledge();
258 evt->event_handler(evt);
263 static struct irqaction mxc_timer_irq = {
264 .name = "i.MX Timer Tick",
265 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
266 .handler = mxc_timer_interrupt,
269 static struct clock_event_device clockevent_mxc = {
270 .name = "mxc_timer1",
271 .features = CLOCK_EVT_FEAT_ONESHOT,
273 .set_mode = mxc_set_mode,
274 .set_next_event = mx1_2_set_next_event,
278 static int __init mxc_clockevent_init(struct clk *timer_clk)
280 unsigned int c = clk_get_rate(timer_clk);
283 clockevent_mxc.set_next_event = v2_set_next_event;
285 clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC,
286 clockevent_mxc.shift);
287 clockevent_mxc.max_delta_ns =
288 clockevent_delta2ns(0xfffffffe, &clockevent_mxc);
289 clockevent_mxc.min_delta_ns =
290 clockevent_delta2ns(0xff, &clockevent_mxc);
292 clockevent_mxc.cpumask = cpumask_of(0);
294 clockevents_register_device(&clockevent_mxc);
299 void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
303 clk_enable(timer_clk);
308 * Initialise to a known state (all timers off, and timing reset)
311 __raw_writel(0, timer_base + MXC_TCTL);
312 __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
315 tctl_val = V2_TCTL_CLK_IPG | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
317 tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
319 __raw_writel(tctl_val, timer_base + MXC_TCTL);
321 /* init and register the timer to the framework */
322 mxc_clocksource_init(timer_clk);
323 mxc_clockevent_init(timer_clk);
325 /* Make irqs happen */
326 setup_irq(irq, &mxc_timer_irq);