2 * linux/arch/arm/mm/mmu.c
4 * Copyright (C) 1995-2005 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/errno.h>
13 #include <linux/init.h>
14 #include <linux/bootmem.h>
15 #include <linux/mman.h>
16 #include <linux/nodemask.h>
18 #include <asm/cputype.h>
19 #include <asm/mach-types.h>
20 #include <asm/sections.h>
21 #include <asm/setup.h>
22 #include <asm/sizes.h>
25 #include <asm/mach/arch.h>
26 #include <asm/mach/map.h>
30 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
33 * empty_zero_page is a special page that is used for
34 * zero-initialized data and COW.
36 struct page *empty_zero_page;
37 EXPORT_SYMBOL(empty_zero_page);
40 * The pmd table for the upper-most set of pages.
44 #define CPOLICY_UNCACHED 0
45 #define CPOLICY_BUFFERED 1
46 #define CPOLICY_WRITETHROUGH 2
47 #define CPOLICY_WRITEBACK 3
48 #define CPOLICY_WRITEALLOC 4
50 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
51 static unsigned int ecc_mask __initdata = 0;
53 pgprot_t pgprot_kernel;
55 EXPORT_SYMBOL(pgprot_user);
56 EXPORT_SYMBOL(pgprot_kernel);
59 const char policy[16];
65 static struct cachepolicy cache_policies[] __initdata = {
69 .pmd = PMD_SECT_UNCACHED,
70 .pte = L_PTE_MT_UNCACHED,
74 .pmd = PMD_SECT_BUFFERED,
75 .pte = L_PTE_MT_BUFFERABLE,
77 .policy = "writethrough",
80 .pte = L_PTE_MT_WRITETHROUGH,
82 .policy = "writeback",
85 .pte = L_PTE_MT_WRITEBACK,
87 .policy = "writealloc",
90 .pte = L_PTE_MT_WRITEALLOC,
95 * These are useful for identifying cache coherency
96 * problems by allowing the cache or the cache and
97 * writebuffer to be turned off. (Note: the write
98 * buffer should not be on and the cache off).
100 static void __init early_cachepolicy(char **p)
104 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
105 int len = strlen(cache_policies[i].policy);
107 if (memcmp(*p, cache_policies[i].policy, len) == 0) {
109 cr_alignment &= ~cache_policies[i].cr_mask;
110 cr_no_alignment &= ~cache_policies[i].cr_mask;
115 if (i == ARRAY_SIZE(cache_policies))
116 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
117 if (cpu_architecture() >= CPU_ARCH_ARMv6) {
118 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
119 cachepolicy = CPOLICY_WRITEBACK;
122 set_cr(cr_alignment);
124 __early_param("cachepolicy=", early_cachepolicy);
126 static void __init early_nocache(char **__unused)
128 char *p = "buffered";
129 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
130 early_cachepolicy(&p);
132 __early_param("nocache", early_nocache);
134 static void __init early_nowrite(char **__unused)
136 char *p = "uncached";
137 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
138 early_cachepolicy(&p);
140 __early_param("nowb", early_nowrite);
142 static void __init early_ecc(char **p)
144 if (memcmp(*p, "on", 2) == 0) {
145 ecc_mask = PMD_PROTECTION;
147 } else if (memcmp(*p, "off", 3) == 0) {
152 __early_param("ecc=", early_ecc);
154 static int __init noalign_setup(char *__unused)
156 cr_alignment &= ~CR_A;
157 cr_no_alignment &= ~CR_A;
158 set_cr(cr_alignment);
161 __setup("noalign", noalign_setup);
164 void adjust_cr(unsigned long mask, unsigned long set)
172 local_irq_save(flags);
174 cr_no_alignment = (cr_no_alignment & ~mask) | set;
175 cr_alignment = (cr_alignment & ~mask) | set;
177 set_cr((get_cr() & ~mask) | set);
179 local_irq_restore(flags);
183 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_WRITE
184 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
186 static struct mem_type mem_types[] = {
187 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
188 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
190 .prot_l1 = PMD_TYPE_TABLE,
191 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
194 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
195 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
196 .prot_l1 = PMD_TYPE_TABLE,
197 .prot_sect = PROT_SECT_DEVICE,
200 [MT_DEVICE_CACHED] = { /* ioremap_cached */
201 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
202 .prot_l1 = PMD_TYPE_TABLE,
203 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
206 [MT_DEVICE_WC] = { /* ioremap_wc */
207 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
208 .prot_l1 = PMD_TYPE_TABLE,
209 .prot_sect = PROT_SECT_DEVICE,
213 .prot_pte = PROT_PTE_DEVICE,
214 .prot_l1 = PMD_TYPE_TABLE,
215 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
219 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
220 .domain = DOMAIN_KERNEL,
223 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
224 .domain = DOMAIN_KERNEL,
227 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
229 .prot_l1 = PMD_TYPE_TABLE,
230 .domain = DOMAIN_USER,
232 [MT_HIGH_VECTORS] = {
233 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
234 L_PTE_USER | L_PTE_EXEC,
235 .prot_l1 = PMD_TYPE_TABLE,
236 .domain = DOMAIN_USER,
239 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
240 .domain = DOMAIN_KERNEL,
243 .prot_sect = PMD_TYPE_SECT,
244 .domain = DOMAIN_KERNEL,
246 [MT_MEMORY_NONCACHED] = {
247 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
248 .domain = DOMAIN_KERNEL,
252 const struct mem_type *get_mem_type(unsigned int type)
254 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
258 * Adjust the PMD section entries according to the CPU in use.
260 static void __init build_mem_type_table(void)
262 struct cachepolicy *cp;
263 unsigned int cr = get_cr();
264 unsigned int user_pgprot, kern_pgprot, vecs_pgprot;
265 int cpu_arch = cpu_architecture();
268 if (cpu_arch < CPU_ARCH_ARMv6) {
269 #if defined(CONFIG_CPU_DCACHE_DISABLE)
270 if (cachepolicy > CPOLICY_BUFFERED)
271 cachepolicy = CPOLICY_BUFFERED;
272 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
273 if (cachepolicy > CPOLICY_WRITETHROUGH)
274 cachepolicy = CPOLICY_WRITETHROUGH;
277 if (cpu_arch < CPU_ARCH_ARMv5) {
278 if (cachepolicy >= CPOLICY_WRITEALLOC)
279 cachepolicy = CPOLICY_WRITEBACK;
283 cachepolicy = CPOLICY_WRITEALLOC;
287 * Strip out features not present on earlier architectures.
288 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
289 * without extended page tables don't have the 'Shared' bit.
291 if (cpu_arch < CPU_ARCH_ARMv5)
292 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
293 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
294 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
295 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
296 mem_types[i].prot_sect &= ~PMD_SECT_S;
299 * ARMv5 and lower, bit 4 must be set for page tables (was: cache
300 * "update-able on write" bit on ARM610). However, Xscale and
301 * Xscale3 require this bit to be cleared.
303 if (cpu_is_xscale() || cpu_is_xsc3()) {
304 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
305 mem_types[i].prot_sect &= ~PMD_BIT4;
306 mem_types[i].prot_l1 &= ~PMD_BIT4;
308 } else if (cpu_arch < CPU_ARCH_ARMv6) {
309 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
310 if (mem_types[i].prot_l1)
311 mem_types[i].prot_l1 |= PMD_BIT4;
312 if (mem_types[i].prot_sect)
313 mem_types[i].prot_sect |= PMD_BIT4;
318 * Mark the device areas according to the CPU/architecture.
320 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
321 if (!cpu_is_xsc3()) {
323 * Mark device regions on ARMv6+ as execute-never
324 * to prevent speculative instruction fetches.
326 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
327 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
328 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
329 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
331 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
333 * For ARMv7 with TEX remapping,
334 * - shared device is SXCB=1100
335 * - nonshared device is SXCB=0100
336 * - write combine device mem is SXCB=0001
337 * (Uncached Normal memory)
339 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
340 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
341 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
342 } else if (cpu_is_xsc3()) {
345 * - shared device is TEXCB=00101
346 * - nonshared device is TEXCB=01000
347 * - write combine device mem is TEXCB=00100
348 * (Inner/Outer Uncacheable in xsc3 parlance)
350 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
351 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
352 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
355 * For ARMv6 and ARMv7 without TEX remapping,
356 * - shared device is TEXCB=00001
357 * - nonshared device is TEXCB=01000
358 * - write combine device mem is TEXCB=00100
359 * (Uncached Normal in ARMv6 parlance).
361 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
362 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
363 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
367 * On others, write combining is "Uncached/Buffered"
369 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
373 * Now deal with the memory-type mappings
375 cp = &cache_policies[cachepolicy];
376 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
380 * Only use write-through for non-SMP systems
382 if (cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
383 vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
387 * Enable CPU-specific coherency if supported.
388 * (Only available on XSC3 at the moment.)
390 if (arch_is_coherent() && cpu_is_xsc3())
391 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
394 * ARMv6 and above have extended page tables.
396 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
398 * Mark cache clean areas and XIP ROM read only
399 * from SVC mode and no access from userspace.
401 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
402 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
403 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
407 * Mark memory with the "shared" attribute for SMP systems
409 user_pgprot |= L_PTE_SHARED;
410 kern_pgprot |= L_PTE_SHARED;
411 vecs_pgprot |= L_PTE_SHARED;
412 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
413 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
418 * Non-cacheable Normal - intended for memory areas that must
419 * not cause dirty cache line writebacks when used
421 if (cpu_arch >= CPU_ARCH_ARMv6) {
422 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
423 /* Non-cacheable Normal is XCB = 001 */
424 mem_types[MT_MEMORY_NONCACHED].prot_sect |=
427 /* For both ARMv6 and non-TEX-remapping ARMv7 */
428 mem_types[MT_MEMORY_NONCACHED].prot_sect |=
432 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
435 for (i = 0; i < 16; i++) {
436 unsigned long v = pgprot_val(protection_map[i]);
437 protection_map[i] = __pgprot(v | user_pgprot);
440 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
441 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
443 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
444 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
445 L_PTE_DIRTY | L_PTE_WRITE |
446 L_PTE_EXEC | kern_pgprot);
448 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
449 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
450 mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
451 mem_types[MT_ROM].prot_sect |= cp->pmd;
455 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
459 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
462 printk("Memory policy: ECC %sabled, Data cache %s\n",
463 ecc_mask ? "en" : "dis", cp->policy);
465 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
466 struct mem_type *t = &mem_types[i];
468 t->prot_l1 |= PMD_DOMAIN(t->domain);
470 t->prot_sect |= PMD_DOMAIN(t->domain);
474 #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
476 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
477 unsigned long end, unsigned long pfn,
478 const struct mem_type *type)
482 if (pmd_none(*pmd)) {
483 pte = alloc_bootmem_low_pages(2 * PTRS_PER_PTE * sizeof(pte_t));
484 __pmd_populate(pmd, __pa(pte) | type->prot_l1);
487 pte = pte_offset_kernel(pmd, addr);
489 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
491 } while (pte++, addr += PAGE_SIZE, addr != end);
494 static void __init alloc_init_section(pgd_t *pgd, unsigned long addr,
495 unsigned long end, unsigned long phys,
496 const struct mem_type *type)
498 pmd_t *pmd = pmd_offset(pgd, addr);
501 * Try a section mapping - end, addr and phys must all be aligned
502 * to a section boundary. Note that PMDs refer to the individual
503 * L1 entries, whereas PGDs refer to a group of L1 entries making
504 * up one logical pointer to an L2 table.
506 if (((addr | end | phys) & ~SECTION_MASK) == 0) {
509 if (addr & SECTION_SIZE)
513 *pmd = __pmd(phys | type->prot_sect);
514 phys += SECTION_SIZE;
515 } while (pmd++, addr += SECTION_SIZE, addr != end);
520 * No need to loop; pte's aren't interested in the
521 * individual L1 entries.
523 alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
527 static void __init create_36bit_mapping(struct map_desc *md,
528 const struct mem_type *type)
530 unsigned long phys, addr, length, end;
534 phys = (unsigned long)__pfn_to_phys(md->pfn);
535 length = PAGE_ALIGN(md->length);
537 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
538 printk(KERN_ERR "MM: CPU does not support supersection "
539 "mapping for 0x%08llx at 0x%08lx\n",
540 __pfn_to_phys((u64)md->pfn), addr);
544 /* N.B. ARMv6 supersections are only defined to work with domain 0.
545 * Since domain assignments can in fact be arbitrary, the
546 * 'domain == 0' check below is required to insure that ARMv6
547 * supersections are only allocated for domain 0 regardless
548 * of the actual domain assignments in use.
551 printk(KERN_ERR "MM: invalid domain in supersection "
552 "mapping for 0x%08llx at 0x%08lx\n",
553 __pfn_to_phys((u64)md->pfn), addr);
557 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
558 printk(KERN_ERR "MM: cannot create mapping for "
559 "0x%08llx at 0x%08lx invalid alignment\n",
560 __pfn_to_phys((u64)md->pfn), addr);
565 * Shift bits [35:32] of address into bits [23:20] of PMD
568 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
570 pgd = pgd_offset_k(addr);
573 pmd_t *pmd = pmd_offset(pgd, addr);
576 for (i = 0; i < 16; i++)
577 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
579 addr += SUPERSECTION_SIZE;
580 phys += SUPERSECTION_SIZE;
581 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
582 } while (addr != end);
586 * Create the page directory entries and any necessary
587 * page tables for the mapping specified by `md'. We
588 * are able to cope here with varying sizes and address
589 * offsets, and we take full advantage of sections and
592 void __init create_mapping(struct map_desc *md)
594 unsigned long phys, addr, length, end;
595 const struct mem_type *type;
598 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
599 printk(KERN_WARNING "BUG: not creating mapping for "
600 "0x%08llx at 0x%08lx in user region\n",
601 __pfn_to_phys((u64)md->pfn), md->virtual);
605 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
606 md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
607 printk(KERN_WARNING "BUG: mapping for 0x%08llx at 0x%08lx "
608 "overlaps vmalloc space\n",
609 __pfn_to_phys((u64)md->pfn), md->virtual);
612 type = &mem_types[md->type];
615 * Catch 36-bit addresses
617 if (md->pfn >= 0x100000) {
618 create_36bit_mapping(md, type);
622 addr = md->virtual & PAGE_MASK;
623 phys = (unsigned long)__pfn_to_phys(md->pfn);
624 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
626 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
627 printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not "
628 "be mapped using pages, ignoring.\n",
629 __pfn_to_phys(md->pfn), addr);
633 pgd = pgd_offset_k(addr);
636 unsigned long next = pgd_addr_end(addr, end);
638 alloc_init_section(pgd, addr, next, phys, type);
642 } while (pgd++, addr != end);
646 * Create the architecture specific mappings
648 void __init iotable_init(struct map_desc *io_desc, int nr)
652 for (i = 0; i < nr; i++)
653 create_mapping(io_desc + i);
656 static unsigned long __initdata vmalloc_reserve = SZ_128M;
659 * vmalloc=size forces the vmalloc area to be exactly 'size'
660 * bytes. This can be used to increase (or decrease) the vmalloc
661 * area - the default is 128m.
663 static void __init early_vmalloc(char **arg)
665 vmalloc_reserve = memparse(*arg, arg);
667 if (vmalloc_reserve < SZ_16M) {
668 vmalloc_reserve = SZ_16M;
670 "vmalloc area too small, limiting to %luMB\n",
671 vmalloc_reserve >> 20);
674 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
675 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
677 "vmalloc area is too big, limiting to %luMB\n",
678 vmalloc_reserve >> 20);
681 __early_param("vmalloc=", early_vmalloc);
683 #define VMALLOC_MIN (void *)(VMALLOC_END - vmalloc_reserve)
685 static void __init sanity_check_meminfo(void)
689 for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
690 struct membank *bank = &meminfo.bank[j];
691 *bank = meminfo.bank[i];
693 #ifdef CONFIG_HIGHMEM
695 * Split those memory banks which are partially overlapping
696 * the vmalloc area greatly simplifying things later.
698 if (__va(bank->start) < VMALLOC_MIN &&
699 bank->size > VMALLOC_MIN - __va(bank->start)) {
700 if (meminfo.nr_banks >= NR_BANKS) {
701 printk(KERN_CRIT "NR_BANKS too low, "
702 "ignoring high memory\n");
704 memmove(bank + 1, bank,
705 (meminfo.nr_banks - i) * sizeof(*bank));
708 bank[1].size -= VMALLOC_MIN - __va(bank->start);
709 bank[1].start = __pa(VMALLOC_MIN - 1) + 1;
712 bank->size = VMALLOC_MIN - __va(bank->start);
716 * Check whether this memory bank would entirely overlap
719 if (__va(bank->start) >= VMALLOC_MIN ||
720 __va(bank->start) < PAGE_OFFSET) {
721 printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx "
722 "(vmalloc region overlap).\n",
723 bank->start, bank->start + bank->size - 1);
728 * Check whether this memory bank would partially overlap
731 if (__va(bank->start + bank->size) > VMALLOC_MIN ||
732 __va(bank->start + bank->size) < __va(bank->start)) {
733 unsigned long newsize = VMALLOC_MIN - __va(bank->start);
734 printk(KERN_NOTICE "Truncating RAM at %.8lx-%.8lx "
735 "to -%.8lx (vmalloc region overlap).\n",
736 bank->start, bank->start + bank->size - 1,
737 bank->start + newsize - 1);
738 bank->size = newsize;
743 meminfo.nr_banks = j;
746 static inline void prepare_page_table(void)
751 * Clear out all the mappings below the kernel image.
753 for (addr = 0; addr < MODULES_VADDR; addr += PGDIR_SIZE)
754 pmd_clear(pmd_off_k(addr));
756 #ifdef CONFIG_XIP_KERNEL
757 /* The XIP kernel is mapped in the module area -- skip over it */
758 addr = ((unsigned long)_etext + PGDIR_SIZE - 1) & PGDIR_MASK;
760 for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE)
761 pmd_clear(pmd_off_k(addr));
764 * Clear out all the kernel space mappings, except for the first
765 * memory bank, up to the end of the vmalloc region.
767 for (addr = __phys_to_virt(bank_phys_end(&meminfo.bank[0]));
768 addr < VMALLOC_END; addr += PGDIR_SIZE)
769 pmd_clear(pmd_off_k(addr));
773 * Reserve the various regions of node 0
775 void __init reserve_node_zero(pg_data_t *pgdat)
777 unsigned long res_size = 0;
780 * Register the kernel text and data with bootmem.
781 * Note that this can only be in node 0.
783 #ifdef CONFIG_XIP_KERNEL
784 reserve_bootmem_node(pgdat, __pa(_data), _end - _data,
787 reserve_bootmem_node(pgdat, __pa(_stext), _end - _stext,
792 * Reserve the page tables. These are already in use,
793 * and can only be in node 0.
795 reserve_bootmem_node(pgdat, __pa(swapper_pg_dir),
796 PTRS_PER_PGD * sizeof(pgd_t), BOOTMEM_DEFAULT);
799 * Hmm... This should go elsewhere, but we really really need to
800 * stop things allocating the low memory; ideally we need a better
801 * implementation of GFP_DMA which does not assume that DMA-able
802 * memory starts at zero.
804 if (machine_is_integrator() || machine_is_cintegrator())
805 res_size = __pa(swapper_pg_dir) - PHYS_OFFSET;
808 * These should likewise go elsewhere. They pre-reserve the
809 * screen memory region at the start of main system memory.
811 if (machine_is_edb7211())
812 res_size = 0x00020000;
813 if (machine_is_p720t())
814 res_size = 0x00014000;
816 /* H1940 and RX3715 need to reserve this for suspend */
818 if (machine_is_h1940() || machine_is_rx3715()) {
819 reserve_bootmem_node(pgdat, 0x30003000, 0x1000,
821 reserve_bootmem_node(pgdat, 0x30081000, 0x1000,
827 * Because of the SA1111 DMA bug, we want to preserve our
828 * precious DMA-able memory...
830 res_size = __pa(swapper_pg_dir) - PHYS_OFFSET;
833 reserve_bootmem_node(pgdat, PHYS_OFFSET, res_size,
838 * Set up device the mappings. Since we clear out the page tables for all
839 * mappings above VMALLOC_END, we will remove any debug device mappings.
840 * This means you have to be careful how you debug this function, or any
841 * called function. This means you can't use any function or debugging
842 * method which may touch any device, otherwise the kernel _will_ crash.
844 static void __init devicemaps_init(struct machine_desc *mdesc)
851 * Allocate the vector page early.
853 vectors = alloc_bootmem_low_pages(PAGE_SIZE);
855 for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE)
856 pmd_clear(pmd_off_k(addr));
859 * Map the kernel if it is XIP.
860 * It is always first in the modulearea.
862 #ifdef CONFIG_XIP_KERNEL
863 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
864 map.virtual = MODULES_VADDR;
865 map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
867 create_mapping(&map);
871 * Map the cache flushing regions.
874 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
875 map.virtual = FLUSH_BASE;
877 map.type = MT_CACHECLEAN;
878 create_mapping(&map);
880 #ifdef FLUSH_BASE_MINICACHE
881 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
882 map.virtual = FLUSH_BASE_MINICACHE;
884 map.type = MT_MINICLEAN;
885 create_mapping(&map);
889 * Create a mapping for the machine vectors at the high-vectors
890 * location (0xffff0000). If we aren't using high-vectors, also
891 * create a mapping at the low-vectors virtual address.
893 map.pfn = __phys_to_pfn(virt_to_phys(vectors));
894 map.virtual = 0xffff0000;
895 map.length = PAGE_SIZE;
896 map.type = MT_HIGH_VECTORS;
897 create_mapping(&map);
899 if (!vectors_high()) {
901 map.type = MT_LOW_VECTORS;
902 create_mapping(&map);
906 * Ask the machine support to map in the statically mapped devices.
912 * Finally flush the caches and tlb to ensure that we're in a
913 * consistent state wrt the writebuffer. This also ensures that
914 * any write-allocated cache lines in the vector page are written
915 * back. After this point, we can start to touch devices again.
917 local_flush_tlb_all();
922 * paging_init() sets up the page tables, initialises the zone memory
923 * maps, and sets up the zero page, bad page and bad page tables.
925 void __init paging_init(struct machine_desc *mdesc)
929 build_mem_type_table();
930 sanity_check_meminfo();
931 prepare_page_table();
933 devicemaps_init(mdesc);
935 top_pmd = pmd_off_k(0xffff0000);
938 * allocate the zero page. Note that this always succeeds and
939 * returns a zeroed result.
941 zero_page = alloc_bootmem_low_pages(PAGE_SIZE);
942 empty_zero_page = virt_to_page(zero_page);
943 flush_dcache_page(empty_zero_page);
947 * In order to soft-boot, we need to insert a 1:1 mapping in place of
948 * the user-mode pages. This will then ensure that we have predictable
949 * results when turning the mmu off
951 void setup_mm_for_reboot(char mode)
953 unsigned long base_pmdval;
957 if (current->mm && current->mm->pgd)
958 pgd = current->mm->pgd;
962 base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT;
963 if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale())
964 base_pmdval |= PMD_BIT4;
966 for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) {
967 unsigned long pmdval = (i << PGDIR_SHIFT) | base_pmdval;
970 pmd = pmd_off(pgd, i << PGDIR_SHIFT);
971 pmd[0] = __pmd(pmdval);
972 pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1)));
973 flush_pmd_entry(pmd);