1 comment "Processor Type"
3 # Select CPU types depending on the architecture selected. This selects
4 # which CPUs we support in the kernel image, and the compiler instruction
9 bool "Support ARM610 processor" if ARCH_RPC
14 select CPU_COPY_V3 if MMU
15 select CPU_TLB_V3 if MMU
16 select CPU_PABRT_LEGACY
18 The ARM610 is the successor to the ARM3 processor
19 and was produced by VLSI Technology Inc.
21 Say Y if you want support for the ARM610 processor.
26 bool "Support ARM7TDMI processor"
30 select CPU_PABRT_LEGACY
33 A 32-bit RISC microprocessor based on the ARM7 processor core
34 which has no memory control unit and cache.
36 Say Y if you want support for the ARM7TDMI processor.
41 bool "Support ARM710 processor" if ARCH_RPC
46 select CPU_COPY_V3 if MMU
47 select CPU_TLB_V3 if MMU
48 select CPU_PABRT_LEGACY
50 A 32-bit RISC microprocessor based on the ARM7 processor core
51 designed by Advanced RISC Machines Ltd. The ARM710 is the
52 successor to the ARM610 processor. It was released in
53 July 1994 by VLSI Technology Inc.
55 Say Y if you want support for the ARM710 processor.
60 bool "Support ARM720T processor" if ARCH_INTEGRATOR
63 select CPU_PABRT_LEGACY
67 select CPU_COPY_V4WT if MMU
68 select CPU_TLB_V4WT if MMU
70 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
71 MMU built around an ARM7TDMI core.
73 Say Y if you want support for the ARM720T processor.
78 bool "Support ARM740T processor" if ARCH_INTEGRATOR
82 select CPU_PABRT_LEGACY
83 select CPU_CACHE_V3 # although the core is v4t
86 A 32-bit RISC processor with 8KB cache or 4KB variants,
87 write buffer and MPU(Protection Unit) built around
90 Say Y if you want support for the ARM740T processor.
95 bool "Support ARM9TDMI processor"
99 select CPU_PABRT_LEGACY
102 A 32-bit RISC microprocessor based on the ARM9 processor core
103 which has no memory control unit and cache.
105 Say Y if you want support for the ARM9TDMI processor.
110 bool "Support ARM920T processor" if ARCH_INTEGRATOR
113 select CPU_PABRT_LEGACY
114 select CPU_CACHE_V4WT
115 select CPU_CACHE_VIVT
117 select CPU_COPY_V4WB if MMU
118 select CPU_TLB_V4WBI if MMU
120 The ARM920T is licensed to be produced by numerous vendors,
121 and is used in the Cirrus EP93xx and the Samsung S3C2410.
123 Say Y if you want support for the ARM920T processor.
128 bool "Support ARM922T processor" if ARCH_INTEGRATOR
131 select CPU_PABRT_LEGACY
132 select CPU_CACHE_V4WT
133 select CPU_CACHE_VIVT
135 select CPU_COPY_V4WB if MMU
136 select CPU_TLB_V4WBI if MMU
138 The ARM922T is a version of the ARM920T, but with smaller
139 instruction and data caches. It is used in Altera's
140 Excalibur XA device family and Micrel's KS8695 Centaur.
142 Say Y if you want support for the ARM922T processor.
147 bool "Support ARM925T processor" if ARCH_OMAP1
150 select CPU_PABRT_LEGACY
151 select CPU_CACHE_V4WT
152 select CPU_CACHE_VIVT
154 select CPU_COPY_V4WB if MMU
155 select CPU_TLB_V4WBI if MMU
157 The ARM925T is a mix between the ARM920T and ARM926T, but with
158 different instruction and data caches. It is used in TI's OMAP
161 Say Y if you want support for the ARM925T processor.
166 bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB
168 select CPU_ABRT_EV5TJ
169 select CPU_PABRT_LEGACY
170 select CPU_CACHE_VIVT
172 select CPU_COPY_V4WB if MMU
173 select CPU_TLB_V4WBI if MMU
175 This is a variant of the ARM920. It has slightly different
176 instruction sequences for cache and TLB operations. Curiously,
177 there is no documentation on it at the ARM corporate website.
179 Say Y if you want support for the ARM926T processor.
187 select CPU_PABRT_LEGACY
188 select CPU_CACHE_VIVT
191 select CPU_COPY_FA if MMU
192 select CPU_TLB_FA if MMU
194 The FA526 is a version of the ARMv4 compatible processor with
195 Branch Target Buffer, Unified TLB and cache line size 16.
197 Say Y if you want support for the FA526 processor.
202 bool "Support ARM940T processor" if ARCH_INTEGRATOR
205 select CPU_ABRT_NOMMU
206 select CPU_PABRT_LEGACY
207 select CPU_CACHE_VIVT
210 ARM940T is a member of the ARM9TDMI family of general-
211 purpose microprocessors with MPU and separate 4KB
212 instruction and 4KB data cases, each with a 4-word line
215 Say Y if you want support for the ARM940T processor.
220 bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
223 select CPU_ABRT_NOMMU
224 select CPU_PABRT_LEGACY
225 select CPU_CACHE_VIVT
228 ARM946E-S is a member of the ARM9E-S family of high-
229 performance, 32-bit system-on-chip processor solutions.
230 The TCM and ARMv5TE 32-bit instruction set is supported.
232 Say Y if you want support for the ARM946E-S processor.
235 # ARM1020 - needs validating
237 bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR
240 select CPU_PABRT_LEGACY
241 select CPU_CACHE_V4WT
242 select CPU_CACHE_VIVT
244 select CPU_COPY_V4WB if MMU
245 select CPU_TLB_V4WBI if MMU
247 The ARM1020 is the 32K cached version of the ARM10 processor,
248 with an addition of a floating-point unit.
250 Say Y if you want support for the ARM1020 processor.
253 # ARM1020E - needs validating
255 bool "Support ARM1020E processor" if ARCH_INTEGRATOR
258 select CPU_PABRT_LEGACY
259 select CPU_CACHE_V4WT
260 select CPU_CACHE_VIVT
262 select CPU_COPY_V4WB if MMU
263 select CPU_TLB_V4WBI if MMU
268 bool "Support ARM1022E processor" if ARCH_INTEGRATOR
271 select CPU_PABRT_LEGACY
272 select CPU_CACHE_VIVT
274 select CPU_COPY_V4WB if MMU # can probably do better
275 select CPU_TLB_V4WBI if MMU
277 The ARM1022E is an implementation of the ARMv5TE architecture
278 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
279 embedded trace macrocell, and a floating-point unit.
281 Say Y if you want support for the ARM1022E processor.
286 bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR
288 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
289 select CPU_PABRT_LEGACY
290 select CPU_CACHE_VIVT
292 select CPU_COPY_V4WB if MMU # can probably do better
293 select CPU_TLB_V4WBI if MMU
295 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
296 based upon the ARM10 integer core.
298 Say Y if you want support for the ARM1026EJ-S processor.
303 bool "Support StrongARM(R) SA-110 processor" if ARCH_RPC
304 select CPU_32v3 if ARCH_RPC
305 select CPU_32v4 if !ARCH_RPC
307 select CPU_PABRT_LEGACY
308 select CPU_CACHE_V4WB
309 select CPU_CACHE_VIVT
311 select CPU_COPY_V4WB if MMU
312 select CPU_TLB_V4WB if MMU
314 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
315 is available at five speeds ranging from 100 MHz to 233 MHz.
316 More information is available at
317 <http://developer.intel.com/design/strong/sa110.htm>.
319 Say Y if you want support for the SA-110 processor.
327 select CPU_PABRT_LEGACY
328 select CPU_CACHE_V4WB
329 select CPU_CACHE_VIVT
331 select CPU_TLB_V4WB if MMU
338 select CPU_PABRT_LEGACY
339 select CPU_CACHE_VIVT
341 select CPU_TLB_V4WBI if MMU
343 # XScale Core Version 3
348 select CPU_PABRT_LEGACY
349 select CPU_CACHE_VIVT
351 select CPU_TLB_V4WBI if MMU
354 # Marvell PJ1 (Mohawk)
359 select CPU_PABRT_LEGACY
360 select CPU_CACHE_VIVT
362 select CPU_TLB_V4WBI if MMU
363 select CPU_COPY_V4WB if MMU
370 select CPU_PABRT_LEGACY
371 select CPU_CACHE_VIVT
373 select CPU_COPY_FEROCEON if MMU
374 select CPU_TLB_FEROCEON if MMU
376 config CPU_FEROCEON_OLD_ID
377 bool "Accept early Feroceon cores with an ARM926 ID"
378 depends on CPU_FEROCEON && !CPU_ARM926T
381 This enables the usage of some old Feroceon cores
382 for which the CPU ID is equal to the ARM926 ID.
383 Relevant for Feroceon-1850 and early Feroceon-2850.
393 bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || ARCH_DOVE
398 select CPU_CACHE_VIPT
400 select CPU_HAS_ASID if MMU
401 select CPU_COPY_V6 if MMU
402 select CPU_TLB_V6 if MMU
406 bool "Support ARM V6K processor extensions" if !SMP
407 depends on CPU_V6 || CPU_V7
408 default y if SMP && !(ARCH_MX3 || ARCH_OMAP2)
410 Say Y here if your ARMv6 processor supports the 'K' extension.
411 This enables the kernel to use some instructions not present
412 on previous processors, and as such a kernel build with this
413 enabled will not boot on processors with do not support these
418 bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
419 select CPU_32v6K if !ARCH_OMAP2
424 select CPU_CACHE_VIPT
426 select CPU_HAS_ASID if MMU
427 select CPU_COPY_V6 if MMU
428 select CPU_TLB_V7 if MMU
430 # Figure out what processor architecture version we should be using.
431 # This defines the compiler instruction set which depends on the machine type.
434 select TLS_REG_EMUL if SMP || !MMU
435 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
439 select TLS_REG_EMUL if SMP || !MMU
440 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
444 select TLS_REG_EMUL if SMP || !MMU
445 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
449 select TLS_REG_EMUL if SMP || !MMU
450 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
454 select TLS_REG_EMUL if !CPU_32v6K && !MMU
460 config CPU_ABRT_NOMMU
475 config CPU_ABRT_EV5TJ
484 config CPU_PABRT_LEGACY
500 config CPU_CACHE_V4WT
503 config CPU_CACHE_V4WB
512 config CPU_CACHE_VIVT
515 config CPU_CACHE_VIPT
522 # The copy-page model
532 config CPU_COPY_FEROCEON
541 # This selects the TLB model
545 ARM Architecture Version 3 TLB.
550 ARM Architecture Version 4 TLB with writethrough cache.
555 ARM Architecture Version 4 TLB with writeback cache.
560 ARM Architecture Version 4 TLB with writeback cache and invalidate
561 instruction cache entry.
563 config CPU_TLB_FEROCEON
566 Feroceon TLB (v4wbi with non-outer-cachable page table walks).
571 Faraday ARM FA526 architecture, unified TLB with writeback cache
572 and invalidate instruction cache entry. Branch target buffer is
581 config VERIFY_PERMISSION_FAULT
588 This indicates whether the CPU has the ASID register; used to
589 tag TLB and possibly cache entries.
594 Processor has the CP15 register.
600 Processor has the CP15 register, which has MMU related registers.
606 Processor has the CP15 register, which has MPU related registers.
609 # CPU supports 36-bit I/O
614 comment "Processor Features"
617 bool "Support Thumb user binaries"
618 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V7 || CPU_FEROCEON
621 Say Y if you want to include kernel support for running user space
624 The Thumb instruction set is a compressed form of the standard ARM
625 instruction set resulting in smaller binaries at the expense of
626 slightly less efficient code.
628 If you don't know what this all is, saying Y is a safe choice.
631 bool "Enable ThumbEE CPU extension"
634 Say Y here if you have a CPU with the ThumbEE extension and code to
635 make use of it. Say N for code that can run on CPUs without ThumbEE.
637 config CPU_BIG_ENDIAN
638 bool "Build big-endian kernel"
639 depends on ARCH_SUPPORTS_BIG_ENDIAN
641 Say Y if you plan on running a kernel in big-endian mode.
642 Note that your board must be properly built and your board
643 port must properly enable any big-endian related features
644 of your chipset/board/processor.
646 config CPU_ENDIAN_BE8
648 depends on CPU_BIG_ENDIAN
649 default CPU_V6 || CPU_V7
651 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
653 config CPU_ENDIAN_BE32
655 depends on CPU_BIG_ENDIAN
656 default !CPU_ENDIAN_BE8
658 Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
660 config CPU_HIGH_VECTOR
661 depends on !MMU && CPU_CP15 && !CPU_ARM740T
662 bool "Select the High exception vector"
664 Say Y here to select high exception vector(0xFFFF0000~).
665 The exception vector can be vary depending on the platform
666 design in nommu mode. If your platform needs to select
667 high exception vector, say Y.
668 Otherwise or if you are unsure, say N, and the low exception
669 vector (0x00000000~) will be used.
671 config CPU_ICACHE_DISABLE
672 bool "Disable I-Cache (I-bit)"
673 depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
675 Say Y here to disable the processor instruction cache. Unless
676 you have a reason not to or are unsure, say N.
678 config CPU_DCACHE_DISABLE
679 bool "Disable D-Cache (C-bit)"
682 Say Y here to disable the processor data cache. Unless
683 you have a reason not to or are unsure, say N.
685 config CPU_DCACHE_SIZE
687 depends on CPU_ARM740T || CPU_ARM946E
688 default 0x00001000 if CPU_ARM740T
689 default 0x00002000 # default size for ARM946E-S
691 Some cores are synthesizable to have various sized cache. For
692 ARM946E-S case, it can vary from 0KB to 1MB.
693 To support such cache operations, it is efficient to know the size
695 If your SoC is configured to have a different size, define the value
696 here with proper conditions.
698 config CPU_DCACHE_WRITETHROUGH
699 bool "Force write through D-cache"
700 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
701 default y if CPU_ARM925T
703 Say Y here to use the data cache in writethrough mode. Unless you
704 specifically require this or are unsure, say N.
706 config CPU_CACHE_ROUND_ROBIN
707 bool "Round robin I and D cache replacement algorithm"
708 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
710 Say Y here to use the predictable round-robin cache replacement
711 policy. Unless you specifically require this or are unsure, say N.
713 config CPU_BPREDICT_DISABLE
714 bool "Disable branch prediction"
715 depends on CPU_ARM1020 || CPU_V6 || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526
717 Say Y here to disable branch prediction. If unsure, say N.
722 An SMP system using a pre-ARMv6 processor (there are apparently
723 a few prototypes like that in existence) and therefore access to
724 that required register must be emulated.
726 config NEEDS_SYSCALL_FOR_CMPXCHG
729 SMP on a pre-ARMv6 processor? Well OK then.
730 Forget about fast user space cmpxchg support.
731 It is just not possible.
733 config DMA_CACHE_RWFO
734 bool "Enable read/write for ownership DMA cache maintenance"
735 depends on CPU_V6 && SMP
738 The Snoop Control Unit on ARM11MPCore does not detect the
739 cache maintenance operations and the dma_{map,unmap}_area()
740 functions may leave stale cache entries on other CPUs. By
741 enabling this option, Read or Write For Ownership in the ARMv6
742 DMA cache maintenance functions is performed. These LDR/STR
743 instructions change the cache line state to shared or modified
744 so that the cache operation has the desired effect.
746 Note that the workaround is only valid on processors that do
747 not perform speculative loads into the D-cache. For such
748 processors, if cache maintenance operations are not broadcast
749 in hardware, other workarounds are needed (e.g. cache
750 maintenance broadcasting in software via FIQ).
755 config OUTER_CACHE_SYNC
758 The outer cache has a outer_cache_fns.sync function pointer
759 that can be used to drain the write buffer of the outer cache.
761 config CACHE_FEROCEON_L2
762 bool "Enable the Feroceon L2 cache controller"
763 depends on ARCH_KIRKWOOD || ARCH_MV78XX0
767 This option enables the Feroceon L2 cache controller.
769 config CACHE_FEROCEON_L2_WRITETHROUGH
770 bool "Force Feroceon L2 cache write through"
771 depends on CACHE_FEROCEON_L2
773 Say Y here to use the Feroceon L2 cache in writethrough mode.
774 Unless you specifically require this, say N for writeback mode.
777 bool "Enable the L2x0 outer cache controller"
778 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
779 REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \
780 ARCH_NOMADIK || ARCH_OMAP4 || ARCH_S5PV310 || ARCH_TEGRA || \
781 ARCH_U8500 || ARCH_VEXPRESS_CA9X4
784 select OUTER_CACHE_SYNC
786 This option enables the L2x0 PrimeCell.
790 depends on CACHE_L2X0
791 default y if CPU_V7 && !CPU_V6
793 This option enables optimisations for the PL310 cache
797 bool "Enable the Tauros2 L2 cache controller"
798 depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)
802 This option enables the Tauros2 L2 cache controller (as
806 bool "Enable the L2 cache on XScale3"
811 This option enables the L2 cache on XScale3.
813 config ARM_L1_CACHE_SHIFT
815 default 6 if ARM_L1_CACHE_SHIFT_6
818 config ARM_DMA_MEM_BUFFERABLE
819 bool "Use non-cacheable memory for DMA" if CPU_V6 && !CPU_V7
820 depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \
821 MACH_REALVIEW_PB11MP)
822 default y if CPU_V6 || CPU_V7
824 Historically, the kernel has used strongly ordered mappings to
825 provide DMA coherent memory. With the advent of ARMv7, mapping
826 memory with differing types results in unpredictable behaviour,
827 so on these CPUs, this option is forced on.
829 Multiple mappings with differing attributes is also unpredictable
830 on ARMv6 CPUs, but since they do not have aggressive speculative
831 prefetch, no harm appears to occur.
833 However, drivers may be missing the necessary barriers for ARMv6,
834 and therefore turning this on may result in unpredictable driver
835 behaviour. Therefore, we offer this as an option.
837 You are recommended say 'Y' here and debug any affected drivers.
839 config ARCH_HAS_BARRIERS
842 This option allows the use of custom mandatory barriers
843 included via the mach/barriers.h file.