arch/arm/mach-u300/core.c

   1 /*
   2  *
   3  * arch/arm/mach-u300/core.c
   4  *
   5  *
   6  * Copyright (C) 2007-2012 ST-Ericsson SA
   7  * License terms: GNU General Public License (GPL) version 2
   8  * Core platform support, IRQ handling and device definitions.
   9  * Author: Linus Walleij <linus.walleij@stericsson.com>
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/pinctrl/machine.h>
  13 #include <linux/pinctrl/pinconf-generic.h>
  14 #include <linux/platform_data/clk-u300.h>
  15 #include <linux/platform_data/pinctrl-coh901.h>
  16 #include <linux/irqchip.h>
  17 #include <linux/of_platform.h>
  18 #include <linux/clocksource.h>
  19 #include <linux/clk.h>
  20
  21 #include <asm/mach/map.h>
  22 #include <asm/mach/arch.h>
  23
  24 #include "u300-regs.h"
  25
  26 /*
  27  * SYSCON addresses applicable to the core machine.
  28  */
  29
  30 /* Chip ID register 16bit (R/-) */
  31 #define U300_SYSCON_CIDR                                        (0x400)
  32 /* SMCR */
  33 #define U300_SYSCON_SMCR                                        (0x4d0)
  34 #define U300_SYSCON_SMCR_FIELD_MASK                             (0x000e)
  35 #define U300_SYSCON_SMCR_SEMI_SREFACK_IND                       (0x0008)
  36 #define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE                    (0x0004)
  37 #define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE              (0x0002)
  38 /* CPU_SW_DBGEN Software Debug Enable 16bit (R/W) */
  39 #define U300_SYSCON_CSDR                                        (0x4f0)
  40 #define U300_SYSCON_CSDR_SW_DEBUG_ENABLE                        (0x0001)
  41 /* PRINT_CONTROL Print Control 16bit (R/-) */
  42 #define U300_SYSCON_PCR                                         (0x4f8)
  43 #define U300_SYSCON_PCR_SERV_IND                                (0x0001)
  44 /* BOOT_CONTROL 16bit (R/-) */
  45 #define U300_SYSCON_BCR                                         (0x4fc)
  46 #define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND              (0x0400)
  47 #define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND              (0x0200)
  48 #define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK                  (0x01FC)
  49 #define U300_SYSCON_BCR_APP_BOOT_SERV_MASK                      (0x0003)
  50
  51 /*
  52  * Static I/O mappings that are needed for booting the U300 platforms. The
  53  * only things we need are the areas where we find the timer, syscon and
  54  * intcon, since the remaining device drivers will map their own memory
  55  * physical to virtual as the need arise.
  56  */
  57 static struct map_desc u300_io_desc[] __initdata = {
  58         {
  59                 .virtual        = U300_SLOW_PER_VIRT_BASE,
  60                 .pfn            = __phys_to_pfn(U300_SLOW_PER_PHYS_BASE),
  61                 .length         = SZ_64K,
  62                 .type           = MT_DEVICE,
  63         },
  64         {
  65                 .virtual        = U300_AHB_PER_VIRT_BASE,
  66                 .pfn            = __phys_to_pfn(U300_AHB_PER_PHYS_BASE),
  67                 .length         = SZ_32K,
  68                 .type           = MT_DEVICE,
  69         },
  70         {
  71                 .virtual        = U300_FAST_PER_VIRT_BASE,
  72                 .pfn            = __phys_to_pfn(U300_FAST_PER_PHYS_BASE),
  73                 .length         = SZ_32K,
  74                 .type           = MT_DEVICE,
  75         },
  76 };
  77
  78 static void __init u300_map_io(void)
  79 {
  80         iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
  81 }
  82
  83 /*
  84  * The different variants have a few different versions of the
  85  * GPIO block, with different number of ports.
  86  */
  87 static struct u300_gpio_platform u300_gpio_plat = {
  88         .ports = 7,
  89         .gpio_base = 0,
  90 };
  91
  92 static unsigned long pin_pullup_conf[] = {
  93         PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 1),
  94 };
  95
  96 static unsigned long pin_highz_conf[] = {
  97         PIN_CONF_PACKED(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0),
  98 };
  99
 100 /* Pin control settings */
 101 static struct pinctrl_map __initdata u300_pinmux_map[] = {
 102         /* anonymous maps for chip power and EMIFs */
 103         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "power"),
 104         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif0"),
 105         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif1"),
 106         /* per-device maps for MMC/SD, SPI and UART */
 107         PIN_MAP_MUX_GROUP_DEFAULT("mmci",  "pinctrl-u300", NULL, "mmc0"),
 108         PIN_MAP_MUX_GROUP_DEFAULT("pl022", "pinctrl-u300", NULL, "spi0"),
 109         PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-u300", NULL, "uart0"),
 110         /* This pin is used for clock return rather than GPIO */
 111         PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO APP GPIO 11",
 112                                     pin_pullup_conf),
 113         /* This pin is used for card detect */
 114         PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO MS INS",
 115                                     pin_highz_conf),
 116 };
 117
 118 struct db_chip {
 119         u16 chipid;
 120         const char *name;
 121 };
 122
 123 /*
 124  * This is a list of the Digital Baseband chips used in the U300 platform.
 125  */
 126 static struct db_chip db_chips[] __initdata = {
 127         {
 128                 .chipid = 0xb800,
 129                 .name = "DB3000",
 130         },
 131         {
 132                 .chipid = 0xc000,
 133                 .name = "DB3100",
 134         },
 135         {
 136                 .chipid = 0xc800,
 137                 .name = "DB3150",
 138         },
 139         {
 140                 .chipid = 0xd800,
 141                 .name = "DB3200",
 142         },
 143         {
 144                 .chipid = 0xe000,
 145                 .name = "DB3250",
 146         },
 147         {
 148                 .chipid = 0xe800,
 149                 .name = "DB3210",
 150         },
 151         {
 152                 .chipid = 0xf000,
 153                 .name = "DB3350 P1x",
 154         },
 155         {
 156                 .chipid = 0xf100,
 157                 .name = "DB3350 P2x",
 158         },
 159         {
 160                 .chipid = 0x0000, /* List terminator */
 161                 .name = NULL,
 162         }
 163 };
 164
 165 static void __init u300_init_check_chip(void)
 166 {
 167
 168         u16 val;
 169         struct db_chip *chip;
 170         const char *chipname;
 171         const char unknown[] = "UNKNOWN";
 172
 173         /* Read out and print chip ID */
 174         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR);
 175         /* This is in funky bigendian order... */
 176         val = (val & 0xFFU) << 8 | (val >> 8);
 177         chip = db_chips;
 178         chipname = unknown;
 179
 180         for ( ; chip->chipid; chip++) {
 181                 if (chip->chipid == (val & 0xFF00U)) {
 182                         chipname = chip->name;
 183                         break;
 184                 }
 185         }
 186         printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
 187                "(chip ID 0x%04x)\n", chipname, val);
 188
 189         if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
 190                 printk(KERN_ERR "Platform configured for BS335 " \
 191                        " with DB3350 but %s detected, expect problems!",
 192                        chipname);
 193         }
 194 }
 195
 196 /* Forward declare this function from the watchdog */
 197 void coh901327_watchdog_reset(void);
 198
 199 static void u300_restart(char mode, const char *cmd)
 200 {
 201         switch (mode) {
 202         case 's':
 203         case 'h':
 204 #ifdef CONFIG_COH901327_WATCHDOG
 205                 coh901327_watchdog_reset();
 206 #endif
 207                 break;
 208         default:
 209                 /* Do nothing */
 210                 break;
 211         }
 212         /* Wait for system do die/reset. */
 213         while (1);
 214 }
 215
 216 /* These are mostly to get the right device names for the clock lookups */
 217 static struct of_dev_auxdata u300_auxdata_lookup[] __initdata = {
 218         OF_DEV_AUXDATA("stericsson,pinctrl-u300", U300_SYSCON_BASE,
 219                 "pinctrl-u300", NULL),
 220         OF_DEV_AUXDATA("stericsson,gpio-coh901", U300_GPIO_BASE,
 221                 "u300-gpio", &u300_gpio_plat),
 222         OF_DEV_AUXDATA("stericsson,coh901327", U300_WDOG_BASE,
 223                 "coh901327_wdog", NULL),
 224         OF_DEV_AUXDATA("stericsson,coh901331", U300_RTC_BASE,
 225                 "rtc-coh901331", NULL),
 226         OF_DEV_AUXDATA("stericsson,coh901318", U300_DMAC_BASE,
 227                 "coh901318", NULL),
 228         OF_DEV_AUXDATA("stericsson,fsmc-nand", U300_NAND_IF_PHYS_BASE,
 229                 "fsmc-nand", NULL),
 230         OF_DEV_AUXDATA("arm,primecell", U300_UART0_BASE,
 231                 "uart0", NULL),
 232         OF_DEV_AUXDATA("arm,primecell", U300_UART1_BASE,
 233                 "uart1", NULL),
 234         OF_DEV_AUXDATA("arm,primecell", U300_SPI_BASE,
 235                 "pl022", NULL),
 236         OF_DEV_AUXDATA("st,ddci2c", U300_I2C0_BASE,
 237                 "stu300.0", NULL),
 238         OF_DEV_AUXDATA("st,ddci2c", U300_I2C1_BASE,
 239                 "stu300.1", NULL),
 240         OF_DEV_AUXDATA("arm,primecell", U300_MMCSD_BASE,
 241                 "mmci", NULL),
 242         { /* sentinel */ },
 243 };
 244
 245 static void __init u300_init_irq_dt(void)
 246 {
 247         struct clk *clk;
 248
 249         /* initialize clocking early, we want to clock the INTCON */
 250         u300_clk_init(U300_SYSCON_VBASE);
 251
 252         /* Bootstrap EMIF and SEMI clocks */
 253         clk = clk_get_sys("pl172", NULL);
 254         BUG_ON(IS_ERR(clk));
 255         clk_prepare_enable(clk);
 256         clk = clk_get_sys("semi", NULL);
 257         BUG_ON(IS_ERR(clk));
 258         clk_prepare_enable(clk);
 259
 260         /* Clock the interrupt controller */
 261         clk = clk_get_sys("intcon", NULL);
 262         BUG_ON(IS_ERR(clk));
 263         clk_prepare_enable(clk);
 264
 265         irqchip_init();
 266 }
 267
 268 static void __init u300_init_machine_dt(void)
 269 {
 270         u16 val;
 271
 272         /* Check what platform we run and print some status information */
 273         u300_init_check_chip();
 274
 275         /* Initialize pinmuxing */
 276         pinctrl_register_mappings(u300_pinmux_map,
 277                                   ARRAY_SIZE(u300_pinmux_map));
 278
 279         of_platform_populate(NULL, of_default_bus_match_table,
 280                         u300_auxdata_lookup, NULL);
 281
 282         /* Enable SEMI self refresh */
 283         val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
 284                 U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
 285         writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
 286 }
 287
 288 static const char * u300_board_compat[] = {
 289         "stericsson,u300",
 290         NULL,
 291 };
 292
 293 DT_MACHINE_START(U300_DT, "U300 S335/B335 (Device Tree)")
 294         .map_io         = u300_map_io,
 295         .init_irq       = u300_init_irq_dt,
 296         .init_time      = clocksource_of_init,
 297         .init_machine   = u300_init_machine_dt,
 298         .restart        = u300_restart,
 299         .dt_compat      = u300_board_compat,
 300 MACHINE_END