arch/arm/mach-spear/spear1340.c

   1 /*
   2  * arch/arm/mach-spear13xx/spear1340.c
   3  *
   4  * SPEAr1340 machine source file
   5  *
   6  * Copyright (C) 2012 ST Microelectronics
   7  * Viresh Kumar <viresh.linux@gmail.com>
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #define pr_fmt(fmt) "SPEAr1340: " fmt
  15
  16 #include <linux/ahci_platform.h>
  17 #include <linux/amba/serial.h>
  18 #include <linux/delay.h>
  19 #include <linux/of_platform.h>
  20 #include <linux/irqchip.h>
  21 #include <asm/mach/arch.h>
  22 #include "generic.h"
  23 #include <mach/spear.h>
  24
  25 /* FIXME: Move SATA PHY code into a standalone driver */
  26
  27 /* Base addresses */
  28 #define SPEAR1340_SATA_BASE                     UL(0xB1000000)
  29
  30 /* Power Management Registers */
  31 #define SPEAR1340_PCM_CFG                       (VA_MISC_BASE + 0x100)
  32 #define SPEAR1340_PCM_WKUP_CFG                  (VA_MISC_BASE + 0x104)
  33 #define SPEAR1340_SWITCH_CTR                    (VA_MISC_BASE + 0x108)
  34
  35 #define SPEAR1340_PERIP1_SW_RST                 (VA_MISC_BASE + 0x318)
  36 #define SPEAR1340_PERIP2_SW_RST                 (VA_MISC_BASE + 0x31C)
  37 #define SPEAR1340_PERIP3_SW_RST                 (VA_MISC_BASE + 0x320)
  38
  39 /* PCIE - SATA configuration registers */
  40 #define SPEAR1340_PCIE_SATA_CFG                 (VA_MISC_BASE + 0x424)
  41         /* PCIE CFG MASks */
  42         #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT       (1 << 11)
  43         #define SPEAR1340_PCIE_CFG_POWERUP_RESET        (1 << 10)
  44         #define SPEAR1340_PCIE_CFG_CORE_CLK_EN          (1 << 9)
  45         #define SPEAR1340_PCIE_CFG_AUX_CLK_EN           (1 << 8)
  46         #define SPEAR1340_SATA_CFG_TX_CLK_EN            (1 << 4)
  47         #define SPEAR1340_SATA_CFG_RX_CLK_EN            (1 << 3)
  48         #define SPEAR1340_SATA_CFG_POWERUP_RESET        (1 << 2)
  49         #define SPEAR1340_SATA_CFG_PM_CLK_EN            (1 << 1)
  50         #define SPEAR1340_PCIE_SATA_SEL_PCIE            (0)
  51         #define SPEAR1340_PCIE_SATA_SEL_SATA            (1)
  52         #define SPEAR1340_SATA_PCIE_CFG_MASK            0xF1F
  53         #define SPEAR1340_PCIE_CFG_VAL  (SPEAR1340_PCIE_SATA_SEL_PCIE | \
  54                         SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
  55                         SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
  56                         SPEAR1340_PCIE_CFG_POWERUP_RESET | \
  57                         SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
  58         #define SPEAR1340_SATA_CFG_VAL  (SPEAR1340_PCIE_SATA_SEL_SATA | \
  59                         SPEAR1340_SATA_CFG_PM_CLK_EN | \
  60                         SPEAR1340_SATA_CFG_POWERUP_RESET | \
  61                         SPEAR1340_SATA_CFG_RX_CLK_EN | \
  62                         SPEAR1340_SATA_CFG_TX_CLK_EN)
  63
  64 #define SPEAR1340_PCIE_MIPHY_CFG                (VA_MISC_BASE + 0x428)
  65         #define SPEAR1340_MIPHY_OSC_BYPASS_EXT          (1 << 31)
  66         #define SPEAR1340_MIPHY_CLK_REF_DIV2            (1 << 27)
  67         #define SPEAR1340_MIPHY_CLK_REF_DIV4            (2 << 27)
  68         #define SPEAR1340_MIPHY_CLK_REF_DIV8            (3 << 27)
  69         #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x)        (x << 0)
  70         #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
  71                         (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
  72                         SPEAR1340_MIPHY_CLK_REF_DIV2 | \
  73                         SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
  74         #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
  75                         (SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
  76         #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
  77                         (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
  78                         SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
  79
  80 /* SATA device registration */
  81 static int sata_miphy_init(struct device *dev, void __iomem *addr)
  82 {
  83         writel(SPEAR1340_SATA_CFG_VAL, SPEAR1340_PCIE_SATA_CFG);
  84         writel(SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK,
  85                         SPEAR1340_PCIE_MIPHY_CFG);
  86         /* Switch on sata power domain */
  87         writel((readl(SPEAR1340_PCM_CFG) | (0x800)), SPEAR1340_PCM_CFG);
  88         msleep(20);
  89         /* Disable PCIE SATA Controller reset */
  90         writel((readl(SPEAR1340_PERIP1_SW_RST) & (~0x1000)),
  91                         SPEAR1340_PERIP1_SW_RST);
  92         msleep(20);
  93
  94         return 0;
  95 }
  96
  97 void sata_miphy_exit(struct device *dev)
  98 {
  99         writel(0, SPEAR1340_PCIE_SATA_CFG);
 100         writel(0, SPEAR1340_PCIE_MIPHY_CFG);
 101
 102         /* Enable PCIE SATA Controller reset */
 103         writel((readl(SPEAR1340_PERIP1_SW_RST) | (0x1000)),
 104                         SPEAR1340_PERIP1_SW_RST);
 105         msleep(20);
 106         /* Switch off sata power domain */
 107         writel((readl(SPEAR1340_PCM_CFG) & (~0x800)), SPEAR1340_PCM_CFG);
 108         msleep(20);
 109 }
 110
 111 int sata_suspend(struct device *dev)
 112 {
 113         if (dev->power.power_state.event == PM_EVENT_FREEZE)
 114                 return 0;
 115
 116         sata_miphy_exit(dev);
 117
 118         return 0;
 119 }
 120
 121 int sata_resume(struct device *dev)
 122 {
 123         if (dev->power.power_state.event == PM_EVENT_THAW)
 124                 return 0;
 125
 126         return sata_miphy_init(dev, NULL);
 127 }
 128
 129 static struct ahci_platform_data sata_pdata = {
 130         .init = sata_miphy_init,
 131         .exit = sata_miphy_exit,
 132         .suspend = sata_suspend,
 133         .resume = sata_resume,
 134 };
 135
 136 /* Add SPEAr1340 auxdata to pass platform data */
 137 static struct of_dev_auxdata spear1340_auxdata_lookup[] __initdata = {
 138         OF_DEV_AUXDATA("snps,spear-ahci", SPEAR1340_SATA_BASE, NULL,
 139                         &sata_pdata),
 140         {}
 141 };
 142
 143 static void __init spear1340_dt_init(void)
 144 {
 145         of_platform_populate(NULL, of_default_bus_match_table,
 146                         spear1340_auxdata_lookup, NULL);
 147 }
 148
 149 static const char * const spear1340_dt_board_compat[] = {
 150         "st,spear1340",
 151         "st,spear1340-evb",
 152         NULL,
 153 };
 154
 155 DT_MACHINE_START(SPEAR1340_DT, "ST SPEAr1340 SoC with Flattened Device Tree")
 156         .smp            =       smp_ops(spear13xx_smp_ops),
 157         .map_io         =       spear13xx_map_io,
 158         .init_irq       =       irqchip_init,
 159         .init_time      =       spear13xx_timer_init,
 160         .init_machine   =       spear1340_dt_init,
 161         .restart        =       spear_restart,
 162         .dt_compat      =       spear1340_dt_board_compat,
 163 MACHINE_END