arch/arm/mach-socfpga/misc_s10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #include <altera.h>
   8 #include <common.h>
   9 #include <env.h>
  10 #include <errno.h>
  11 #include <fdtdec.h>
  12 #include <miiphy.h>
  13 #include <netdev.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/reset_manager.h>
  16 #include <asm/arch/system_manager.h>
  17 #include <asm/arch/misc.h>
  18 #include <asm/pl310.h>
  19 #include <linux/libfdt.h>
  20 #include <asm/arch/mailbox_s10.h>
  21
  22 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 /*
  27  * FPGA programming support for SoC FPGA Stratix 10
  28  */
  29 static Altera_desc altera_fpga[] = {
  30         {
  31                 /* Family */
  32                 Intel_FPGA_Stratix10,
  33                 /* Interface type */
  34                 secure_device_manager_mailbox,
  35                 /* No limitation as additional data will be ignored */
  36                 -1,
  37                 /* No device function table */
  38                 NULL,
  39                 /* Base interface address specified in driver */
  40                 NULL,
  41                 /* No cookie implementation */
  42                 0
  43         },
  44 };
  45
  46 /*
  47  * DesignWare Ethernet initialization
  48  */
  49 #ifdef CONFIG_ETH_DESIGNWARE
  50
  51 static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode)
  52 {
  53         u32 modereg;
  54
  55         if (!phymode)
  56                 return -EINVAL;
  57
  58         if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii") ||
  59             !strcmp(phymode, "sgmii"))
  60                 modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
  61         else if (!strcmp(phymode, "rgmii"))
  62                 modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
  63         else if (!strcmp(phymode, "rmii"))
  64                 modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
  65         else
  66                 return -EINVAL;
  67
  68         clrsetbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0 +
  69                         gmac_index,
  70                         SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, modereg);
  71
  72         return 0;
  73 }
  74
  75 static int socfpga_set_phymode(void)
  76 {
  77         const void *fdt = gd->fdt_blob;
  78         struct fdtdec_phandle_args args;
  79         const char *phy_mode;
  80         u32 gmac_index;
  81         int nodes[3];   /* Max. 3 GMACs */
  82         int ret, count;
  83         int i, node;
  84
  85         count = fdtdec_find_aliases_for_id(fdt, "ethernet",
  86                                            COMPAT_ALTERA_SOCFPGA_DWMAC,
  87                                            nodes, ARRAY_SIZE(nodes));
  88         for (i = 0; i < count; i++) {
  89                 node = nodes[i];
  90                 if (node <= 0)
  91                         continue;
  92
  93                 ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
  94                                                      "#reset-cells", 1, 0,
  95                                                      &args);
  96                 if (ret || args.args_count != 1) {
  97                         debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
  98                         continue;
  99                 }
 100
 101                 gmac_index = args.args[0] - EMAC0_RESET;
 102
 103                 phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
 104                 ret = socfpga_phymode_setup(gmac_index, phy_mode);
 105                 if (ret) {
 106                         debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
 107                         continue;
 108                 }
 109         }
 110
 111         return 0;
 112 }
 113 #else
 114 static int socfpga_set_phymode(void)
 115 {
 116         return 0;
 117 };
 118 #endif
 119
 120 /*
 121  * Print CPU information
 122  */
 123 #if defined(CONFIG_DISPLAY_CPUINFO)
 124 int print_cpuinfo(void)
 125 {
 126         puts("CPU:   Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)\n");
 127
 128         return 0;
 129 }
 130 #endif
 131
 132 #ifdef CONFIG_ARCH_MISC_INIT
 133 int arch_misc_init(void)
 134 {
 135         char qspi_string[13];
 136
 137         sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
 138         env_set("qspi_clock", qspi_string);
 139
 140         socfpga_set_phymode();
 141         return 0;
 142 }
 143 #endif
 144
 145 int arch_early_init_r(void)
 146 {
 147         socfpga_fpga_add(&altera_fpga[0]);
 148
 149         return 0;
 150 }
 151
 152 void do_bridge_reset(int enable, unsigned int mask)
 153 {
 154         /* Check FPGA status before bridge enable */
 155         if (enable) {
 156                 int ret = mbox_get_fpga_config_status(MBOX_RECONFIG_STATUS);
 157
 158                 if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG)
 159                         ret = mbox_get_fpga_config_status(MBOX_CONFIG_STATUS);
 160
 161                 if (ret)
 162                         return;
 163         }
 164
 165         socfpga_bridges_reset(enable);
 166 }