2 * R8A7740 processor support
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/delay.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
24 #include <linux/platform_device.h>
25 #include <linux/serial_sci.h>
26 #include <linux/sh_timer.h>
27 #include <mach/r8a7740.h>
28 #include <asm/mach-types.h>
29 #include <asm/mach/arch.h>
32 static struct plat_sci_port scif0_platform_data = {
33 .mapbase = 0xe6c40000,
34 .flags = UPF_BOOT_AUTOCONF,
35 .scscr = SCSCR_RE | SCSCR_TE,
36 .scbrr_algo_id = SCBRR_ALGO_4,
38 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c00)),
41 static struct platform_device scif0_device = {
45 .platform_data = &scif0_platform_data,
50 static struct plat_sci_port scif1_platform_data = {
51 .mapbase = 0xe6c50000,
52 .flags = UPF_BOOT_AUTOCONF,
53 .scscr = SCSCR_RE | SCSCR_TE,
54 .scbrr_algo_id = SCBRR_ALGO_4,
56 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c20)),
59 static struct platform_device scif1_device = {
63 .platform_data = &scif1_platform_data,
68 static struct plat_sci_port scif2_platform_data = {
69 .mapbase = 0xe6c60000,
70 .flags = UPF_BOOT_AUTOCONF,
71 .scscr = SCSCR_RE | SCSCR_TE,
72 .scbrr_algo_id = SCBRR_ALGO_4,
74 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c40)),
77 static struct platform_device scif2_device = {
81 .platform_data = &scif2_platform_data,
86 static struct plat_sci_port scif3_platform_data = {
87 .mapbase = 0xe6c70000,
88 .flags = UPF_BOOT_AUTOCONF,
89 .scscr = SCSCR_RE | SCSCR_TE,
90 .scbrr_algo_id = SCBRR_ALGO_4,
92 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c60)),
95 static struct platform_device scif3_device = {
99 .platform_data = &scif3_platform_data,
104 static struct plat_sci_port scif4_platform_data = {
105 .mapbase = 0xe6c80000,
106 .flags = UPF_BOOT_AUTOCONF,
107 .scscr = SCSCR_RE | SCSCR_TE,
108 .scbrr_algo_id = SCBRR_ALGO_4,
110 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d20)),
113 static struct platform_device scif4_device = {
117 .platform_data = &scif4_platform_data,
122 static struct plat_sci_port scif5_platform_data = {
123 .mapbase = 0xe6cb0000,
124 .flags = UPF_BOOT_AUTOCONF,
125 .scscr = SCSCR_RE | SCSCR_TE,
126 .scbrr_algo_id = SCBRR_ALGO_4,
128 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d40)),
131 static struct platform_device scif5_device = {
135 .platform_data = &scif5_platform_data,
140 static struct plat_sci_port scif6_platform_data = {
141 .mapbase = 0xe6cc0000,
142 .flags = UPF_BOOT_AUTOCONF,
143 .scscr = SCSCR_RE | SCSCR_TE,
144 .scbrr_algo_id = SCBRR_ALGO_4,
146 .irqs = SCIx_IRQ_MUXED(evt2irq(0x04c0)),
149 static struct platform_device scif6_device = {
153 .platform_data = &scif6_platform_data,
158 static struct plat_sci_port scif7_platform_data = {
159 .mapbase = 0xe6cd0000,
160 .flags = UPF_BOOT_AUTOCONF,
161 .scscr = SCSCR_RE | SCSCR_TE,
162 .scbrr_algo_id = SCBRR_ALGO_4,
164 .irqs = SCIx_IRQ_MUXED(evt2irq(0x04e0)),
167 static struct platform_device scif7_device = {
171 .platform_data = &scif7_platform_data,
176 static struct plat_sci_port scifb_platform_data = {
177 .mapbase = 0xe6c30000,
178 .flags = UPF_BOOT_AUTOCONF,
179 .scscr = SCSCR_RE | SCSCR_TE,
180 .scbrr_algo_id = SCBRR_ALGO_4,
182 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d60)),
185 static struct platform_device scifb_device = {
189 .platform_data = &scifb_platform_data,
194 static struct sh_timer_config cmt10_platform_data = {
196 .channel_offset = 0x10,
198 .clockevent_rating = 125,
199 .clocksource_rating = 125,
202 static struct resource cmt10_resources[] = {
207 .flags = IORESOURCE_MEM,
210 .start = evt2irq(0x0b00),
211 .flags = IORESOURCE_IRQ,
215 static struct platform_device cmt10_device = {
219 .platform_data = &cmt10_platform_data,
221 .resource = cmt10_resources,
222 .num_resources = ARRAY_SIZE(cmt10_resources),
225 static struct platform_device *r8a7740_early_devices[] __initdata = {
239 static struct resource i2c0_resources[] = {
243 .end = 0xfff20425 - 1,
244 .flags = IORESOURCE_MEM,
247 .start = intcs_evt2irq(0xe00),
248 .end = intcs_evt2irq(0xe60),
249 .flags = IORESOURCE_IRQ,
253 static struct resource i2c1_resources[] = {
257 .end = 0xe6c20425 - 1,
258 .flags = IORESOURCE_MEM,
261 .start = evt2irq(0x780), /* IIC1_ALI1 */
262 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
263 .flags = IORESOURCE_IRQ,
267 static struct platform_device i2c0_device = {
268 .name = "i2c-sh_mobile",
270 .resource = i2c0_resources,
271 .num_resources = ARRAY_SIZE(i2c0_resources),
274 static struct platform_device i2c1_device = {
275 .name = "i2c-sh_mobile",
277 .resource = i2c1_resources,
278 .num_resources = ARRAY_SIZE(i2c1_resources),
281 static struct platform_device *r8a7740_late_devices[] __initdata = {
287 #define ICSTART 0x0070
289 #define i2c_read(reg, offset) ioread8(reg + offset)
290 #define i2c_write(reg, offset, data) iowrite8(data, reg + offset)
293 * r8a7740 chip has lasting errata on I2C I/O pad reset.
294 * this is work-around for it.
296 static void r8a7740_i2c_workaround(struct platform_device *pdev)
298 struct resource *res;
301 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
302 if (unlikely(!res)) {
303 pr_err("r8a7740 i2c workaround fail (cannot find resource)\n");
307 reg = ioremap(res->start, resource_size(res));
308 if (unlikely(!reg)) {
309 pr_err("r8a7740 i2c workaround fail (cannot map IO)\n");
313 i2c_write(reg, ICCR, i2c_read(reg, ICCR) | 0x80);
314 i2c_read(reg, ICCR); /* dummy read */
316 i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) | 0x10);
317 i2c_read(reg, ICSTART); /* dummy read */
321 i2c_write(reg, ICCR, 0x01);
323 i2c_write(reg, ICSTART, 0x00);
324 i2c_read(reg, ICSTART);
326 i2c_write(reg, ICCR, 0x10);
328 i2c_write(reg, ICCR, 0x00);
330 i2c_write(reg, ICCR, 0x10);
336 void __init r8a7740_add_standard_devices(void)
338 /* I2C work-around */
339 r8a7740_i2c_workaround(&i2c0_device);
340 r8a7740_i2c_workaround(&i2c1_device);
342 platform_add_devices(r8a7740_early_devices,
343 ARRAY_SIZE(r8a7740_early_devices));
344 platform_add_devices(r8a7740_late_devices,
345 ARRAY_SIZE(r8a7740_late_devices));
348 void __init r8a7740_add_early_devices(void)
350 early_platform_add_devices(r8a7740_early_devices,
351 ARRAY_SIZE(r8a7740_early_devices));