1 /* linux/arch/arm/mach-s5p6440/clock.c
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
6 * S5P6440 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/sysdev.h>
23 #include <mach/hardware.h>
26 #include <plat/cpu-freq.h>
27 #include <mach/regs-clock.h>
28 #include <plat/clock.h>
30 #include <plat/clock-clksrc.h>
31 #include <plat/s5p-clock.h>
33 #include <plat/s5p6440.h>
35 /* APLL Mux output clock */
36 static struct clksrc_clk clk_mout_apll = {
41 .sources = &clk_src_apll,
42 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
45 static int s5p6440_epll_enable(struct clk *clk, int enable)
47 unsigned int ctrlbit = clk->ctrlbit;
48 unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit;
51 __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON);
53 __raw_writel(epll_con, S5P_EPLL_CON);
58 static unsigned long s5p6440_epll_get_rate(struct clk *clk)
63 static u32 epll_div[][5] = {
64 { 36000000, 0, 48, 1, 4 },
65 { 48000000, 0, 32, 1, 3 },
66 { 60000000, 0, 40, 1, 3 },
67 { 72000000, 0, 48, 1, 3 },
68 { 84000000, 0, 28, 1, 2 },
69 { 96000000, 0, 32, 1, 2 },
70 { 32768000, 45264, 43, 1, 4 },
71 { 45158000, 6903, 30, 1, 3 },
72 { 49152000, 50332, 32, 1, 3 },
73 { 67738000, 10398, 45, 1, 3 },
74 { 73728000, 9961, 49, 1, 3 }
77 static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate)
79 unsigned int epll_con, epll_con_k;
82 if (clk->rate == rate) /* Return if nothing changed */
85 epll_con = __raw_readl(S5P_EPLL_CON);
86 epll_con_k = __raw_readl(S5P_EPLL_CON_K);
88 epll_con_k &= ~(PLL90XX_KDIV_MASK);
89 epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
91 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
92 if (epll_div[i][0] == rate) {
93 epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
94 epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
95 (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
96 (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
101 if (i == ARRAY_SIZE(epll_div)) {
102 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
106 __raw_writel(epll_con, S5P_EPLL_CON);
107 __raw_writel(epll_con_k, S5P_EPLL_CON_K);
114 static struct clk_ops s5p6440_epll_ops = {
115 .get_rate = s5p6440_epll_get_rate,
116 .set_rate = s5p6440_epll_set_rate,
119 static struct clksrc_clk clk_mout_epll = {
124 .sources = &clk_src_epll,
125 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 2, .size = 1 },
128 static struct clksrc_clk clk_mout_mpll = {
133 .sources = &clk_src_mpll,
134 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 1, .size = 1 },
143 static const u32 clock_table[][3] = {
144 /*{ARM_CLK, DIVarm, DIVhclk}*/
145 {L0 * 1000, (0 << ARM_DIV_RATIO_SHIFT), (3 << S5P_CLKDIV0_HCLK_SHIFT)},
146 {L1 * 1000, (1 << ARM_DIV_RATIO_SHIFT), (1 << S5P_CLKDIV0_HCLK_SHIFT)},
147 {L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P_CLKDIV0_HCLK_SHIFT)},
150 static unsigned long s5p6440_armclk_get_rate(struct clk *clk)
152 unsigned long rate = clk_get_rate(clk->parent);
155 /* divisor mask starts at bit0, so no need to shift */
156 clkdiv = __raw_readl(ARM_CLK_DIV) & ARM_DIV_MASK;
158 return rate / (clkdiv + 1);
161 static unsigned long s5p6440_armclk_round_rate(struct clk *clk,
166 for (iter = 1 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
167 if (rate > clock_table[iter][0])
168 return clock_table[iter-1][0];
171 return clock_table[ARRAY_SIZE(clock_table) - 1][0];
174 static int s5p6440_armclk_set_rate(struct clk *clk, unsigned long rate)
179 u32 cur_rate = clk->ops->get_rate(clk);
182 round_tmp = clk->ops->round_rate(clk, rate);
183 if (round_tmp == cur_rate)
187 for (iter = 0 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
188 if (round_tmp == clock_table[iter][0])
192 if (iter >= ARRAY_SIZE(clock_table))
193 iter = ARRAY_SIZE(clock_table) - 1;
195 local_irq_save(flags);
196 if (cur_rate > round_tmp) {
198 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
199 clk_div0_tmp |= clock_table[iter][1];
200 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
202 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
203 ~(S5P_CLKDIV0_HCLK_MASK);
204 clk_div0_tmp |= clock_table[iter][2];
205 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
210 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
211 ~(S5P_CLKDIV0_HCLK_MASK);
212 clk_div0_tmp |= clock_table[iter][2];
213 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
215 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
216 clk_div0_tmp |= clock_table[iter][1];
217 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
219 local_irq_restore(flags);
221 clk->rate = clock_table[iter][0];
226 static struct clk_ops s5p6440_clkarm_ops = {
227 .get_rate = s5p6440_armclk_get_rate,
228 .set_rate = s5p6440_armclk_set_rate,
229 .round_rate = s5p6440_armclk_round_rate,
232 static struct clksrc_clk clk_armclk = {
236 .parent = &clk_mout_apll.clk,
237 .ops = &s5p6440_clkarm_ops,
239 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 4 },
242 static struct clksrc_clk clk_dout_mpll = {
246 .parent = &clk_mout_mpll.clk,
248 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 1 },
251 static struct clksrc_clk clk_hclk = {
255 .parent = &clk_armclk.clk,
257 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 4 },
260 static struct clksrc_clk clk_pclk = {
264 .parent = &clk_hclk.clk,
266 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 4 },
269 static struct clk *clkset_hclklow_list[] = {
274 static struct clksrc_sources clkset_hclklow = {
275 .sources = clkset_hclklow_list,
276 .nr_sources = ARRAY_SIZE(clkset_hclklow_list),
279 static struct clksrc_clk clk_hclk_low = {
284 .sources = &clkset_hclklow,
285 .reg_src = { .reg = S5P_SYS_OTHERS, .shift = 6, .size = 1 },
286 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
289 static struct clksrc_clk clk_pclk_low = {
293 .parent = &clk_hclk_low.clk,
295 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
298 int s5p6440_clk48m_ctrl(struct clk *clk, int enable)
303 /* can't rely on clock lock, this register has other usages */
304 local_irq_save(flags);
306 val = __raw_readl(S5P_OTHERS);
308 val |= S5P_OTHERS_USB_SIG_MASK;
310 val &= ~S5P_OTHERS_USB_SIG_MASK;
312 __raw_writel(val, S5P_OTHERS);
314 local_irq_restore(flags);
319 static int s5p6440_pclk_ctrl(struct clk *clk, int enable)
321 return s5p_gatectrl(S5P_CLK_GATE_PCLK, clk, enable);
324 static int s5p6440_hclk0_ctrl(struct clk *clk, int enable)
326 return s5p_gatectrl(S5P_CLK_GATE_HCLK0, clk, enable);
329 static int s5p6440_hclk1_ctrl(struct clk *clk, int enable)
331 return s5p_gatectrl(S5P_CLK_GATE_HCLK1, clk, enable);
334 static int s5p6440_sclk_ctrl(struct clk *clk, int enable)
336 return s5p_gatectrl(S5P_CLK_GATE_SCLK0, clk, enable);
339 static int s5p6440_sclk1_ctrl(struct clk *clk, int enable)
341 return s5p_gatectrl(S5P_CLK_GATE_SCLK1, clk, enable);
344 static int s5p6440_mem_ctrl(struct clk *clk, int enable)
346 return s5p_gatectrl(S5P_CLK_GATE_MEM0, clk, enable);
350 * The following clocks will be disabled during clock initialization. It is
351 * recommended to keep the following clocks disabled until the driver requests
352 * for enabling the clock.
354 static struct clk init_clocks_disable[] = {
358 .parent = &clk_hclk.clk,
359 .enable = s5p6440_mem_ctrl,
360 .ctrlbit = S5P_CLKCON_MEM0_HCLK_NFCON,
364 .parent = &clk_pclk_low.clk,
365 .enable = s5p6440_pclk_ctrl,
366 .ctrlbit = S5P_CLKCON_PCLK_TSADC,
370 .parent = &clk_pclk_low.clk,
371 .enable = s5p6440_pclk_ctrl,
372 .ctrlbit = S5P_CLKCON_PCLK_IIC0,
376 .parent = &clk_pclk_low.clk,
377 .enable = s5p6440_pclk_ctrl,
378 .ctrlbit = S5P_CLKCON_PCLK_IIS2,
382 .parent = &clk_pclk_low.clk,
383 .enable = s5p6440_pclk_ctrl,
384 .ctrlbit = S5P_CLKCON_PCLK_SPI0,
388 .parent = &clk_pclk_low.clk,
389 .enable = s5p6440_pclk_ctrl,
390 .ctrlbit = S5P_CLKCON_PCLK_SPI1,
392 .name = "sclk_spi_48",
395 .enable = s5p6440_sclk_ctrl,
396 .ctrlbit = S5P_CLKCON_SCLK0_SPI0_48,
398 .name = "sclk_spi_48",
401 .enable = s5p6440_sclk_ctrl,
402 .ctrlbit = S5P_CLKCON_SCLK0_SPI1_48,
407 .enable = s5p6440_sclk_ctrl,
408 .ctrlbit = S5P_CLKCON_SCLK0_MMC0_48,
413 .enable = s5p6440_sclk_ctrl,
414 .ctrlbit = S5P_CLKCON_SCLK0_MMC1_48,
419 .enable = s5p6440_sclk_ctrl,
420 .ctrlbit = S5P_CLKCON_SCLK0_MMC2_48,
424 .parent = &clk_hclk_low.clk,
425 .enable = s5p6440_hclk0_ctrl,
426 .ctrlbit = S5P_CLKCON_HCLK0_USB
430 .parent = &clk_hclk_low.clk,
431 .enable = s5p6440_hclk0_ctrl,
432 .ctrlbit = S5P_CLKCON_HCLK0_POST0
436 .parent = &clk_hclk_low.clk,
437 .enable = s5p6440_hclk1_ctrl,
438 .ctrlbit = S5P_CLKCON_HCLK1_DISPCON,
442 .parent = &clk_hclk_low.clk,
443 .enable = s5p6440_hclk0_ctrl,
444 .ctrlbit = S5P_CLKCON_HCLK0_HSMMC0,
448 .parent = &clk_hclk_low.clk,
449 .enable = s5p6440_hclk0_ctrl,
450 .ctrlbit = S5P_CLKCON_HCLK0_HSMMC1,
454 .parent = &clk_hclk_low.clk,
455 .enable = s5p6440_hclk0_ctrl,
456 .ctrlbit = S5P_CLKCON_HCLK0_HSMMC2,
460 .parent = &clk_pclk_low.clk,
461 .enable = s5p6440_pclk_ctrl,
462 .ctrlbit = S5P_CLKCON_PCLK_RTC,
466 .parent = &clk_pclk_low.clk,
467 .enable = s5p6440_pclk_ctrl,
468 .ctrlbit = S5P_CLKCON_PCLK_WDT,
472 .parent = &clk_pclk_low.clk,
473 .enable = s5p6440_pclk_ctrl,
474 .ctrlbit = S5P_CLKCON_PCLK_PWM,
476 .name = "hclk_fimgvg",
478 .parent = &clk_hclk.clk,
479 .enable = s5p6440_hclk1_ctrl,
484 .parent = &clk_hclk_low.clk,
485 .enable = s5p6440_hclk1_ctrl,
488 .name = "pclk_fimgvg",
490 .parent = &clk_pclk.clk,
491 .enable = s5p6440_pclk_ctrl,
492 .ctrlbit = (1 << 31),
496 .parent = &clk_pclk.clk,
497 .enable = s5p6440_pclk_ctrl,
498 .ctrlbit = (1 << 30),
502 .parent = &clk_pclk.clk,
503 .enable = s5p6440_pclk_ctrl,
504 .ctrlbit = (1 << 29),
508 .parent = &clk_pclk_low.clk,
509 .enable = s5p6440_pclk_ctrl,
510 .ctrlbit = (1 << 28),
514 .parent = &clk_pclk_low.clk,
515 .enable = s5p6440_pclk_ctrl,
516 .ctrlbit = (1 << 25),
520 .parent = &clk_pclk_low.clk,
521 .enable = s5p6440_pclk_ctrl,
526 .parent = &clk_hclk.clk,
527 .enable = s5p6440_hclk0_ctrl,
528 .ctrlbit = (1 << 25),
532 .parent = &clk_hclk_low.clk,
533 .enable = s5p6440_hclk0_ctrl,
534 .ctrlbit = (1 << 12),
538 .parent = &clk_hclk.clk,
539 .enable = s5p6440_hclk0_ctrl,
545 * The following clocks will be enabled during clock initialization.
547 static struct clk init_clocks[] = {
551 .parent = &clk_pclk_low.clk,
552 .enable = s5p6440_pclk_ctrl,
553 .ctrlbit = S5P_CLKCON_PCLK_GPIO,
557 .parent = &clk_pclk_low.clk,
558 .enable = s5p6440_pclk_ctrl,
559 .ctrlbit = S5P_CLKCON_PCLK_UART0,
563 .parent = &clk_pclk_low.clk,
564 .enable = s5p6440_pclk_ctrl,
565 .ctrlbit = S5P_CLKCON_PCLK_UART1,
569 .parent = &clk_pclk_low.clk,
570 .enable = s5p6440_pclk_ctrl,
571 .ctrlbit = S5P_CLKCON_PCLK_UART2,
575 .parent = &clk_pclk_low.clk,
576 .enable = s5p6440_pclk_ctrl,
577 .ctrlbit = S5P_CLKCON_PCLK_UART3,
581 .parent = &clk_hclk.clk,
582 .enable = s5p6440_hclk0_ctrl,
583 .ctrlbit = (1 << 21),
587 .parent = &clk_hclk.clk,
588 .enable = s5p6440_hclk0_ctrl,
593 static struct clk clk_iis_cd_v40 = {
594 .name = "iis_cdclk_v40",
598 static struct clk clk_pcm_cd = {
603 static struct clk *clkset_group1_list[] = {
609 static struct clksrc_sources clkset_group1 = {
610 .sources = clkset_group1_list,
611 .nr_sources = ARRAY_SIZE(clkset_group1_list),
614 static struct clk *clkset_uart_list[] = {
619 static struct clksrc_sources clkset_uart = {
620 .sources = clkset_uart_list,
621 .nr_sources = ARRAY_SIZE(clkset_uart_list),
624 static struct clk *clkset_audio_list[] = {
632 static struct clksrc_sources clkset_audio = {
633 .sources = clkset_audio_list,
634 .nr_sources = ARRAY_SIZE(clkset_audio_list),
637 static struct clksrc_clk clksrcs[] = {
642 .ctrlbit = S5P_CLKCON_SCLK0_MMC0,
643 .enable = s5p6440_sclk_ctrl,
645 .sources = &clkset_group1,
646 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 18, .size = 2 },
647 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4 },
652 .ctrlbit = S5P_CLKCON_SCLK0_MMC1,
653 .enable = s5p6440_sclk_ctrl,
655 .sources = &clkset_group1,
656 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 2 },
657 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 4 },
662 .ctrlbit = S5P_CLKCON_SCLK0_MMC2,
663 .enable = s5p6440_sclk_ctrl,
665 .sources = &clkset_group1,
666 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 22, .size = 2 },
667 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 4 },
672 .ctrlbit = S5P_CLKCON_SCLK0_UART,
673 .enable = s5p6440_sclk_ctrl,
675 .sources = &clkset_uart,
676 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 13, .size = 1 },
677 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 16, .size = 4 },
682 .ctrlbit = S5P_CLKCON_SCLK0_SPI0,
683 .enable = s5p6440_sclk_ctrl,
685 .sources = &clkset_group1,
686 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 14, .size = 2 },
687 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
692 .ctrlbit = S5P_CLKCON_SCLK0_SPI1,
693 .enable = s5p6440_sclk_ctrl,
695 .sources = &clkset_group1,
696 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 2 },
697 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
702 .ctrlbit = (1 << 10),
703 .enable = s5p6440_sclk_ctrl,
705 .sources = &clkset_group1,
706 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 26, .size = 2 },
707 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
710 .name = "sclk_dispcon",
713 .enable = s5p6440_sclk1_ctrl,
715 .sources = &clkset_group1,
716 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
717 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
720 .name = "sclk_fimgvg",
723 .enable = s5p6440_sclk1_ctrl,
725 .sources = &clkset_group1,
726 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
727 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
730 .name = "sclk_audio2",
732 .ctrlbit = (1 << 11),
733 .enable = s5p6440_sclk_ctrl,
735 .sources = &clkset_audio,
736 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 3 },
737 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 24, .size = 4 },
741 /* Clock initialisation code */
742 static struct clksrc_clk *sysclks[] = {
754 void __init_or_cpufreq s5p6440_setup_clocks(void)
756 struct clk *xtal_clk;
760 unsigned long hclk_low;
762 unsigned long pclk_low;
768 /* Set S5P6440 functions for clk_fout_epll */
769 clk_fout_epll.enable = s5p6440_epll_enable;
770 clk_fout_epll.ops = &s5p6440_epll_ops;
772 clk_48m.enable = s5p6440_clk48m_ctrl;
774 xtal_clk = clk_get(NULL, "ext_xtal");
775 BUG_ON(IS_ERR(xtal_clk));
777 xtal = clk_get_rate(xtal_clk);
780 epll = s5p_get_pll90xx(xtal, __raw_readl(S5P_EPLL_CON),
781 __raw_readl(S5P_EPLL_CON_K));
782 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
783 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4502);
785 clk_fout_mpll.rate = mpll;
786 clk_fout_epll.rate = epll;
787 clk_fout_apll.rate = apll;
789 printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
791 print_mhz(apll), print_mhz(mpll), print_mhz(epll));
793 fclk = clk_get_rate(&clk_armclk.clk);
794 hclk = clk_get_rate(&clk_hclk.clk);
795 pclk = clk_get_rate(&clk_pclk.clk);
796 hclk_low = clk_get_rate(&clk_hclk_low.clk);
797 pclk_low = clk_get_rate(&clk_pclk_low.clk);
799 printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
800 " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
801 print_mhz(hclk), print_mhz(hclk_low),
802 print_mhz(pclk), print_mhz(pclk_low));
808 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
809 s3c_set_clksrc(&clksrcs[ptr], true);
812 static struct clk *clks[] __initdata = {
818 void __init s5p6440_register_clocks(void)
824 ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
826 printk(KERN_ERR "Failed to register %u clocks\n", ret);
828 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
829 s3c_register_clksrc(sysclks[ptr], 1);
831 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
832 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
834 clkp = init_clocks_disable;
835 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
837 ret = s3c24xx_register_clock(clkp);
839 printk(KERN_ERR "Failed to register clock %s (%d)\n",
842 (clkp->enable)(clkp, 0);