arch/arm/mach-pxa/generic.c

   1 /*
   2  *  linux/arch/arm/mach-pxa/generic.c
   3  *
   4  *  Author:     Nicolas Pitre
   5  *  Created:    Jun 15, 2001
   6  *  Copyright:  MontaVista Software Inc.
   7  *
   8  * Code common to all PXA machines.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  * Since this file should be linked before any other machine specific file,
  15  * the __initcall() here will be executed first.  This serves as default
  16  * initialization stuff for PXA machines which can be overridden later if
  17  * need be.
  18  */
  19 #include <linux/module.h>
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/delay.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/ioport.h>
  25 #include <linux/pm.h>
  26 #include <linux/string.h>
  27 #include <linux/dma-mapping.h>
  28
  29 #include <asm/hardware.h>
  30 #include <asm/irq.h>
  31 #include <asm/system.h>
  32 #include <asm/pgtable.h>
  33 #include <asm/mach/map.h>
  34
  35 #include <asm/arch/pxa-regs.h>
  36 #include <asm/arch/gpio.h>
  37 #include <asm/arch/udc.h>
  38 #include <asm/arch/pxafb.h>
  39 #include <asm/arch/mmc.h>
  40 #include <asm/arch/irda.h>
  41 #include <asm/arch/i2c.h>
  42
  43 #include "devices.h"
  44 #include "generic.h"
  45
  46 /*
  47  * Get the clock frequency as reflected by CCCR and the turbo flag.
  48  * We assume these values have been applied via a fcs.
  49  * If info is not 0 we also display the current settings.
  50  */
  51 unsigned int get_clk_frequency_khz(int info)
  52 {
  53         if (cpu_is_pxa21x() || cpu_is_pxa25x())
  54                 return pxa25x_get_clk_frequency_khz(info);
  55         else if (cpu_is_pxa27x())
  56                 return pxa27x_get_clk_frequency_khz(info);
  57         else
  58                 return pxa3xx_get_clk_frequency_khz(info);
  59 }
  60 EXPORT_SYMBOL(get_clk_frequency_khz);
  61
  62 /*
  63  * Return the current memory clock frequency in units of 10kHz
  64  */
  65 unsigned int get_memclk_frequency_10khz(void)
  66 {
  67         if (cpu_is_pxa21x() || cpu_is_pxa25x())
  68                 return pxa25x_get_memclk_frequency_10khz();
  69         else if (cpu_is_pxa27x())
  70                 return pxa27x_get_memclk_frequency_10khz();
  71         else
  72                 return pxa3xx_get_memclk_frequency_10khz();
  73 }
  74 EXPORT_SYMBOL(get_memclk_frequency_10khz);
  75
  76 /*
  77  * Handy function to set GPIO alternate functions
  78  */
  79 int pxa_last_gpio;
  80
  81 int pxa_gpio_mode(int gpio_mode)
  82 {
  83         unsigned long flags;
  84         int gpio = gpio_mode & GPIO_MD_MASK_NR;
  85         int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
  86         int gafr;
  87
  88         if (gpio > pxa_last_gpio)
  89                 return -EINVAL;
  90
  91         local_irq_save(flags);
  92         if (gpio_mode & GPIO_DFLT_LOW)
  93                 GPCR(gpio) = GPIO_bit(gpio);
  94         else if (gpio_mode & GPIO_DFLT_HIGH)
  95                 GPSR(gpio) = GPIO_bit(gpio);
  96         if (gpio_mode & GPIO_MD_MASK_DIR)
  97                 GPDR(gpio) |= GPIO_bit(gpio);
  98         else
  99                 GPDR(gpio) &= ~GPIO_bit(gpio);
 100         gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
 101         GAFR(gpio) = gafr |  (fn  << (((gpio) & 0xf)*2));
 102         local_irq_restore(flags);
 103
 104         return 0;
 105 }
 106
 107 EXPORT_SYMBOL(pxa_gpio_mode);
 108
 109 int gpio_direction_input(unsigned gpio)
 110 {
 111         unsigned long flags;
 112         u32 mask;
 113
 114         if (gpio > pxa_last_gpio)
 115                 return -EINVAL;
 116
 117         mask = GPIO_bit(gpio);
 118         local_irq_save(flags);
 119         GPDR(gpio) &= ~mask;
 120         local_irq_restore(flags);
 121
 122         return 0;
 123 }
 124 EXPORT_SYMBOL(gpio_direction_input);
 125
 126 int gpio_direction_output(unsigned gpio, int value)
 127 {
 128         unsigned long flags;
 129         u32 mask;
 130
 131         if (gpio > pxa_last_gpio)
 132                 return -EINVAL;
 133
 134         mask = GPIO_bit(gpio);
 135         local_irq_save(flags);
 136         if (value)
 137                 GPSR(gpio) = mask;
 138         else
 139                 GPCR(gpio) = mask;
 140         GPDR(gpio) |= mask;
 141         local_irq_restore(flags);
 142
 143         return 0;
 144 }
 145 EXPORT_SYMBOL(gpio_direction_output);
 146
 147 /*
 148  * Return GPIO level
 149  */
 150 int pxa_gpio_get_value(unsigned gpio)
 151 {
 152         return __gpio_get_value(gpio);
 153 }
 154
 155 EXPORT_SYMBOL(pxa_gpio_get_value);
 156
 157 /*
 158  * Set output GPIO level
 159  */
 160 void pxa_gpio_set_value(unsigned gpio, int value)
 161 {
 162         __gpio_set_value(gpio, value);
 163 }
 164
 165 EXPORT_SYMBOL(pxa_gpio_set_value);
 166
 167 /*
 168  * Routine to safely enable or disable a clock in the CKEN
 169  */
 170 void __pxa_set_cken(int clock, int enable)
 171 {
 172         unsigned long flags;
 173         local_irq_save(flags);
 174
 175         if (enable)
 176                 CKEN |= (1 << clock);
 177         else
 178                 CKEN &= ~(1 << clock);
 179
 180         local_irq_restore(flags);
 181 }
 182
 183 EXPORT_SYMBOL(__pxa_set_cken);
 184
 185 /*
 186  * Intel PXA2xx internal register mapping.
 187  *
 188  * Note 1: not all PXA2xx variants implement all those addresses.
 189  *
 190  * Note 2: virtual 0xfffe0000-0xffffffff is reserved for the vector table
 191  *         and cache flush area.
 192  */
 193 static struct map_desc standard_io_desc[] __initdata = {
 194         {       /* Devs */
 195                 .virtual        =  0xf2000000,
 196                 .pfn            = __phys_to_pfn(0x40000000),
 197                 .length         = 0x02000000,
 198                 .type           = MT_DEVICE
 199         }, {    /* LCD */
 200                 .virtual        =  0xf4000000,
 201                 .pfn            = __phys_to_pfn(0x44000000),
 202                 .length         = 0x00100000,
 203                 .type           = MT_DEVICE
 204         }, {    /* Mem Ctl */
 205                 .virtual        =  0xf6000000,
 206                 .pfn            = __phys_to_pfn(0x48000000),
 207                 .length         = 0x00100000,
 208                 .type           = MT_DEVICE
 209         }, {    /* USB host */
 210                 .virtual        =  0xf8000000,
 211                 .pfn            = __phys_to_pfn(0x4c000000),
 212                 .length         = 0x00100000,
 213                 .type           = MT_DEVICE
 214         }, {    /* Camera */
 215                 .virtual        =  0xfa000000,
 216                 .pfn            = __phys_to_pfn(0x50000000),
 217                 .length         = 0x00100000,
 218                 .type           = MT_DEVICE
 219         }, {    /* IMem ctl */
 220                 .virtual        =  0xfe000000,
 221                 .pfn            = __phys_to_pfn(0x58000000),
 222                 .length         = 0x00100000,
 223                 .type           = MT_DEVICE
 224         }, {    /* UNCACHED_PHYS_0 */
 225                 .virtual        = 0xff000000,
 226                 .pfn            = __phys_to_pfn(0x00000000),
 227                 .length         = 0x00100000,
 228                 .type           = MT_DEVICE
 229         }
 230 };
 231
 232 void __init pxa_map_io(void)
 233 {
 234         iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
 235         get_clk_frequency_khz(1);
 236 }
 237
 238
 239 void __init pxa_register_device(struct platform_device *dev, void *data)
 240 {
 241         int ret;
 242
 243         dev->dev.platform_data = data;
 244
 245         ret = platform_device_register(dev);
 246         if (ret)
 247                 dev_err(&dev->dev, "unable to register device: %d\n", ret);
 248 }
 249
 250
 251 static struct resource pxamci_resources[] = {
 252         [0] = {
 253                 .start  = 0x41100000,
 254                 .end    = 0x41100fff,
 255                 .flags  = IORESOURCE_MEM,
 256         },
 257         [1] = {
 258                 .start  = IRQ_MMC,
 259                 .end    = IRQ_MMC,
 260                 .flags  = IORESOURCE_IRQ,
 261         },
 262         [2] = {
 263                 .start  = 21,
 264                 .end    = 21,
 265                 .flags  = IORESOURCE_DMA,
 266         },
 267         [3] = {
 268                 .start  = 22,
 269                 .end    = 22,
 270                 .flags  = IORESOURCE_DMA,
 271         },
 272 };
 273
 274 static u64 pxamci_dmamask = 0xffffffffUL;
 275
 276 struct platform_device pxa_device_mci = {
 277         .name           = "pxa2xx-mci",
 278         .id             = -1,
 279         .dev            = {
 280                 .dma_mask = &pxamci_dmamask,
 281                 .coherent_dma_mask = 0xffffffff,
 282         },
 283         .num_resources  = ARRAY_SIZE(pxamci_resources),
 284         .resource       = pxamci_resources,
 285 };
 286
 287 void __init pxa_set_mci_info(struct pxamci_platform_data *info)
 288 {
 289         pxa_register_device(&pxa_device_mci, info);
 290 }
 291
 292
 293 static struct pxa2xx_udc_mach_info pxa_udc_info;
 294
 295 void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
 296 {
 297         memcpy(&pxa_udc_info, info, sizeof *info);
 298 }
 299
 300 static struct resource pxa2xx_udc_resources[] = {
 301         [0] = {
 302                 .start  = 0x40600000,
 303                 .end    = 0x4060ffff,
 304                 .flags  = IORESOURCE_MEM,
 305         },
 306         [1] = {
 307                 .start  = IRQ_USB,
 308                 .end    = IRQ_USB,
 309                 .flags  = IORESOURCE_IRQ,
 310         },
 311 };
 312
 313 static u64 udc_dma_mask = ~(u32)0;
 314
 315 struct platform_device pxa_device_udc = {
 316         .name           = "pxa2xx-udc",
 317         .id             = -1,
 318         .resource       = pxa2xx_udc_resources,
 319         .num_resources  = ARRAY_SIZE(pxa2xx_udc_resources),
 320         .dev            =  {
 321                 .platform_data  = &pxa_udc_info,
 322                 .dma_mask       = &udc_dma_mask,
 323         }
 324 };
 325
 326 static struct resource pxafb_resources[] = {
 327         [0] = {
 328                 .start  = 0x44000000,
 329                 .end    = 0x4400ffff,
 330                 .flags  = IORESOURCE_MEM,
 331         },
 332         [1] = {
 333                 .start  = IRQ_LCD,
 334                 .end    = IRQ_LCD,
 335                 .flags  = IORESOURCE_IRQ,
 336         },
 337 };
 338
 339 static u64 fb_dma_mask = ~(u64)0;
 340
 341 struct platform_device pxa_device_fb = {
 342         .name           = "pxa2xx-fb",
 343         .id             = -1,
 344         .dev            = {
 345                 .dma_mask       = &fb_dma_mask,
 346                 .coherent_dma_mask = 0xffffffff,
 347         },
 348         .num_resources  = ARRAY_SIZE(pxafb_resources),
 349         .resource       = pxafb_resources,
 350 };
 351
 352 void __init set_pxa_fb_info(struct pxafb_mach_info *info)
 353 {
 354         pxa_register_device(&pxa_device_fb, info);
 355 }
 356
 357 void __init set_pxa_fb_parent(struct device *parent_dev)
 358 {
 359         pxa_device_fb.dev.parent = parent_dev;
 360 }
 361
 362 static struct resource pxa_resource_ffuart[] = {
 363         {
 364                 .start  = __PREG(FFUART),
 365                 .end    = __PREG(FFUART) + 35,
 366                 .flags  = IORESOURCE_MEM,
 367         }, {
 368                 .start  = IRQ_FFUART,
 369                 .end    = IRQ_FFUART,
 370                 .flags  = IORESOURCE_IRQ,
 371         }
 372 };
 373
 374 struct platform_device pxa_device_ffuart= {
 375         .name           = "pxa2xx-uart",
 376         .id             = 0,
 377         .resource       = pxa_resource_ffuart,
 378         .num_resources  = ARRAY_SIZE(pxa_resource_ffuart),
 379 };
 380
 381 static struct resource pxa_resource_btuart[] = {
 382         {
 383                 .start  = __PREG(BTUART),
 384                 .end    = __PREG(BTUART) + 35,
 385                 .flags  = IORESOURCE_MEM,
 386         }, {
 387                 .start  = IRQ_BTUART,
 388                 .end    = IRQ_BTUART,
 389                 .flags  = IORESOURCE_IRQ,
 390         }
 391 };
 392
 393 struct platform_device pxa_device_btuart = {
 394         .name           = "pxa2xx-uart",
 395         .id             = 1,
 396         .resource       = pxa_resource_btuart,
 397         .num_resources  = ARRAY_SIZE(pxa_resource_btuart),
 398 };
 399
 400 static struct resource pxa_resource_stuart[] = {
 401         {
 402                 .start  = __PREG(STUART),
 403                 .end    = __PREG(STUART) + 35,
 404                 .flags  = IORESOURCE_MEM,
 405         }, {
 406                 .start  = IRQ_STUART,
 407                 .end    = IRQ_STUART,
 408                 .flags  = IORESOURCE_IRQ,
 409         }
 410 };
 411
 412 struct platform_device pxa_device_stuart = {
 413         .name           = "pxa2xx-uart",
 414         .id             = 2,
 415         .resource       = pxa_resource_stuart,
 416         .num_resources  = ARRAY_SIZE(pxa_resource_stuart),
 417 };
 418
 419 static struct resource pxa_resource_hwuart[] = {
 420         {
 421                 .start  = __PREG(HWUART),
 422                 .end    = __PREG(HWUART) + 47,
 423                 .flags  = IORESOURCE_MEM,
 424         }, {
 425                 .start  = IRQ_HWUART,
 426                 .end    = IRQ_HWUART,
 427                 .flags  = IORESOURCE_IRQ,
 428         }
 429 };
 430
 431 struct platform_device pxa_device_hwuart = {
 432         .name           = "pxa2xx-uart",
 433         .id             = 3,
 434         .resource       = pxa_resource_hwuart,
 435         .num_resources  = ARRAY_SIZE(pxa_resource_hwuart),
 436 };
 437
 438 static struct resource pxai2c_resources[] = {
 439         {
 440                 .start  = 0x40301680,
 441                 .end    = 0x403016a3,
 442                 .flags  = IORESOURCE_MEM,
 443         }, {
 444                 .start  = IRQ_I2C,
 445                 .end    = IRQ_I2C,
 446                 .flags  = IORESOURCE_IRQ,
 447         },
 448 };
 449
 450 struct platform_device pxa_device_i2c = {
 451         .name           = "pxa2xx-i2c",
 452         .id             = 0,
 453         .resource       = pxai2c_resources,
 454         .num_resources  = ARRAY_SIZE(pxai2c_resources),
 455 };
 456
 457 void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
 458 {
 459         pxa_register_device(&pxa_device_i2c, info);
 460 }
 461
 462 static struct resource pxai2s_resources[] = {
 463         {
 464                 .start  = 0x40400000,
 465                 .end    = 0x40400083,
 466                 .flags  = IORESOURCE_MEM,
 467         }, {
 468                 .start  = IRQ_I2S,
 469                 .end    = IRQ_I2S,
 470                 .flags  = IORESOURCE_IRQ,
 471         },
 472 };
 473
 474 struct platform_device pxa_device_i2s = {
 475         .name           = "pxa2xx-i2s",
 476         .id             = -1,
 477         .resource       = pxai2s_resources,
 478         .num_resources  = ARRAY_SIZE(pxai2s_resources),
 479 };
 480
 481 static u64 pxaficp_dmamask = ~(u32)0;
 482
 483 struct platform_device pxa_device_ficp = {
 484         .name           = "pxa2xx-ir",
 485         .id             = -1,
 486         .dev            = {
 487                 .dma_mask = &pxaficp_dmamask,
 488                 .coherent_dma_mask = 0xffffffff,
 489         },
 490 };
 491
 492 void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
 493 {
 494         pxa_register_device(&pxa_device_ficp, info);
 495 }
 496
 497 struct platform_device pxa_device_rtc = {
 498         .name           = "sa1100-rtc",
 499         .id             = -1,
 500 };
 501
 502 #ifdef CONFIG_PXA25x
 503
 504 static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
 505
 506 static struct resource pxa25x_resource_ssp[] = {
 507         [0] = {
 508                 .start  = 0x41000000,
 509                 .end    = 0x4100001f,
 510                 .flags  = IORESOURCE_MEM,
 511         },
 512         [1] = {
 513                 .start  = IRQ_SSP,
 514                 .end    = IRQ_SSP,
 515                 .flags  = IORESOURCE_IRQ,
 516         },
 517         [2] = {
 518                 /* DRCMR for RX */
 519                 .start  = 13,
 520                 .end    = 13,
 521                 .flags  = IORESOURCE_DMA,
 522         },
 523         [3] = {
 524                 /* DRCMR for TX */
 525                 .start  = 14,
 526                 .end    = 14,
 527                 .flags  = IORESOURCE_DMA,
 528         },
 529 };
 530
 531 struct platform_device pxa25x_device_ssp = {
 532         .name           = "pxa25x-ssp",
 533         .id             = 0,
 534         .dev            = {
 535                 .dma_mask = &pxa25x_ssp_dma_mask,
 536                 .coherent_dma_mask = DMA_BIT_MASK(32),
 537         },
 538         .resource       = pxa25x_resource_ssp,
 539         .num_resources  = ARRAY_SIZE(pxa25x_resource_ssp),
 540 };
 541
 542 static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
 543
 544 static struct resource pxa25x_resource_nssp[] = {
 545         [0] = {
 546                 .start  = 0x41400000,
 547                 .end    = 0x4140002f,
 548                 .flags  = IORESOURCE_MEM,
 549         },
 550         [1] = {
 551                 .start  = IRQ_NSSP,
 552                 .end    = IRQ_NSSP,
 553                 .flags  = IORESOURCE_IRQ,
 554         },
 555         [2] = {
 556                 /* DRCMR for RX */
 557                 .start  = 15,
 558                 .end    = 15,
 559                 .flags  = IORESOURCE_DMA,
 560         },
 561         [3] = {
 562                 /* DRCMR for TX */
 563                 .start  = 16,
 564                 .end    = 16,
 565                 .flags  = IORESOURCE_DMA,
 566         },
 567 };
 568
 569 struct platform_device pxa25x_device_nssp = {
 570         .name           = "pxa25x-nssp",
 571         .id             = 1,
 572         .dev            = {
 573                 .dma_mask = &pxa25x_nssp_dma_mask,
 574                 .coherent_dma_mask = DMA_BIT_MASK(32),
 575         },
 576         .resource       = pxa25x_resource_nssp,
 577         .num_resources  = ARRAY_SIZE(pxa25x_resource_nssp),
 578 };
 579
 580 static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
 581
 582 static struct resource pxa25x_resource_assp[] = {
 583         [0] = {
 584                 .start  = 0x41500000,
 585                 .end    = 0x4150002f,
 586                 .flags  = IORESOURCE_MEM,
 587         },
 588         [1] = {
 589                 .start  = IRQ_ASSP,
 590                 .end    = IRQ_ASSP,
 591                 .flags  = IORESOURCE_IRQ,
 592         },
 593         [2] = {
 594                 /* DRCMR for RX */
 595                 .start  = 23,
 596                 .end    = 23,
 597                 .flags  = IORESOURCE_DMA,
 598         },
 599         [3] = {
 600                 /* DRCMR for TX */
 601                 .start  = 24,
 602                 .end    = 24,
 603                 .flags  = IORESOURCE_DMA,
 604         },
 605 };
 606
 607 struct platform_device pxa25x_device_assp = {
 608         /* ASSP is basically equivalent to NSSP */
 609         .name           = "pxa25x-nssp",
 610         .id             = 2,
 611         .dev            = {
 612                 .dma_mask = &pxa25x_assp_dma_mask,
 613                 .coherent_dma_mask = DMA_BIT_MASK(32),
 614         },
 615         .resource       = pxa25x_resource_assp,
 616         .num_resources  = ARRAY_SIZE(pxa25x_resource_assp),
 617 };
 618 #endif /* CONFIG_PXA25x */
 619
 620 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
 621
 622 static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
 623
 624 static struct resource pxa27x_resource_ssp1[] = {
 625         [0] = {
 626                 .start  = 0x41000000,
 627                 .end    = 0x4100003f,
 628                 .flags  = IORESOURCE_MEM,
 629         },
 630         [1] = {
 631                 .start  = IRQ_SSP,
 632                 .end    = IRQ_SSP,
 633                 .flags  = IORESOURCE_IRQ,
 634         },
 635         [2] = {
 636                 /* DRCMR for RX */
 637                 .start  = 13,
 638                 .end    = 13,
 639                 .flags  = IORESOURCE_DMA,
 640         },
 641         [3] = {
 642                 /* DRCMR for TX */
 643                 .start  = 14,
 644                 .end    = 14,
 645                 .flags  = IORESOURCE_DMA,
 646         },
 647 };
 648
 649 struct platform_device pxa27x_device_ssp1 = {
 650         .name           = "pxa27x-ssp",
 651         .id             = 0,
 652         .dev            = {
 653                 .dma_mask = &pxa27x_ssp1_dma_mask,
 654                 .coherent_dma_mask = DMA_BIT_MASK(32),
 655         },
 656         .resource       = pxa27x_resource_ssp1,
 657         .num_resources  = ARRAY_SIZE(pxa27x_resource_ssp1),
 658 };
 659
 660 static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
 661
 662 static struct resource pxa27x_resource_ssp2[] = {
 663         [0] = {
 664                 .start  = 0x41700000,
 665                 .end    = 0x4170003f,
 666                 .flags  = IORESOURCE_MEM,
 667         },
 668         [1] = {
 669                 .start  = IRQ_SSP2,
 670                 .end    = IRQ_SSP2,
 671                 .flags  = IORESOURCE_IRQ,
 672         },
 673         [2] = {
 674                 /* DRCMR for RX */
 675                 .start  = 15,
 676                 .end    = 15,
 677                 .flags  = IORESOURCE_DMA,
 678         },
 679         [3] = {
 680                 /* DRCMR for TX */
 681                 .start  = 16,
 682                 .end    = 16,
 683                 .flags  = IORESOURCE_DMA,
 684         },
 685 };
 686
 687 struct platform_device pxa27x_device_ssp2 = {
 688         .name           = "pxa27x-ssp",
 689         .id             = 1,
 690         .dev            = {
 691                 .dma_mask = &pxa27x_ssp2_dma_mask,
 692                 .coherent_dma_mask = DMA_BIT_MASK(32),
 693         },
 694         .resource       = pxa27x_resource_ssp2,
 695         .num_resources  = ARRAY_SIZE(pxa27x_resource_ssp2),
 696 };
 697
 698 static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
 699
 700 static struct resource pxa27x_resource_ssp3[] = {
 701         [0] = {
 702                 .start  = 0x41900000,
 703                 .end    = 0x4190003f,
 704                 .flags  = IORESOURCE_MEM,
 705         },
 706         [1] = {
 707                 .start  = IRQ_SSP3,
 708                 .end    = IRQ_SSP3,
 709                 .flags  = IORESOURCE_IRQ,
 710         },
 711         [2] = {
 712                 /* DRCMR for RX */
 713                 .start  = 66,
 714                 .end    = 66,
 715                 .flags  = IORESOURCE_DMA,
 716         },
 717         [3] = {
 718                 /* DRCMR for TX */
 719                 .start  = 67,
 720                 .end    = 67,
 721                 .flags  = IORESOURCE_DMA,
 722         },
 723 };
 724
 725 struct platform_device pxa27x_device_ssp3 = {
 726         .name           = "pxa27x-ssp",
 727         .id             = 2,
 728         .dev            = {
 729                 .dma_mask = &pxa27x_ssp3_dma_mask,
 730                 .coherent_dma_mask = DMA_BIT_MASK(32),
 731         },
 732         .resource       = pxa27x_resource_ssp3,
 733         .num_resources  = ARRAY_SIZE(pxa27x_resource_ssp3),
 734 };
 735 #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
 736
 737 #ifdef CONFIG_PXA3xx
 738 static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
 739
 740 static struct resource pxa3xx_resource_ssp4[] = {
 741         [0] = {
 742                 .start  = 0x41a00000,
 743                 .end    = 0x41a0003f,
 744                 .flags  = IORESOURCE_MEM,
 745         },
 746         [1] = {
 747                 .start  = IRQ_SSP4,
 748                 .end    = IRQ_SSP4,
 749                 .flags  = IORESOURCE_IRQ,
 750         },
 751         [2] = {
 752                 /* DRCMR for RX */
 753                 .start  = 2,
 754                 .end    = 2,
 755                 .flags  = IORESOURCE_DMA,
 756         },
 757         [3] = {
 758                 /* DRCMR for TX */
 759                 .start  = 3,
 760                 .end    = 3,
 761                 .flags  = IORESOURCE_DMA,
 762         },
 763 };
 764
 765 struct platform_device pxa3xx_device_ssp4 = {
 766         /* PXA3xx SSP is basically equivalent to PXA27x */
 767         .name           = "pxa27x-ssp",
 768         .id             = 3,
 769         .dev            = {
 770                 .dma_mask = &pxa3xx_ssp4_dma_mask,
 771                 .coherent_dma_mask = DMA_BIT_MASK(32),
 772         },
 773         .resource       = pxa3xx_resource_ssp4,
 774         .num_resources  = ARRAY_SIZE(pxa3xx_resource_ssp4),
 775 };
 776 #endif /* CONFIG_PXA3xx */