2 * arch/arm/mach-orion5x/irq.c
4 * Core IRQ functions for Marvell Orion System On Chip
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/irq.h>
18 #include <asm/arch/orion5x.h>
19 #include <asm/plat-orion/irq.h>
22 /*****************************************************************************
25 * GPIO_IN_POL register controlls whether GPIO_DATA_IN will hold the same
26 * value of the line or the opposite value.
28 * Level IRQ handlers: DATA_IN is used directly as cause register.
29 * Interrupt are masked by LEVEL_MASK registers.
30 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
31 * Interrupt are masked by EDGE_MASK registers.
32 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
33 * the polarity to catch the next line transaction.
34 * This is a race condition that might not perfectly
35 * work on some use cases.
37 * Every eight GPIO lines are grouped (OR'ed) before going up to main
41 * data-in /--------| |-----| |----\
42 * -----| |----- ---- to main cause reg
43 * X \----------------| |----/
46 ****************************************************************************/
47 static void orion5x_gpio_irq_ack(u32 irq)
49 int pin = irq_to_gpio(irq);
50 if (irq_desc[irq].status & IRQ_LEVEL)
52 * Mask bit for level interrupt
54 orion5x_clrbits(GPIO_LEVEL_MASK, 1 << pin);
57 * Clear casue bit for egde interrupt
59 orion5x_clrbits(GPIO_EDGE_CAUSE, 1 << pin);
62 static void orion5x_gpio_irq_mask(u32 irq)
64 int pin = irq_to_gpio(irq);
65 if (irq_desc[irq].status & IRQ_LEVEL)
66 orion5x_clrbits(GPIO_LEVEL_MASK, 1 << pin);
68 orion5x_clrbits(GPIO_EDGE_MASK, 1 << pin);
71 static void orion5x_gpio_irq_unmask(u32 irq)
73 int pin = irq_to_gpio(irq);
74 if (irq_desc[irq].status & IRQ_LEVEL)
75 orion5x_setbits(GPIO_LEVEL_MASK, 1 << pin);
77 orion5x_setbits(GPIO_EDGE_MASK, 1 << pin);
80 static int orion5x_gpio_set_irq_type(u32 irq, u32 type)
82 int pin = irq_to_gpio(irq);
83 struct irq_desc *desc;
85 if ((orion5x_read(GPIO_IO_CONF) & (1 << pin)) == 0) {
86 printk(KERN_ERR "orion5x_gpio_set_irq_type failed "
87 "(irq %d, pin %d).\n", irq, pin);
91 desc = irq_desc + irq;
95 desc->handle_irq = handle_level_irq;
96 desc->status |= IRQ_LEVEL;
97 orion5x_clrbits(GPIO_IN_POL, (1 << pin));
100 desc->handle_irq = handle_level_irq;
101 desc->status |= IRQ_LEVEL;
102 orion5x_setbits(GPIO_IN_POL, (1 << pin));
105 desc->handle_irq = handle_edge_irq;
106 desc->status &= ~IRQ_LEVEL;
107 orion5x_clrbits(GPIO_IN_POL, (1 << pin));
110 desc->handle_irq = handle_edge_irq;
111 desc->status &= ~IRQ_LEVEL;
112 orion5x_setbits(GPIO_IN_POL, (1 << pin));
115 desc->handle_irq = handle_edge_irq;
116 desc->status &= ~IRQ_LEVEL;
118 * set initial polarity based on current input level
120 if ((orion5x_read(GPIO_IN_POL) ^ orion5x_read(GPIO_DATA_IN))
122 orion5x_setbits(GPIO_IN_POL, (1 << pin)); /* falling */
124 orion5x_clrbits(GPIO_IN_POL, (1 << pin)); /* rising */
128 printk(KERN_ERR "failed to set irq=%d (type=%d)\n", irq, type);
132 desc->status &= ~IRQ_TYPE_SENSE_MASK;
133 desc->status |= type & IRQ_TYPE_SENSE_MASK;
138 static struct irq_chip orion5x_gpio_irq_chip = {
139 .name = "Orion-IRQ-GPIO",
140 .ack = orion5x_gpio_irq_ack,
141 .mask = orion5x_gpio_irq_mask,
142 .unmask = orion5x_gpio_irq_unmask,
143 .set_type = orion5x_gpio_set_irq_type,
146 static void orion5x_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
148 u32 cause, offs, pin;
150 BUG_ON(irq < IRQ_ORION5X_GPIO_0_7 || irq > IRQ_ORION5X_GPIO_24_31);
151 offs = (irq - IRQ_ORION5X_GPIO_0_7) * 8;
152 cause = (orion5x_read(GPIO_DATA_IN) & orion5x_read(GPIO_LEVEL_MASK)) |
153 (orion5x_read(GPIO_EDGE_CAUSE) & orion5x_read(GPIO_EDGE_MASK));
155 for (pin = offs; pin < offs + 8; pin++) {
156 if (cause & (1 << pin)) {
157 irq = gpio_to_irq(pin);
158 desc = irq_desc + irq;
159 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) {
160 /* Swap polarity (race with GPIO line) */
161 u32 polarity = orion5x_read(GPIO_IN_POL);
162 polarity ^= 1 << pin;
163 orion5x_write(GPIO_IN_POL, polarity);
165 desc_handle_irq(irq, desc);
170 static void __init orion5x_init_gpio_irq(void)
173 struct irq_desc *desc;
176 * Mask and clear GPIO IRQ interrupts
178 orion5x_write(GPIO_LEVEL_MASK, 0x0);
179 orion5x_write(GPIO_EDGE_MASK, 0x0);
180 orion5x_write(GPIO_EDGE_CAUSE, 0x0);
183 * Register chained level handlers for GPIO IRQs by default.
184 * User can use set_type() if he wants to use edge types handlers.
186 for (i = IRQ_ORION5X_GPIO_START; i < NR_IRQS; i++) {
187 set_irq_chip(i, &orion5x_gpio_irq_chip);
188 set_irq_handler(i, handle_level_irq);
190 desc->status |= IRQ_LEVEL;
191 set_irq_flags(i, IRQF_VALID);
193 set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, orion5x_gpio_irq_handler);
194 set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, orion5x_gpio_irq_handler);
195 set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, orion5x_gpio_irq_handler);
196 set_irq_chained_handler(IRQ_ORION5X_GPIO_24_31, orion5x_gpio_irq_handler);
199 /*****************************************************************************
201 ****************************************************************************/
202 static void __init orion5x_init_main_irq(void)
204 orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK);
207 void __init orion5x_init_irq(void)
209 orion5x_init_main_irq();
210 orion5x_init_gpio_irq();