arch/arm/mach-omap2/pm34xx.c

   1 /*
   2  * OMAP3 Power Management Routines
   3  *
   4  * Copyright (C) 2006-2008 Nokia Corporation
   5  * Tony Lindgren <tony@atomide.com>
   6  * Jouni Hogander
   7  *
   8  * Copyright (C) 2007 Texas Instruments, Inc.
   9  * Rajendra Nayak <rnayak@ti.com>
  10  *
  11  * Copyright (C) 2005 Texas Instruments, Inc.
  12  * Richard Woodruff <r-woodruff2@ti.com>
  13  *
  14  * Based on pm.c for omap1
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/pm.h>
  22 #include <linux/suspend.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/module.h>
  25 #include <linux/list.h>
  26 #include <linux/err.h>
  27 #include <linux/gpio.h>
  28 #include <linux/clk.h>
  29 #include <linux/delay.h>
  30 #include <linux/slab.h>
  31 #include <linux/console.h>
  32 #include <trace/events/power.h>
  33
  34 #include <asm/suspend.h>
  35
  36 #include <plat/sram.h>
  37 #include "clockdomain.h"
  38 #include "powerdomain.h"
  39 #include <plat/serial.h>
  40 #include <plat/sdrc.h>
  41 #include <plat/prcm.h>
  42 #include <plat/gpmc.h>
  43 #include <plat/dma.h>
  44
  45 #include "cm2xxx_3xxx.h"
  46 #include "cm-regbits-34xx.h"
  47 #include "prm-regbits-34xx.h"
  48
  49 #include "prm2xxx_3xxx.h"
  50 #include "pm.h"
  51 #include "sdrc.h"
  52 #include "control.h"
  53
  54 #ifdef CONFIG_SUSPEND
  55 static suspend_state_t suspend_state = PM_SUSPEND_ON;
  56 static inline bool is_suspending(void)
  57 {
  58         return (suspend_state != PM_SUSPEND_ON);
  59 }
  60 #else
  61 static inline bool is_suspending(void)
  62 {
  63         return false;
  64 }
  65 #endif
  66
  67 /* pm34xx errata defined in pm.h */
  68 u16 pm34xx_errata;
  69
  70 struct power_state {
  71         struct powerdomain *pwrdm;
  72         u32 next_state;
  73 #ifdef CONFIG_SUSPEND
  74         u32 saved_state;
  75 #endif
  76         struct list_head node;
  77 };
  78
  79 static LIST_HEAD(pwrst_list);
  80
  81 static void (*_omap_sram_idle)(u32 *addr, int save_state);
  82
  83 static int (*_omap_save_secure_sram)(u32 *addr);
  84
  85 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
  86 static struct powerdomain *core_pwrdm, *per_pwrdm;
  87 static struct powerdomain *cam_pwrdm;
  88
  89 static inline void omap3_per_save_context(void)
  90 {
  91         omap_gpio_save_context();
  92 }
  93
  94 static inline void omap3_per_restore_context(void)
  95 {
  96         omap_gpio_restore_context();
  97 }
  98
  99 static void omap3_enable_io_chain(void)
 100 {
 101         int timeout = 0;
 102
 103         if (omap_rev() >= OMAP3430_REV_ES3_1) {
 104                 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
 105                                      PM_WKEN);
 106                 /* Do a readback to assure write has been done */
 107                 omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 108
 109                 while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
 110                          OMAP3430_ST_IO_CHAIN_MASK)) {
 111                         timeout++;
 112                         if (timeout > 1000) {
 113                                 printk(KERN_ERR "Wake up daisy chain "
 114                                        "activation failed.\n");
 115                                 return;
 116                         }
 117                         omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
 118                                              WKUP_MOD, PM_WKEN);
 119                 }
 120         }
 121 }
 122
 123 static void omap3_disable_io_chain(void)
 124 {
 125         if (omap_rev() >= OMAP3430_REV_ES3_1)
 126                 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
 127                                        PM_WKEN);
 128 }
 129
 130 static void omap3_core_save_context(void)
 131 {
 132         omap3_ctrl_save_padconf();
 133
 134         /*
 135          * Force write last pad into memory, as this can fail in some
 136          * cases according to errata 1.157, 1.185
 137          */
 138         omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
 139                 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
 140
 141         /* Save the Interrupt controller context */
 142         omap_intc_save_context();
 143         /* Save the GPMC context */
 144         omap3_gpmc_save_context();
 145         /* Save the system control module context, padconf already save above*/
 146         omap3_control_save_context();
 147         omap_dma_global_context_save();
 148 }
 149
 150 static void omap3_core_restore_context(void)
 151 {
 152         /* Restore the control module context, padconf restored by h/w */
 153         omap3_control_restore_context();
 154         /* Restore the GPMC context */
 155         omap3_gpmc_restore_context();
 156         /* Restore the interrupt controller context */
 157         omap_intc_restore_context();
 158         omap_dma_global_context_restore();
 159 }
 160
 161 /*
 162  * FIXME: This function should be called before entering off-mode after
 163  * OMAP3 secure services have been accessed. Currently it is only called
 164  * once during boot sequence, but this works as we are not using secure
 165  * services.
 166  */
 167 static void omap3_save_secure_ram_context(void)
 168 {
 169         u32 ret;
 170         int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 171
 172         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 173                 /*
 174                  * MPU next state must be set to POWER_ON temporarily,
 175                  * otherwise the WFI executed inside the ROM code
 176                  * will hang the system.
 177                  */
 178                 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
 179                 ret = _omap_save_secure_sram((u32 *)
 180                                 __pa(omap3_secure_ram_storage));
 181                 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
 182                 /* Following is for error tracking, it should not happen */
 183                 if (ret) {
 184                         printk(KERN_ERR "save_secure_sram() returns %08x\n",
 185                                 ret);
 186                         while (1)
 187                                 ;
 188                 }
 189         }
 190 }
 191
 192 /*
 193  * PRCM Interrupt Handler Helper Function
 194  *
 195  * The purpose of this function is to clear any wake-up events latched
 196  * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
 197  * may occur whilst attempting to clear a PM_WKST_x register and thus
 198  * set another bit in this register. A while loop is used to ensure
 199  * that any peripheral wake-up events occurring while attempting to
 200  * clear the PM_WKST_x are detected and cleared.
 201  */
 202 static int prcm_clear_mod_irqs(s16 module, u8 regs)
 203 {
 204         u32 wkst, fclk, iclk, clken;
 205         u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
 206         u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
 207         u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
 208         u16 grpsel_off = (regs == 3) ?
 209                 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
 210         int c = 0;
 211
 212         wkst = omap2_prm_read_mod_reg(module, wkst_off);
 213         wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
 214         if (wkst) {
 215                 iclk = omap2_cm_read_mod_reg(module, iclk_off);
 216                 fclk = omap2_cm_read_mod_reg(module, fclk_off);
 217                 while (wkst) {
 218                         clken = wkst;
 219                         omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
 220                         /*
 221                          * For USBHOST, we don't know whether HOST1 or
 222                          * HOST2 woke us up, so enable both f-clocks
 223                          */
 224                         if (module == OMAP3430ES2_USBHOST_MOD)
 225                                 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
 226                         omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
 227                         omap2_prm_write_mod_reg(wkst, module, wkst_off);
 228                         wkst = omap2_prm_read_mod_reg(module, wkst_off);
 229                         c++;
 230                 }
 231                 omap2_cm_write_mod_reg(iclk, module, iclk_off);
 232                 omap2_cm_write_mod_reg(fclk, module, fclk_off);
 233         }
 234
 235         return c;
 236 }
 237
 238 static int _prcm_int_handle_wakeup(void)
 239 {
 240         int c;
 241
 242         c = prcm_clear_mod_irqs(WKUP_MOD, 1);
 243         c += prcm_clear_mod_irqs(CORE_MOD, 1);
 244         c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
 245         if (omap_rev() > OMAP3430_REV_ES1_0) {
 246                 c += prcm_clear_mod_irqs(CORE_MOD, 3);
 247                 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
 248         }
 249
 250         return c;
 251 }
 252
 253 /*
 254  * PRCM Interrupt Handler
 255  *
 256  * The PRM_IRQSTATUS_MPU register indicates if there are any pending
 257  * interrupts from the PRCM for the MPU. These bits must be cleared in
 258  * order to clear the PRCM interrupt. The PRCM interrupt handler is
 259  * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
 260  * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
 261  * register indicates that a wake-up event is pending for the MPU and
 262  * this bit can only be cleared if the all the wake-up events latched
 263  * in the various PM_WKST_x registers have been cleared. The interrupt
 264  * handler is implemented using a do-while loop so that if a wake-up
 265  * event occurred during the processing of the prcm interrupt handler
 266  * (setting a bit in the corresponding PM_WKST_x register and thus
 267  * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
 268  * this would be handled.
 269  */
 270 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
 271 {
 272         u32 irqenable_mpu, irqstatus_mpu;
 273         int c = 0;
 274
 275         irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD,
 276                                          OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 277         irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
 278                                          OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 279         irqstatus_mpu &= irqenable_mpu;
 280
 281         do {
 282                 if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
 283                                      OMAP3430_IO_ST_MASK)) {
 284                         c = _prcm_int_handle_wakeup();
 285
 286                         /*
 287                          * Is the MPU PRCM interrupt handler racing with the
 288                          * IVA2 PRCM interrupt handler ?
 289                          */
 290                         WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
 291                              "but no wakeup sources are marked\n");
 292                 } else {
 293                         /* XXX we need to expand our PRCM interrupt handler */
 294                         WARN(1, "prcm: WARNING: PRCM interrupt received, but "
 295                              "no code to handle it (%08x)\n", irqstatus_mpu);
 296                 }
 297
 298                 omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
 299                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 300
 301                 irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
 302                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 303                 irqstatus_mpu &= irqenable_mpu;
 304
 305         } while (irqstatus_mpu);
 306
 307         return IRQ_HANDLED;
 308 }
 309
 310 static void omap34xx_do_sram_idle(unsigned long save_state)
 311 {
 312         _omap_sram_idle(omap3_arm_context, save_state);
 313 }
 314
 315 void omap_sram_idle(void)
 316 {
 317         /* Variable to tell what needs to be saved and restored
 318          * in omap_sram_idle*/
 319         /* save_state = 0 => Nothing to save and restored */
 320         /* save_state = 1 => Only L1 and logic lost */
 321         /* save_state = 2 => Only L2 lost */
 322         /* save_state = 3 => L1, L2 and logic lost */
 323         int save_state = 0;
 324         int mpu_next_state = PWRDM_POWER_ON;
 325         int per_next_state = PWRDM_POWER_ON;
 326         int core_next_state = PWRDM_POWER_ON;
 327         int per_going_off;
 328         int core_prev_state, per_prev_state;
 329         u32 sdrc_pwr = 0;
 330
 331         if (!_omap_sram_idle)
 332                 return;
 333
 334         pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
 335         pwrdm_clear_all_prev_pwrst(neon_pwrdm);
 336         pwrdm_clear_all_prev_pwrst(core_pwrdm);
 337         pwrdm_clear_all_prev_pwrst(per_pwrdm);
 338
 339         mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 340         switch (mpu_next_state) {
 341         case PWRDM_POWER_ON:
 342         case PWRDM_POWER_RET:
 343                 /* No need to save context */
 344                 save_state = 0;
 345                 break;
 346         case PWRDM_POWER_OFF:
 347                 save_state = 3;
 348                 break;
 349         default:
 350                 /* Invalid state */
 351                 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
 352                 return;
 353         }
 354         pwrdm_pre_transition();
 355
 356         /* NEON control */
 357         if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
 358                 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
 359
 360         /* Enable IO-PAD and IO-CHAIN wakeups */
 361         per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
 362         core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
 363         if (omap3_has_io_wakeup() &&
 364             (per_next_state < PWRDM_POWER_ON ||
 365              core_next_state < PWRDM_POWER_ON)) {
 366                 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
 367                 omap3_enable_io_chain();
 368         }
 369
 370         /* Block console output in case it is on one of the OMAP UARTs */
 371         if (!is_suspending())
 372                 if (per_next_state < PWRDM_POWER_ON ||
 373                     core_next_state < PWRDM_POWER_ON)
 374                         if (!console_trylock())
 375                                 goto console_still_active;
 376
 377         /* PER */
 378         if (per_next_state < PWRDM_POWER_ON) {
 379                 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
 380                 omap_uart_prepare_idle(2);
 381                 omap_uart_prepare_idle(3);
 382                 omap2_gpio_prepare_for_idle(per_going_off);
 383                 if (per_next_state == PWRDM_POWER_OFF)
 384                                 omap3_per_save_context();
 385         }
 386
 387         /* CORE */
 388         if (core_next_state < PWRDM_POWER_ON) {
 389                 omap_uart_prepare_idle(0);
 390                 omap_uart_prepare_idle(1);
 391                 if (core_next_state == PWRDM_POWER_OFF) {
 392                         omap3_core_save_context();
 393                         omap3_cm_save_context();
 394                 }
 395         }
 396
 397         omap3_intc_prepare_idle();
 398
 399         /*
 400         * On EMU/HS devices ROM code restores a SRDC value
 401         * from scratchpad which has automatic self refresh on timeout
 402         * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
 403         * Hence store/restore the SDRC_POWER register here.
 404         */
 405         if (omap_rev() >= OMAP3430_REV_ES3_0 &&
 406             omap_type() != OMAP2_DEVICE_TYPE_GP &&
 407             core_next_state == PWRDM_POWER_OFF)
 408                 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
 409
 410         /*
 411          * omap3_arm_context is the location where some ARM context
 412          * get saved. The rest is placed on the stack, and restored
 413          * from there before resuming.
 414          */
 415         if (save_state == 1 || save_state == 3)
 416                 cpu_suspend(save_state, omap34xx_do_sram_idle);
 417         else
 418                 omap34xx_do_sram_idle(save_state);
 419
 420         /* Restore normal SDRC POWER settings */
 421         if (omap_rev() >= OMAP3430_REV_ES3_0 &&
 422             omap_type() != OMAP2_DEVICE_TYPE_GP &&
 423             core_next_state == PWRDM_POWER_OFF)
 424                 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
 425
 426         /* CORE */
 427         if (core_next_state < PWRDM_POWER_ON) {
 428                 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
 429                 if (core_prev_state == PWRDM_POWER_OFF) {
 430                         omap3_core_restore_context();
 431                         omap3_cm_restore_context();
 432                         omap3_sram_restore_context();
 433                         omap2_sms_restore_context();
 434                 }
 435                 omap_uart_resume_idle(0);
 436                 omap_uart_resume_idle(1);
 437                 if (core_next_state == PWRDM_POWER_OFF)
 438                         omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
 439                                                OMAP3430_GR_MOD,
 440                                                OMAP3_PRM_VOLTCTRL_OFFSET);
 441         }
 442         omap3_intc_resume_idle();
 443
 444         /* PER */
 445         if (per_next_state < PWRDM_POWER_ON) {
 446                 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
 447                 omap2_gpio_resume_after_idle();
 448                 if (per_prev_state == PWRDM_POWER_OFF)
 449                         omap3_per_restore_context();
 450                 omap_uart_resume_idle(2);
 451                 omap_uart_resume_idle(3);
 452         }
 453
 454         if (!is_suspending())
 455                 console_unlock();
 456
 457 console_still_active:
 458         /* Disable IO-PAD and IO-CHAIN wakeup */
 459         if (omap3_has_io_wakeup() &&
 460             (per_next_state < PWRDM_POWER_ON ||
 461              core_next_state < PWRDM_POWER_ON)) {
 462                 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
 463                                              PM_WKEN);
 464                 omap3_disable_io_chain();
 465         }
 466
 467         pwrdm_post_transition();
 468
 469         clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
 470 }
 471
 472 int omap3_can_sleep(void)
 473 {
 474         if (!sleep_while_idle)
 475                 return 0;
 476         if (!omap_uart_can_sleep())
 477                 return 0;
 478         return 1;
 479 }
 480
 481 static void omap3_pm_idle(void)
 482 {
 483         local_irq_disable();
 484         local_fiq_disable();
 485
 486         if (!omap3_can_sleep())
 487                 goto out;
 488
 489         if (omap_irq_pending() || need_resched())
 490                 goto out;
 491
 492         trace_power_start(POWER_CSTATE, 1, smp_processor_id());
 493         trace_cpu_idle(1, smp_processor_id());
 494
 495         omap_sram_idle();
 496
 497         trace_power_end(smp_processor_id());
 498         trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
 499
 500 out:
 501         local_fiq_enable();
 502         local_irq_enable();
 503 }
 504
 505 #ifdef CONFIG_SUSPEND
 506 static int omap3_pm_suspend(void)
 507 {
 508         struct power_state *pwrst;
 509         int state, ret = 0;
 510
 511         if (wakeup_timer_seconds || wakeup_timer_milliseconds)
 512                 omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
 513                                          wakeup_timer_milliseconds);
 514
 515         /* Read current next_pwrsts */
 516         list_for_each_entry(pwrst, &pwrst_list, node)
 517                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
 518         /* Set ones wanted by suspend */
 519         list_for_each_entry(pwrst, &pwrst_list, node) {
 520                 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
 521                         goto restore;
 522                 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
 523                         goto restore;
 524         }
 525
 526         omap_uart_prepare_suspend();
 527         omap3_intc_suspend();
 528
 529         omap_sram_idle();
 530
 531 restore:
 532         /* Restore next_pwrsts */
 533         list_for_each_entry(pwrst, &pwrst_list, node) {
 534                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
 535                 if (state > pwrst->next_state) {
 536                         printk(KERN_INFO "Powerdomain (%s) didn't enter "
 537                                "target state %d\n",
 538                                pwrst->pwrdm->name, pwrst->next_state);
 539                         ret = -1;
 540                 }
 541                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
 542         }
 543         if (ret)
 544                 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
 545         else
 546                 printk(KERN_INFO "Successfully put all powerdomains "
 547                        "to target state\n");
 548
 549         return ret;
 550 }
 551
 552 static int omap3_pm_enter(suspend_state_t unused)
 553 {
 554         int ret = 0;
 555
 556         switch (suspend_state) {
 557         case PM_SUSPEND_STANDBY:
 558         case PM_SUSPEND_MEM:
 559                 ret = omap3_pm_suspend();
 560                 break;
 561         default:
 562                 ret = -EINVAL;
 563         }
 564
 565         return ret;
 566 }
 567
 568 /* Hooks to enable / disable UART interrupts during suspend */
 569 static int omap3_pm_begin(suspend_state_t state)
 570 {
 571         disable_hlt();
 572         suspend_state = state;
 573         omap_uart_enable_irqs(0);
 574         return 0;
 575 }
 576
 577 static void omap3_pm_end(void)
 578 {
 579         suspend_state = PM_SUSPEND_ON;
 580         omap_uart_enable_irqs(1);
 581         enable_hlt();
 582         return;
 583 }
 584
 585 static const struct platform_suspend_ops omap_pm_ops = {
 586         .begin          = omap3_pm_begin,
 587         .end            = omap3_pm_end,
 588         .enter          = omap3_pm_enter,
 589         .valid          = suspend_valid_only_mem,
 590 };
 591 #endif /* CONFIG_SUSPEND */
 592
 593
 594 /**
 595  * omap3_iva_idle(): ensure IVA is in idle so it can be put into
 596  *                   retention
 597  *
 598  * In cases where IVA2 is activated by bootcode, it may prevent
 599  * full-chip retention or off-mode because it is not idle.  This
 600  * function forces the IVA2 into idle state so it can go
 601  * into retention/off and thus allow full-chip retention/off.
 602  *
 603  **/
 604 static void __init omap3_iva_idle(void)
 605 {
 606         /* ensure IVA2 clock is disabled */
 607         omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 608
 609         /* if no clock activity, nothing else to do */
 610         if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
 611               OMAP3430_CLKACTIVITY_IVA2_MASK))
 612                 return;
 613
 614         /* Reset IVA2 */
 615         omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
 616                           OMAP3430_RST2_IVA2_MASK |
 617                           OMAP3430_RST3_IVA2_MASK,
 618                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 619
 620         /* Enable IVA2 clock */
 621         omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
 622                          OMAP3430_IVA2_MOD, CM_FCLKEN);
 623
 624         /* Set IVA2 boot mode to 'idle' */
 625         omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
 626                          OMAP343X_CONTROL_IVA2_BOOTMOD);
 627
 628         /* Un-reset IVA2 */
 629         omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 630
 631         /* Disable IVA2 clock */
 632         omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 633
 634         /* Reset IVA2 */
 635         omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
 636                           OMAP3430_RST2_IVA2_MASK |
 637                           OMAP3430_RST3_IVA2_MASK,
 638                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 639 }
 640
 641 static void __init omap3_d2d_idle(void)
 642 {
 643         u16 mask, padconf;
 644
 645         /* In a stand alone OMAP3430 where there is not a stacked
 646          * modem for the D2D Idle Ack and D2D MStandby must be pulled
 647          * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
 648          * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
 649         mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
 650         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
 651         padconf |= mask;
 652         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
 653
 654         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
 655         padconf |= mask;
 656         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
 657
 658         /* reset modem */
 659         omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
 660                           OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
 661                           CORE_MOD, OMAP2_RM_RSTCTRL);
 662         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
 663 }
 664
 665 static void __init prcm_setup_regs(void)
 666 {
 667         u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
 668                                         OMAP3630_EN_UART4_MASK : 0;
 669         u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
 670                                         OMAP3630_GRPSEL_UART4_MASK : 0;
 671
 672         /* XXX This should be handled by hwmod code or SCM init code */
 673         omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
 674
 675         /*
 676          * Enable control of expternal oscillator through
 677          * sys_clkreq. In the long run clock framework should
 678          * take care of this.
 679          */
 680         omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
 681                              1 << OMAP_AUTOEXTCLKMODE_SHIFT,
 682                              OMAP3430_GR_MOD,
 683                              OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 684
 685         /* setup wakup source */
 686         omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
 687                           OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
 688                           WKUP_MOD, PM_WKEN);
 689         /* No need to write EN_IO, that is always enabled */
 690         omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
 691                           OMAP3430_GRPSEL_GPT1_MASK |
 692                           OMAP3430_GRPSEL_GPT12_MASK,
 693                           WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
 694         /* For some reason IO doesn't generate wakeup event even if
 695          * it is selected to mpu wakeup goup */
 696         omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
 697                           OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 698
 699         /* Enable PM_WKEN to support DSS LPR */
 700         omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
 701                                 OMAP3430_DSS_MOD, PM_WKEN);
 702
 703         /* Enable wakeups in PER */
 704         omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
 705                           OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
 706                           OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
 707                           OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
 708                           OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
 709                           OMAP3430_EN_MCBSP4_MASK,
 710                           OMAP3430_PER_MOD, PM_WKEN);
 711         /* and allow them to wake up MPU */
 712         omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
 713                           OMAP3430_GRPSEL_GPIO2_MASK |
 714                           OMAP3430_GRPSEL_GPIO3_MASK |
 715                           OMAP3430_GRPSEL_GPIO4_MASK |
 716                           OMAP3430_GRPSEL_GPIO5_MASK |
 717                           OMAP3430_GRPSEL_GPIO6_MASK |
 718                           OMAP3430_GRPSEL_UART3_MASK |
 719                           OMAP3430_GRPSEL_MCBSP2_MASK |
 720                           OMAP3430_GRPSEL_MCBSP3_MASK |
 721                           OMAP3430_GRPSEL_MCBSP4_MASK,
 722                           OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
 723
 724         /* Don't attach IVA interrupts */
 725         omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 726         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
 727         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 728         omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 729
 730         /* Clear any pending 'reset' flags */
 731         omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
 732         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
 733         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
 734         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
 735         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
 736         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
 737         omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
 738
 739         /* Clear any pending PRCM interrupts */
 740         omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 741
 742         omap3_iva_idle();
 743         omap3_d2d_idle();
 744 }
 745
 746 void omap3_pm_off_mode_enable(int enable)
 747 {
 748         struct power_state *pwrst;
 749         u32 state;
 750
 751         if (enable)
 752                 state = PWRDM_POWER_OFF;
 753         else
 754                 state = PWRDM_POWER_RET;
 755
 756         list_for_each_entry(pwrst, &pwrst_list, node) {
 757                 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
 758                                 pwrst->pwrdm == core_pwrdm &&
 759                                 state == PWRDM_POWER_OFF) {
 760                         pwrst->next_state = PWRDM_POWER_RET;
 761                         pr_warn("%s: Core OFF disabled due to errata i583\n",
 762                                 __func__);
 763                 } else {
 764                         pwrst->next_state = state;
 765                 }
 766                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 767         }
 768 }
 769
 770 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
 771 {
 772         struct power_state *pwrst;
 773
 774         list_for_each_entry(pwrst, &pwrst_list, node) {
 775                 if (pwrst->pwrdm == pwrdm)
 776                         return pwrst->next_state;
 777         }
 778         return -EINVAL;
 779 }
 780
 781 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
 782 {
 783         struct power_state *pwrst;
 784
 785         list_for_each_entry(pwrst, &pwrst_list, node) {
 786                 if (pwrst->pwrdm == pwrdm) {
 787                         pwrst->next_state = state;
 788                         return 0;
 789                 }
 790         }
 791         return -EINVAL;
 792 }
 793
 794 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 795 {
 796         struct power_state *pwrst;
 797
 798         if (!pwrdm->pwrsts)
 799                 return 0;
 800
 801         pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
 802         if (!pwrst)
 803                 return -ENOMEM;
 804         pwrst->pwrdm = pwrdm;
 805         pwrst->next_state = PWRDM_POWER_RET;
 806         list_add(&pwrst->node, &pwrst_list);
 807
 808         if (pwrdm_has_hdwr_sar(pwrdm))
 809                 pwrdm_enable_hdwr_sar(pwrdm);
 810
 811         return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 812 }
 813
 814 /*
 815  * Enable hw supervised mode for all clockdomains if it's
 816  * supported. Initiate sleep transition for other clockdomains, if
 817  * they are not used
 818  */
 819 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
 820 {
 821         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
 822                 clkdm_allow_idle(clkdm);
 823         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
 824                  atomic_read(&clkdm->usecount) == 0)
 825                 clkdm_sleep(clkdm);
 826         return 0;
 827 }
 828
 829 void omap_push_sram_idle(void)
 830 {
 831         _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
 832                                         omap34xx_cpu_suspend_sz);
 833         if (omap_type() != OMAP2_DEVICE_TYPE_GP)
 834                 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
 835                                 save_secure_ram_context_sz);
 836 }
 837
 838 static void __init pm_errata_configure(void)
 839 {
 840         if (cpu_is_omap3630()) {
 841                 pm34xx_errata |= PM_RTA_ERRATUM_i608;
 842                 /* Enable the l2 cache toggling in sleep logic */
 843                 enable_omap3630_toggle_l2_on_restore();
 844                 if (omap_rev() < OMAP3630_REV_ES1_2)
 845                         pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
 846         }
 847 }
 848
 849 static int __init omap3_pm_init(void)
 850 {
 851         struct power_state *pwrst, *tmp;
 852         struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
 853         int ret;
 854
 855         if (!cpu_is_omap34xx())
 856                 return -ENODEV;
 857
 858         pm_errata_configure();
 859
 860         /* XXX prcm_setup_regs needs to be before enabling hw
 861          * supervised mode for powerdomains */
 862         prcm_setup_regs();
 863
 864         ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
 865                           (irq_handler_t)prcm_interrupt_handler,
 866                           IRQF_DISABLED, "prcm", NULL);
 867         if (ret) {
 868                 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
 869                        INT_34XX_PRCM_MPU_IRQ);
 870                 goto err1;
 871         }
 872
 873         ret = pwrdm_for_each(pwrdms_setup, NULL);
 874         if (ret) {
 875                 printk(KERN_ERR "Failed to setup powerdomains\n");
 876                 goto err2;
 877         }
 878
 879         (void) clkdm_for_each(clkdms_setup, NULL);
 880
 881         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 882         if (mpu_pwrdm == NULL) {
 883                 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
 884                 goto err2;
 885         }
 886
 887         neon_pwrdm = pwrdm_lookup("neon_pwrdm");
 888         per_pwrdm = pwrdm_lookup("per_pwrdm");
 889         core_pwrdm = pwrdm_lookup("core_pwrdm");
 890         cam_pwrdm = pwrdm_lookup("cam_pwrdm");
 891
 892         neon_clkdm = clkdm_lookup("neon_clkdm");
 893         mpu_clkdm = clkdm_lookup("mpu_clkdm");
 894         per_clkdm = clkdm_lookup("per_clkdm");
 895         core_clkdm = clkdm_lookup("core_clkdm");
 896
 897         omap_push_sram_idle();
 898 #ifdef CONFIG_SUSPEND
 899         suspend_set_ops(&omap_pm_ops);
 900 #endif /* CONFIG_SUSPEND */
 901
 902         pm_idle = omap3_pm_idle;
 903         omap3_idle_init();
 904
 905         /*
 906          * RTA is disabled during initialization as per erratum i608
 907          * it is safer to disable RTA by the bootloader, but we would like
 908          * to be doubly sure here and prevent any mishaps.
 909          */
 910         if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
 911                 omap3630_ctrl_disable_rta();
 912
 913         clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
 914         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 915                 omap3_secure_ram_storage =
 916                         kmalloc(0x803F, GFP_KERNEL);
 917                 if (!omap3_secure_ram_storage)
 918                         printk(KERN_ERR "Memory allocation failed when"
 919                                         "allocating for secure sram context\n");
 920
 921                 local_irq_disable();
 922                 local_fiq_disable();
 923
 924                 omap_dma_global_context_save();
 925                 omap3_save_secure_ram_context();
 926                 omap_dma_global_context_restore();
 927
 928                 local_irq_enable();
 929                 local_fiq_enable();
 930         }
 931
 932         omap3_save_scratchpad_contents();
 933 err1:
 934         return ret;
 935 err2:
 936         free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
 937         list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
 938                 list_del(&pwrst->node);
 939                 kfree(pwrst);
 940         }
 941         return ret;
 942 }
 943
 944 late_initcall(omap3_pm_init);