arch/arm/mach-omap2/omap_twl.c

   1 /**
   2  * OMAP and TWL PMIC specific intializations.
   3  *
   4  * Copyright (C) 2010 Texas Instruments Incorporated.
   5  * Thara Gopinath
   6  * Copyright (C) 2009 Texas Instruments Incorporated.
   7  * Nishanth Menon
   8  * Copyright (C) 2009 Nokia Corporation
   9  * Paul Walmsley
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/kernel.h>
  19 #include <linux/i2c/twl.h>
  20
  21 #include "voltage.h"
  22
  23 #include "pm.h"
  24
  25 #define OMAP3_SRI2C_SLAVE_ADDR          0x12
  26 #define OMAP3_VDD_MPU_SR_CONTROL_REG    0x00
  27 #define OMAP3_VDD_CORE_SR_CONTROL_REG   0x01
  28 #define OMAP3_VP_CONFIG_ERROROFFSET     0x00
  29 #define OMAP3_VP_VSTEPMIN_VSTEPMIN      0x1
  30 #define OMAP3_VP_VSTEPMAX_VSTEPMAX      0x04
  31 #define OMAP3_VP_VLIMITTO_TIMEOUT_US    200
  32
  33 #define OMAP3430_VP1_VLIMITTO_VDDMIN    0x14
  34 #define OMAP3430_VP1_VLIMITTO_VDDMAX    0x42
  35 #define OMAP3430_VP2_VLIMITTO_VDDMIN    0x18
  36 #define OMAP3430_VP2_VLIMITTO_VDDMAX    0x2c
  37
  38 #define OMAP3630_VP1_VLIMITTO_VDDMIN    0x18
  39 #define OMAP3630_VP1_VLIMITTO_VDDMAX    0x3c
  40 #define OMAP3630_VP2_VLIMITTO_VDDMIN    0x18
  41 #define OMAP3630_VP2_VLIMITTO_VDDMAX    0x30
  42
  43 #define OMAP4_SRI2C_SLAVE_ADDR          0x12
  44 #define OMAP4_VDD_MPU_SR_VOLT_REG       0x55
  45 #define OMAP4_VDD_IVA_SR_VOLT_REG       0x5B
  46 #define OMAP4_VDD_CORE_SR_VOLT_REG      0x61
  47
  48 #define OMAP4_VP_CONFIG_ERROROFFSET     0x00
  49 #define OMAP4_VP_VSTEPMIN_VSTEPMIN      0x01
  50 #define OMAP4_VP_VSTEPMAX_VSTEPMAX      0x04
  51 #define OMAP4_VP_VLIMITTO_TIMEOUT_US    200
  52
  53 #define OMAP4_VP_MPU_VLIMITTO_VDDMIN    0xA
  54 #define OMAP4_VP_MPU_VLIMITTO_VDDMAX    0x39
  55 #define OMAP4_VP_IVA_VLIMITTO_VDDMIN    0xA
  56 #define OMAP4_VP_IVA_VLIMITTO_VDDMAX    0x2D
  57 #define OMAP4_VP_CORE_VLIMITTO_VDDMIN   0xA
  58 #define OMAP4_VP_CORE_VLIMITTO_VDDMAX   0x28
  59
  60 static bool is_offset_valid;
  61 static u8 smps_offset;
  62 /*
  63  * Flag to ensure Smartreflex bit in TWL
  64  * being cleared in board file is not overwritten.
  65  */
  66 static bool __initdata twl_sr_enable_autoinit;
  67
  68 #define TWL4030_DCDC_GLOBAL_CFG        0x06
  69 #define REG_SMPS_OFFSET         0xE0
  70 #define SMARTREFLEX_ENABLE     BIT(3)
  71
  72 static unsigned long twl4030_vsel_to_uv(const u8 vsel)
  73 {
  74         return (((vsel * 125) + 6000)) * 100;
  75 }
  76
  77 static u8 twl4030_uv_to_vsel(unsigned long uv)
  78 {
  79         return DIV_ROUND_UP(uv - 600000, 12500);
  80 }
  81
  82 static unsigned long twl6030_vsel_to_uv(const u8 vsel)
  83 {
  84         /*
  85          * In TWL6030 depending on the value of SMPS_OFFSET
  86          * efuse register the voltage range supported in
  87          * standard mode can be either between 0.6V - 1.3V or
  88          * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
  89          * is programmed to all 0's where as starting from
  90          * TWL6030 ES1.1 the efuse is programmed to 1
  91          */
  92         if (!is_offset_valid) {
  93                 twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,
  94                                 REG_SMPS_OFFSET);
  95                 is_offset_valid = true;
  96         }
  97
  98         /*
  99          * There is no specific formula for voltage to vsel
 100          * conversion above 1.3V. There are special hardcoded
 101          * values for voltages above 1.3V. Currently we are
 102          * hardcoding only for 1.35 V which is used for 1GH OPP for
 103          * OMAP4430.
 104          */
 105         if (vsel == 0x3A)
 106                 return 1350000;
 107
 108         if (smps_offset & 0x8)
 109                 return ((((vsel - 1) * 1266) + 70900)) * 10;
 110         else
 111                 return ((((vsel - 1) * 1266) + 60770)) * 10;
 112 }
 113
 114 static u8 twl6030_uv_to_vsel(unsigned long uv)
 115 {
 116         /*
 117          * In TWL6030 depending on the value of SMPS_OFFSET
 118          * efuse register the voltage range supported in
 119          * standard mode can be either between 0.6V - 1.3V or
 120          * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
 121          * is programmed to all 0's where as starting from
 122          * TWL6030 ES1.1 the efuse is programmed to 1
 123          */
 124         if (!is_offset_valid) {
 125                 twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,
 126                                 REG_SMPS_OFFSET);
 127                 is_offset_valid = true;
 128         }
 129
 130         /*
 131          * There is no specific formula for voltage to vsel
 132          * conversion above 1.3V. There are special hardcoded
 133          * values for voltages above 1.3V. Currently we are
 134          * hardcoding only for 1.35 V which is used for 1GH OPP for
 135          * OMAP4430.
 136          */
 137         if (uv > twl6030_vsel_to_uv(0x39)) {
 138                 if (uv == 1350000)
 139                         return 0x3A;
 140                 pr_err("%s:OUT OF RANGE! non mapped vsel for %ld Vs max %ld\n",
 141                         __func__, uv, twl6030_vsel_to_uv(0x39));
 142                 return 0x3A;
 143         }
 144
 145         if (smps_offset & 0x8)
 146                 return DIV_ROUND_UP(uv - 709000, 12660) + 1;
 147         else
 148                 return DIV_ROUND_UP(uv - 607700, 12660) + 1;
 149 }
 150
 151 static struct omap_voltdm_pmic omap3_mpu_pmic = {
 152         .slew_rate              = 4000,
 153         .step_size              = 12500,
 154         .on_volt                = 1200000,
 155         .onlp_volt              = 1000000,
 156         .ret_volt               = 975000,
 157         .off_volt               = 600000,
 158         .volt_setup_time        = 0xfff,
 159         .vp_erroroffset         = OMAP3_VP_CONFIG_ERROROFFSET,
 160         .vp_vstepmin            = OMAP3_VP_VSTEPMIN_VSTEPMIN,
 161         .vp_vstepmax            = OMAP3_VP_VSTEPMAX_VSTEPMAX,
 162         .vp_vddmin              = OMAP3430_VP1_VLIMITTO_VDDMIN,
 163         .vp_vddmax              = OMAP3430_VP1_VLIMITTO_VDDMAX,
 164         .vp_timeout_us          = OMAP3_VP_VLIMITTO_TIMEOUT_US,
 165         .i2c_slave_addr         = OMAP3_SRI2C_SLAVE_ADDR,
 166         .volt_reg_addr          = OMAP3_VDD_MPU_SR_CONTROL_REG,
 167         .i2c_high_speed         = true,
 168         .vsel_to_uv             = twl4030_vsel_to_uv,
 169         .uv_to_vsel             = twl4030_uv_to_vsel,
 170 };
 171
 172 static struct omap_voltdm_pmic omap3_core_pmic = {
 173         .slew_rate              = 4000,
 174         .step_size              = 12500,
 175         .on_volt                = 1200000,
 176         .onlp_volt              = 1000000,
 177         .ret_volt               = 975000,
 178         .off_volt               = 600000,
 179         .volt_setup_time        = 0xfff,
 180         .vp_erroroffset         = OMAP3_VP_CONFIG_ERROROFFSET,
 181         .vp_vstepmin            = OMAP3_VP_VSTEPMIN_VSTEPMIN,
 182         .vp_vstepmax            = OMAP3_VP_VSTEPMAX_VSTEPMAX,
 183         .vp_vddmin              = OMAP3430_VP2_VLIMITTO_VDDMIN,
 184         .vp_vddmax              = OMAP3430_VP2_VLIMITTO_VDDMAX,
 185         .vp_timeout_us          = OMAP3_VP_VLIMITTO_TIMEOUT_US,
 186         .i2c_slave_addr         = OMAP3_SRI2C_SLAVE_ADDR,
 187         .volt_reg_addr          = OMAP3_VDD_CORE_SR_CONTROL_REG,
 188         .i2c_high_speed         = true,
 189         .vsel_to_uv             = twl4030_vsel_to_uv,
 190         .uv_to_vsel             = twl4030_uv_to_vsel,
 191 };
 192
 193 static struct omap_voltdm_pmic omap4_mpu_pmic = {
 194         .slew_rate              = 4000,
 195         .step_size              = 12660,
 196         .on_volt                = 1350000,
 197         .onlp_volt              = 1350000,
 198         .ret_volt               = 837500,
 199         .off_volt               = 600000,
 200         .volt_setup_time        = 0,
 201         .vp_erroroffset         = OMAP4_VP_CONFIG_ERROROFFSET,
 202         .vp_vstepmin            = OMAP4_VP_VSTEPMIN_VSTEPMIN,
 203         .vp_vstepmax            = OMAP4_VP_VSTEPMAX_VSTEPMAX,
 204         .vp_vddmin              = OMAP4_VP_MPU_VLIMITTO_VDDMIN,
 205         .vp_vddmax              = OMAP4_VP_MPU_VLIMITTO_VDDMAX,
 206         .vp_timeout_us          = OMAP4_VP_VLIMITTO_TIMEOUT_US,
 207         .i2c_slave_addr         = OMAP4_SRI2C_SLAVE_ADDR,
 208         .volt_reg_addr          = OMAP4_VDD_MPU_SR_VOLT_REG,
 209         .i2c_high_speed         = true,
 210         .vsel_to_uv             = twl6030_vsel_to_uv,
 211         .uv_to_vsel             = twl6030_uv_to_vsel,
 212 };
 213
 214 static struct omap_voltdm_pmic omap4_iva_pmic = {
 215         .slew_rate              = 4000,
 216         .step_size              = 12660,
 217         .on_volt                = 1100000,
 218         .onlp_volt              = 1100000,
 219         .ret_volt               = 837500,
 220         .off_volt               = 600000,
 221         .volt_setup_time        = 0,
 222         .vp_erroroffset         = OMAP4_VP_CONFIG_ERROROFFSET,
 223         .vp_vstepmin            = OMAP4_VP_VSTEPMIN_VSTEPMIN,
 224         .vp_vstepmax            = OMAP4_VP_VSTEPMAX_VSTEPMAX,
 225         .vp_vddmin              = OMAP4_VP_IVA_VLIMITTO_VDDMIN,
 226         .vp_vddmax              = OMAP4_VP_IVA_VLIMITTO_VDDMAX,
 227         .vp_timeout_us          = OMAP4_VP_VLIMITTO_TIMEOUT_US,
 228         .i2c_slave_addr         = OMAP4_SRI2C_SLAVE_ADDR,
 229         .volt_reg_addr          = OMAP4_VDD_IVA_SR_VOLT_REG,
 230         .i2c_high_speed         = true,
 231         .vsel_to_uv             = twl6030_vsel_to_uv,
 232         .uv_to_vsel             = twl6030_uv_to_vsel,
 233 };
 234
 235 static struct omap_voltdm_pmic omap4_core_pmic = {
 236         .slew_rate              = 4000,
 237         .step_size              = 12660,
 238         .on_volt                = 1100000,
 239         .onlp_volt              = 1100000,
 240         .ret_volt               = 837500,
 241         .off_volt               = 600000,
 242         .volt_setup_time        = 0,
 243         .vp_erroroffset         = OMAP4_VP_CONFIG_ERROROFFSET,
 244         .vp_vstepmin            = OMAP4_VP_VSTEPMIN_VSTEPMIN,
 245         .vp_vstepmax            = OMAP4_VP_VSTEPMAX_VSTEPMAX,
 246         .vp_vddmin              = OMAP4_VP_CORE_VLIMITTO_VDDMIN,
 247         .vp_vddmax              = OMAP4_VP_CORE_VLIMITTO_VDDMAX,
 248         .vp_timeout_us          = OMAP4_VP_VLIMITTO_TIMEOUT_US,
 249         .i2c_slave_addr         = OMAP4_SRI2C_SLAVE_ADDR,
 250         .volt_reg_addr          = OMAP4_VDD_CORE_SR_VOLT_REG,
 251         .vsel_to_uv             = twl6030_vsel_to_uv,
 252         .uv_to_vsel             = twl6030_uv_to_vsel,
 253 };
 254
 255 int __init omap4_twl_init(void)
 256 {
 257         struct voltagedomain *voltdm;
 258
 259         if (!cpu_is_omap44xx())
 260                 return -ENODEV;
 261
 262         voltdm = voltdm_lookup("mpu");
 263         omap_voltage_register_pmic(voltdm, &omap4_mpu_pmic);
 264
 265         voltdm = voltdm_lookup("iva");
 266         omap_voltage_register_pmic(voltdm, &omap4_iva_pmic);
 267
 268         voltdm = voltdm_lookup("core");
 269         omap_voltage_register_pmic(voltdm, &omap4_core_pmic);
 270
 271         return 0;
 272 }
 273
 274 int __init omap3_twl_init(void)
 275 {
 276         struct voltagedomain *voltdm;
 277
 278         if (!cpu_is_omap34xx())
 279                 return -ENODEV;
 280
 281         if (cpu_is_omap3630()) {
 282                 omap3_mpu_pmic.vp_vddmin = OMAP3630_VP1_VLIMITTO_VDDMIN;
 283                 omap3_mpu_pmic.vp_vddmax = OMAP3630_VP1_VLIMITTO_VDDMAX;
 284                 omap3_core_pmic.vp_vddmin = OMAP3630_VP2_VLIMITTO_VDDMIN;
 285                 omap3_core_pmic.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;
 286         }
 287
 288         /*
 289          * The smartreflex bit on twl4030 specifies if the setting of voltage
 290          * is done over the I2C_SR path. Since this setting is independent of
 291          * the actual usage of smartreflex AVS module, we enable TWL SR bit
 292          * by default irrespective of whether smartreflex AVS module is enabled
 293          * on the OMAP side or not. This is because without this bit enabled,
 294          * the voltage scaling through vp forceupdate/bypass mechanism of
 295          * voltage scaling will not function on TWL over I2C_SR.
 296          */
 297         if (!twl_sr_enable_autoinit)
 298                 omap3_twl_set_sr_bit(true);
 299
 300         voltdm = voltdm_lookup("mpu_iva");
 301         omap_voltage_register_pmic(voltdm, &omap3_mpu_pmic);
 302
 303         voltdm = voltdm_lookup("core");
 304         omap_voltage_register_pmic(voltdm, &omap3_core_pmic);
 305
 306         return 0;
 307 }
 308
 309 /**
 310  * omap3_twl_set_sr_bit() - Set/Clear SR bit on TWL
 311  * @enable: enable SR mode in twl or not
 312  *
 313  * If 'enable' is true, enables Smartreflex bit on TWL 4030 to make sure
 314  * voltage scaling through OMAP SR works. Else, the smartreflex bit
 315  * on twl4030 is cleared as there are platforms which use OMAP3 and T2 but
 316  * use Synchronized Scaling Hardware Strategy (ENABLE_VMODE=1) and Direct
 317  * Strategy Software Scaling Mode (ENABLE_VMODE=0), for setting the voltages,
 318  * in those scenarios this bit is to be cleared (enable = false).
 319  *
 320  * Returns 0 on success, error is returned if I2C read/write fails.
 321  */
 322 int __init omap3_twl_set_sr_bit(bool enable)
 323 {
 324         u8 temp;
 325         int ret;
 326         if (twl_sr_enable_autoinit)
 327                 pr_warning("%s: unexpected multiple calls\n", __func__);
 328
 329         ret = twl_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &temp,
 330                                         TWL4030_DCDC_GLOBAL_CFG);
 331         if (ret)
 332                 goto err;
 333
 334         if (enable)
 335                 temp |= SMARTREFLEX_ENABLE;
 336         else
 337                 temp &= ~SMARTREFLEX_ENABLE;
 338
 339         ret = twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, temp,
 340                                 TWL4030_DCDC_GLOBAL_CFG);
 341         if (!ret) {
 342                 twl_sr_enable_autoinit = true;
 343                 return 0;
 344         }
 345 err:
 346         pr_err("%s: Error access to TWL4030 (%d)\n", __func__, ret);
 347         return ret;
 348 }