2 * Hardware modules present on the OMAP44xx chips
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
23 #include <plat/omap_hwmod.h>
25 #include <plat/gpio.h>
28 #include "omap_hwmod_common_data.h"
33 #include "prm-regbits-44xx.h"
36 /* Base offset for all OMAP4 interrupts external to MPUSS */
37 #define OMAP44XX_IRQ_GIC_START 32
39 /* Base offset for all OMAP4 dma requests */
40 #define OMAP44XX_DMA_REQ_START 1
42 /* Backward references (IPs with Bus Master capability) */
43 static struct omap_hwmod omap44xx_dma_system_hwmod;
44 static struct omap_hwmod omap44xx_dmm_hwmod;
45 static struct omap_hwmod omap44xx_dsp_hwmod;
46 static struct omap_hwmod omap44xx_emif_fw_hwmod;
47 static struct omap_hwmod omap44xx_iva_hwmod;
48 static struct omap_hwmod omap44xx_l3_instr_hwmod;
49 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
50 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
51 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
52 static struct omap_hwmod omap44xx_l4_abe_hwmod;
53 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
54 static struct omap_hwmod omap44xx_l4_per_hwmod;
55 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
56 static struct omap_hwmod omap44xx_mpu_hwmod;
57 static struct omap_hwmod omap44xx_mpu_private_hwmod;
60 * Interconnects omap_hwmod structures
61 * hwmods that compose the global OMAP interconnect
68 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
72 /* dmm interface data */
73 /* l3_main_1 -> dmm */
74 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
75 .master = &omap44xx_l3_main_1_hwmod,
76 .slave = &omap44xx_dmm_hwmod,
78 .user = OCP_USER_SDMA,
81 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
83 .pa_start = 0x4e000000,
90 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
91 .master = &omap44xx_mpu_hwmod,
92 .slave = &omap44xx_dmm_hwmod,
94 .addr = omap44xx_dmm_addrs,
95 .addr_cnt = ARRAY_SIZE(omap44xx_dmm_addrs),
100 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
101 &omap44xx_l3_main_1__dmm,
105 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
106 { .irq = 113 + OMAP44XX_IRQ_GIC_START },
109 static struct omap_hwmod omap44xx_dmm_hwmod = {
111 .class = &omap44xx_dmm_hwmod_class,
112 .slaves = omap44xx_dmm_slaves,
113 .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
114 .mpu_irqs = omap44xx_dmm_irqs,
115 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmm_irqs),
116 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
121 * instance(s): emif_fw
123 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
127 /* emif_fw interface data */
129 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
130 .master = &omap44xx_dmm_hwmod,
131 .slave = &omap44xx_emif_fw_hwmod,
133 .user = OCP_USER_MPU | OCP_USER_SDMA,
136 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
138 .pa_start = 0x4a20c000,
139 .pa_end = 0x4a20c0ff,
140 .flags = ADDR_TYPE_RT
144 /* l4_cfg -> emif_fw */
145 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
146 .master = &omap44xx_l4_cfg_hwmod,
147 .slave = &omap44xx_emif_fw_hwmod,
149 .addr = omap44xx_emif_fw_addrs,
150 .addr_cnt = ARRAY_SIZE(omap44xx_emif_fw_addrs),
151 .user = OCP_USER_MPU,
154 /* emif_fw slave ports */
155 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
156 &omap44xx_dmm__emif_fw,
157 &omap44xx_l4_cfg__emif_fw,
160 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
162 .class = &omap44xx_emif_fw_hwmod_class,
163 .slaves = omap44xx_emif_fw_slaves,
164 .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves),
165 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
170 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
172 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
176 /* l3_instr interface data */
177 /* iva -> l3_instr */
178 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
179 .master = &omap44xx_iva_hwmod,
180 .slave = &omap44xx_l3_instr_hwmod,
182 .user = OCP_USER_MPU | OCP_USER_SDMA,
185 /* l3_main_3 -> l3_instr */
186 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
187 .master = &omap44xx_l3_main_3_hwmod,
188 .slave = &omap44xx_l3_instr_hwmod,
190 .user = OCP_USER_MPU | OCP_USER_SDMA,
193 /* l3_instr slave ports */
194 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
195 &omap44xx_iva__l3_instr,
196 &omap44xx_l3_main_3__l3_instr,
199 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
201 .class = &omap44xx_l3_hwmod_class,
202 .slaves = omap44xx_l3_instr_slaves,
203 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves),
204 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
207 /* l3_main_1 interface data */
208 /* dsp -> l3_main_1 */
209 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
210 .master = &omap44xx_dsp_hwmod,
211 .slave = &omap44xx_l3_main_1_hwmod,
213 .user = OCP_USER_MPU | OCP_USER_SDMA,
216 /* l3_main_2 -> l3_main_1 */
217 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
218 .master = &omap44xx_l3_main_2_hwmod,
219 .slave = &omap44xx_l3_main_1_hwmod,
221 .user = OCP_USER_MPU | OCP_USER_SDMA,
224 /* l4_cfg -> l3_main_1 */
225 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
226 .master = &omap44xx_l4_cfg_hwmod,
227 .slave = &omap44xx_l3_main_1_hwmod,
229 .user = OCP_USER_MPU | OCP_USER_SDMA,
232 /* mpu -> l3_main_1 */
233 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
234 .master = &omap44xx_mpu_hwmod,
235 .slave = &omap44xx_l3_main_1_hwmod,
237 .user = OCP_USER_MPU | OCP_USER_SDMA,
240 /* l3_main_1 slave ports */
241 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
242 &omap44xx_dsp__l3_main_1,
243 &omap44xx_l3_main_2__l3_main_1,
244 &omap44xx_l4_cfg__l3_main_1,
245 &omap44xx_mpu__l3_main_1,
248 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
250 .class = &omap44xx_l3_hwmod_class,
251 .slaves = omap44xx_l3_main_1_slaves,
252 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
253 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
256 /* l3_main_2 interface data */
257 /* iva -> l3_main_2 */
258 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
259 .master = &omap44xx_iva_hwmod,
260 .slave = &omap44xx_l3_main_2_hwmod,
262 .user = OCP_USER_MPU | OCP_USER_SDMA,
265 /* l3_main_1 -> l3_main_2 */
266 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
267 .master = &omap44xx_l3_main_1_hwmod,
268 .slave = &omap44xx_l3_main_2_hwmod,
270 .user = OCP_USER_MPU | OCP_USER_SDMA,
273 /* dma_system -> l3_main_2 */
274 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
275 .master = &omap44xx_dma_system_hwmod,
276 .slave = &omap44xx_l3_main_2_hwmod,
278 .user = OCP_USER_MPU | OCP_USER_SDMA,
281 /* l4_cfg -> l3_main_2 */
282 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
283 .master = &omap44xx_l4_cfg_hwmod,
284 .slave = &omap44xx_l3_main_2_hwmod,
286 .user = OCP_USER_MPU | OCP_USER_SDMA,
289 /* l3_main_2 slave ports */
290 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
291 &omap44xx_dma_system__l3_main_2,
292 &omap44xx_iva__l3_main_2,
293 &omap44xx_l3_main_1__l3_main_2,
294 &omap44xx_l4_cfg__l3_main_2,
297 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
299 .class = &omap44xx_l3_hwmod_class,
300 .slaves = omap44xx_l3_main_2_slaves,
301 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
302 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
305 /* l3_main_3 interface data */
306 /* l3_main_1 -> l3_main_3 */
307 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
308 .master = &omap44xx_l3_main_1_hwmod,
309 .slave = &omap44xx_l3_main_3_hwmod,
311 .user = OCP_USER_MPU | OCP_USER_SDMA,
314 /* l3_main_2 -> l3_main_3 */
315 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
316 .master = &omap44xx_l3_main_2_hwmod,
317 .slave = &omap44xx_l3_main_3_hwmod,
319 .user = OCP_USER_MPU | OCP_USER_SDMA,
322 /* l4_cfg -> l3_main_3 */
323 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
324 .master = &omap44xx_l4_cfg_hwmod,
325 .slave = &omap44xx_l3_main_3_hwmod,
327 .user = OCP_USER_MPU | OCP_USER_SDMA,
330 /* l3_main_3 slave ports */
331 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
332 &omap44xx_l3_main_1__l3_main_3,
333 &omap44xx_l3_main_2__l3_main_3,
334 &omap44xx_l4_cfg__l3_main_3,
337 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
339 .class = &omap44xx_l3_hwmod_class,
340 .slaves = omap44xx_l3_main_3_slaves,
341 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
342 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
347 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
349 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
353 /* l4_abe interface data */
355 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
356 .master = &omap44xx_dsp_hwmod,
357 .slave = &omap44xx_l4_abe_hwmod,
358 .clk = "ocp_abe_iclk",
359 .user = OCP_USER_MPU | OCP_USER_SDMA,
362 /* l3_main_1 -> l4_abe */
363 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
364 .master = &omap44xx_l3_main_1_hwmod,
365 .slave = &omap44xx_l4_abe_hwmod,
367 .user = OCP_USER_MPU | OCP_USER_SDMA,
371 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
372 .master = &omap44xx_mpu_hwmod,
373 .slave = &omap44xx_l4_abe_hwmod,
374 .clk = "ocp_abe_iclk",
375 .user = OCP_USER_MPU | OCP_USER_SDMA,
378 /* l4_abe slave ports */
379 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
380 &omap44xx_dsp__l4_abe,
381 &omap44xx_l3_main_1__l4_abe,
382 &omap44xx_mpu__l4_abe,
385 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
387 .class = &omap44xx_l4_hwmod_class,
388 .slaves = omap44xx_l4_abe_slaves,
389 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves),
390 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
393 /* l4_cfg interface data */
394 /* l3_main_1 -> l4_cfg */
395 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
396 .master = &omap44xx_l3_main_1_hwmod,
397 .slave = &omap44xx_l4_cfg_hwmod,
399 .user = OCP_USER_MPU | OCP_USER_SDMA,
402 /* l4_cfg slave ports */
403 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
404 &omap44xx_l3_main_1__l4_cfg,
407 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
409 .class = &omap44xx_l4_hwmod_class,
410 .slaves = omap44xx_l4_cfg_slaves,
411 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
412 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
415 /* l4_per interface data */
416 /* l3_main_2 -> l4_per */
417 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
418 .master = &omap44xx_l3_main_2_hwmod,
419 .slave = &omap44xx_l4_per_hwmod,
421 .user = OCP_USER_MPU | OCP_USER_SDMA,
424 /* l4_per slave ports */
425 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
426 &omap44xx_l3_main_2__l4_per,
429 static struct omap_hwmod omap44xx_l4_per_hwmod = {
431 .class = &omap44xx_l4_hwmod_class,
432 .slaves = omap44xx_l4_per_slaves,
433 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves),
434 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
437 /* l4_wkup interface data */
438 /* l4_cfg -> l4_wkup */
439 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
440 .master = &omap44xx_l4_cfg_hwmod,
441 .slave = &omap44xx_l4_wkup_hwmod,
443 .user = OCP_USER_MPU | OCP_USER_SDMA,
446 /* l4_wkup slave ports */
447 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
448 &omap44xx_l4_cfg__l4_wkup,
451 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
453 .class = &omap44xx_l4_hwmod_class,
454 .slaves = omap44xx_l4_wkup_slaves,
455 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
456 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
461 * instance(s): mpu_private
463 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
467 /* mpu_private interface data */
468 /* mpu -> mpu_private */
469 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
470 .master = &omap44xx_mpu_hwmod,
471 .slave = &omap44xx_mpu_private_hwmod,
473 .user = OCP_USER_MPU | OCP_USER_SDMA,
476 /* mpu_private slave ports */
477 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
478 &omap44xx_mpu__mpu_private,
481 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
482 .name = "mpu_private",
483 .class = &omap44xx_mpu_bus_hwmod_class,
484 .slaves = omap44xx_mpu_private_slaves,
485 .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves),
486 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
490 * Modules omap_hwmod structures
492 * The following IPs are excluded for the moment because:
493 * - They do not need an explicit SW control using omap_hwmod API.
494 * - They still need to be validated with the driver
495 * properly adapted to omap_hwmod / omap_device
505 * ctrl_module_pad_core
506 * ctrl_module_pad_wkup
587 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
592 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
593 { .irq = 28 + OMAP44XX_IRQ_GIC_START },
596 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
597 { .name = "mmu_cache", .rst_shift = 1 },
600 static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
601 { .name = "dsp", .rst_shift = 0 },
605 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
606 .master = &omap44xx_dsp_hwmod,
607 .slave = &omap44xx_iva_hwmod,
608 .clk = "dpll_iva_m5x2_ck",
611 /* dsp master ports */
612 static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
613 &omap44xx_dsp__l3_main_1,
614 &omap44xx_dsp__l4_abe,
619 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
620 .master = &omap44xx_l4_cfg_hwmod,
621 .slave = &omap44xx_dsp_hwmod,
623 .user = OCP_USER_MPU | OCP_USER_SDMA,
626 /* dsp slave ports */
627 static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
628 &omap44xx_l4_cfg__dsp,
631 /* Pseudo hwmod for reset control purpose only */
632 static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
634 .class = &omap44xx_dsp_hwmod_class,
635 .flags = HWMOD_INIT_NO_RESET,
636 .rst_lines = omap44xx_dsp_c0_resets,
637 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets),
640 .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
643 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
646 static struct omap_hwmod omap44xx_dsp_hwmod = {
648 .class = &omap44xx_dsp_hwmod_class,
649 .mpu_irqs = omap44xx_dsp_irqs,
650 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dsp_irqs),
651 .rst_lines = omap44xx_dsp_resets,
652 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
653 .main_clk = "dsp_fck",
656 .clkctrl_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
657 .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
660 .slaves = omap44xx_dsp_slaves,
661 .slaves_cnt = ARRAY_SIZE(omap44xx_dsp_slaves),
662 .masters = omap44xx_dsp_masters,
663 .masters_cnt = ARRAY_SIZE(omap44xx_dsp_masters),
664 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
669 * general purpose io module
672 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
676 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
677 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
678 SYSS_HAS_RESET_STATUS),
679 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
681 .sysc_fields = &omap_hwmod_sysc_type1,
684 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
686 .sysc = &omap44xx_gpio_sysc,
691 static struct omap_gpio_dev_attr gpio_dev_attr = {
697 static struct omap_hwmod omap44xx_gpio1_hwmod;
698 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
699 { .irq = 29 + OMAP44XX_IRQ_GIC_START },
702 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
704 .pa_start = 0x4a310000,
705 .pa_end = 0x4a3101ff,
706 .flags = ADDR_TYPE_RT
710 /* l4_wkup -> gpio1 */
711 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
712 .master = &omap44xx_l4_wkup_hwmod,
713 .slave = &omap44xx_gpio1_hwmod,
714 .clk = "l4_wkup_clk_mux_ck",
715 .addr = omap44xx_gpio1_addrs,
716 .addr_cnt = ARRAY_SIZE(omap44xx_gpio1_addrs),
717 .user = OCP_USER_MPU | OCP_USER_SDMA,
720 /* gpio1 slave ports */
721 static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
722 &omap44xx_l4_wkup__gpio1,
725 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
726 { .role = "dbclk", .clk = "gpio1_dbclk" },
729 static struct omap_hwmod omap44xx_gpio1_hwmod = {
731 .class = &omap44xx_gpio_hwmod_class,
732 .mpu_irqs = omap44xx_gpio1_irqs,
733 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio1_irqs),
734 .main_clk = "gpio1_ick",
737 .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
740 .opt_clks = gpio1_opt_clks,
741 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
742 .dev_attr = &gpio_dev_attr,
743 .slaves = omap44xx_gpio1_slaves,
744 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves),
745 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
749 static struct omap_hwmod omap44xx_gpio2_hwmod;
750 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
751 { .irq = 30 + OMAP44XX_IRQ_GIC_START },
754 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
756 .pa_start = 0x48055000,
757 .pa_end = 0x480551ff,
758 .flags = ADDR_TYPE_RT
762 /* l4_per -> gpio2 */
763 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
764 .master = &omap44xx_l4_per_hwmod,
765 .slave = &omap44xx_gpio2_hwmod,
767 .addr = omap44xx_gpio2_addrs,
768 .addr_cnt = ARRAY_SIZE(omap44xx_gpio2_addrs),
769 .user = OCP_USER_MPU | OCP_USER_SDMA,
772 /* gpio2 slave ports */
773 static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
774 &omap44xx_l4_per__gpio2,
777 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
778 { .role = "dbclk", .clk = "gpio2_dbclk" },
781 static struct omap_hwmod omap44xx_gpio2_hwmod = {
783 .class = &omap44xx_gpio_hwmod_class,
784 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
785 .mpu_irqs = omap44xx_gpio2_irqs,
786 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio2_irqs),
787 .main_clk = "gpio2_ick",
790 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
793 .opt_clks = gpio2_opt_clks,
794 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
795 .dev_attr = &gpio_dev_attr,
796 .slaves = omap44xx_gpio2_slaves,
797 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves),
798 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
802 static struct omap_hwmod omap44xx_gpio3_hwmod;
803 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
804 { .irq = 31 + OMAP44XX_IRQ_GIC_START },
807 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
809 .pa_start = 0x48057000,
810 .pa_end = 0x480571ff,
811 .flags = ADDR_TYPE_RT
815 /* l4_per -> gpio3 */
816 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
817 .master = &omap44xx_l4_per_hwmod,
818 .slave = &omap44xx_gpio3_hwmod,
820 .addr = omap44xx_gpio3_addrs,
821 .addr_cnt = ARRAY_SIZE(omap44xx_gpio3_addrs),
822 .user = OCP_USER_MPU | OCP_USER_SDMA,
825 /* gpio3 slave ports */
826 static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
827 &omap44xx_l4_per__gpio3,
830 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
831 { .role = "dbclk", .clk = "gpio3_dbclk" },
834 static struct omap_hwmod omap44xx_gpio3_hwmod = {
836 .class = &omap44xx_gpio_hwmod_class,
837 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
838 .mpu_irqs = omap44xx_gpio3_irqs,
839 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio3_irqs),
840 .main_clk = "gpio3_ick",
843 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
846 .opt_clks = gpio3_opt_clks,
847 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
848 .dev_attr = &gpio_dev_attr,
849 .slaves = omap44xx_gpio3_slaves,
850 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves),
851 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
855 static struct omap_hwmod omap44xx_gpio4_hwmod;
856 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
857 { .irq = 32 + OMAP44XX_IRQ_GIC_START },
860 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
862 .pa_start = 0x48059000,
863 .pa_end = 0x480591ff,
864 .flags = ADDR_TYPE_RT
868 /* l4_per -> gpio4 */
869 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
870 .master = &omap44xx_l4_per_hwmod,
871 .slave = &omap44xx_gpio4_hwmod,
873 .addr = omap44xx_gpio4_addrs,
874 .addr_cnt = ARRAY_SIZE(omap44xx_gpio4_addrs),
875 .user = OCP_USER_MPU | OCP_USER_SDMA,
878 /* gpio4 slave ports */
879 static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
880 &omap44xx_l4_per__gpio4,
883 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
884 { .role = "dbclk", .clk = "gpio4_dbclk" },
887 static struct omap_hwmod omap44xx_gpio4_hwmod = {
889 .class = &omap44xx_gpio_hwmod_class,
890 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
891 .mpu_irqs = omap44xx_gpio4_irqs,
892 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio4_irqs),
893 .main_clk = "gpio4_ick",
896 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
899 .opt_clks = gpio4_opt_clks,
900 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
901 .dev_attr = &gpio_dev_attr,
902 .slaves = omap44xx_gpio4_slaves,
903 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves),
904 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
908 static struct omap_hwmod omap44xx_gpio5_hwmod;
909 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
910 { .irq = 33 + OMAP44XX_IRQ_GIC_START },
913 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
915 .pa_start = 0x4805b000,
916 .pa_end = 0x4805b1ff,
917 .flags = ADDR_TYPE_RT
921 /* l4_per -> gpio5 */
922 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
923 .master = &omap44xx_l4_per_hwmod,
924 .slave = &omap44xx_gpio5_hwmod,
926 .addr = omap44xx_gpio5_addrs,
927 .addr_cnt = ARRAY_SIZE(omap44xx_gpio5_addrs),
928 .user = OCP_USER_MPU | OCP_USER_SDMA,
931 /* gpio5 slave ports */
932 static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
933 &omap44xx_l4_per__gpio5,
936 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
937 { .role = "dbclk", .clk = "gpio5_dbclk" },
940 static struct omap_hwmod omap44xx_gpio5_hwmod = {
942 .class = &omap44xx_gpio_hwmod_class,
943 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
944 .mpu_irqs = omap44xx_gpio5_irqs,
945 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio5_irqs),
946 .main_clk = "gpio5_ick",
949 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
952 .opt_clks = gpio5_opt_clks,
953 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
954 .dev_attr = &gpio_dev_attr,
955 .slaves = omap44xx_gpio5_slaves,
956 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves),
957 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
961 static struct omap_hwmod omap44xx_gpio6_hwmod;
962 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
963 { .irq = 34 + OMAP44XX_IRQ_GIC_START },
966 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
968 .pa_start = 0x4805d000,
969 .pa_end = 0x4805d1ff,
970 .flags = ADDR_TYPE_RT
974 /* l4_per -> gpio6 */
975 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
976 .master = &omap44xx_l4_per_hwmod,
977 .slave = &omap44xx_gpio6_hwmod,
979 .addr = omap44xx_gpio6_addrs,
980 .addr_cnt = ARRAY_SIZE(omap44xx_gpio6_addrs),
981 .user = OCP_USER_MPU | OCP_USER_SDMA,
984 /* gpio6 slave ports */
985 static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
986 &omap44xx_l4_per__gpio6,
989 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
990 { .role = "dbclk", .clk = "gpio6_dbclk" },
993 static struct omap_hwmod omap44xx_gpio6_hwmod = {
995 .class = &omap44xx_gpio_hwmod_class,
996 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
997 .mpu_irqs = omap44xx_gpio6_irqs,
998 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio6_irqs),
999 .main_clk = "gpio6_ick",
1002 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1005 .opt_clks = gpio6_opt_clks,
1006 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1007 .dev_attr = &gpio_dev_attr,
1008 .slaves = omap44xx_gpio6_slaves,
1009 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves),
1010 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1015 * multimaster high-speed i2c controller
1018 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1019 .sysc_offs = 0x0010,
1020 .syss_offs = 0x0090,
1021 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1022 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1023 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1024 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1026 .sysc_fields = &omap_hwmod_sysc_type1,
1029 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1031 .sysc = &omap44xx_i2c_sysc,
1035 static struct omap_hwmod omap44xx_i2c1_hwmod;
1036 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1037 { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1040 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1041 { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1042 { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1045 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
1047 .pa_start = 0x48070000,
1048 .pa_end = 0x480700ff,
1049 .flags = ADDR_TYPE_RT
1053 /* l4_per -> i2c1 */
1054 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
1055 .master = &omap44xx_l4_per_hwmod,
1056 .slave = &omap44xx_i2c1_hwmod,
1058 .addr = omap44xx_i2c1_addrs,
1059 .addr_cnt = ARRAY_SIZE(omap44xx_i2c1_addrs),
1060 .user = OCP_USER_MPU | OCP_USER_SDMA,
1063 /* i2c1 slave ports */
1064 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
1065 &omap44xx_l4_per__i2c1,
1068 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1070 .class = &omap44xx_i2c_hwmod_class,
1071 .flags = HWMOD_INIT_NO_RESET,
1072 .mpu_irqs = omap44xx_i2c1_irqs,
1073 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c1_irqs),
1074 .sdma_reqs = omap44xx_i2c1_sdma_reqs,
1075 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
1076 .main_clk = "i2c1_fck",
1079 .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
1082 .slaves = omap44xx_i2c1_slaves,
1083 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves),
1084 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1088 static struct omap_hwmod omap44xx_i2c2_hwmod;
1089 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1090 { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1093 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1094 { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1095 { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1098 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
1100 .pa_start = 0x48072000,
1101 .pa_end = 0x480720ff,
1102 .flags = ADDR_TYPE_RT
1106 /* l4_per -> i2c2 */
1107 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
1108 .master = &omap44xx_l4_per_hwmod,
1109 .slave = &omap44xx_i2c2_hwmod,
1111 .addr = omap44xx_i2c2_addrs,
1112 .addr_cnt = ARRAY_SIZE(omap44xx_i2c2_addrs),
1113 .user = OCP_USER_MPU | OCP_USER_SDMA,
1116 /* i2c2 slave ports */
1117 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
1118 &omap44xx_l4_per__i2c2,
1121 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1123 .class = &omap44xx_i2c_hwmod_class,
1124 .flags = HWMOD_INIT_NO_RESET,
1125 .mpu_irqs = omap44xx_i2c2_irqs,
1126 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c2_irqs),
1127 .sdma_reqs = omap44xx_i2c2_sdma_reqs,
1128 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
1129 .main_clk = "i2c2_fck",
1132 .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
1135 .slaves = omap44xx_i2c2_slaves,
1136 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves),
1137 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1141 static struct omap_hwmod omap44xx_i2c3_hwmod;
1142 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1143 { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1146 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1147 { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1148 { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1151 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
1153 .pa_start = 0x48060000,
1154 .pa_end = 0x480600ff,
1155 .flags = ADDR_TYPE_RT
1159 /* l4_per -> i2c3 */
1160 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
1161 .master = &omap44xx_l4_per_hwmod,
1162 .slave = &omap44xx_i2c3_hwmod,
1164 .addr = omap44xx_i2c3_addrs,
1165 .addr_cnt = ARRAY_SIZE(omap44xx_i2c3_addrs),
1166 .user = OCP_USER_MPU | OCP_USER_SDMA,
1169 /* i2c3 slave ports */
1170 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
1171 &omap44xx_l4_per__i2c3,
1174 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1176 .class = &omap44xx_i2c_hwmod_class,
1177 .flags = HWMOD_INIT_NO_RESET,
1178 .mpu_irqs = omap44xx_i2c3_irqs,
1179 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c3_irqs),
1180 .sdma_reqs = omap44xx_i2c3_sdma_reqs,
1181 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
1182 .main_clk = "i2c3_fck",
1185 .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
1188 .slaves = omap44xx_i2c3_slaves,
1189 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves),
1190 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1194 static struct omap_hwmod omap44xx_i2c4_hwmod;
1195 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1196 { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1199 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1200 { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1201 { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1204 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
1206 .pa_start = 0x48350000,
1207 .pa_end = 0x483500ff,
1208 .flags = ADDR_TYPE_RT
1212 /* l4_per -> i2c4 */
1213 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
1214 .master = &omap44xx_l4_per_hwmod,
1215 .slave = &omap44xx_i2c4_hwmod,
1217 .addr = omap44xx_i2c4_addrs,
1218 .addr_cnt = ARRAY_SIZE(omap44xx_i2c4_addrs),
1219 .user = OCP_USER_MPU | OCP_USER_SDMA,
1222 /* i2c4 slave ports */
1223 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
1224 &omap44xx_l4_per__i2c4,
1227 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1229 .class = &omap44xx_i2c_hwmod_class,
1230 .flags = HWMOD_INIT_NO_RESET,
1231 .mpu_irqs = omap44xx_i2c4_irqs,
1232 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c4_irqs),
1233 .sdma_reqs = omap44xx_i2c4_sdma_reqs,
1234 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
1235 .main_clk = "i2c4_fck",
1238 .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
1241 .slaves = omap44xx_i2c4_slaves,
1242 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves),
1243 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1248 * multi-standard video encoder/decoder hardware accelerator
1251 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1256 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1257 { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1258 { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1259 { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1262 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1263 { .name = "logic", .rst_shift = 2 },
1266 static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
1267 { .name = "seq0", .rst_shift = 0 },
1270 static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
1271 { .name = "seq1", .rst_shift = 1 },
1274 /* iva master ports */
1275 static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
1276 &omap44xx_iva__l3_main_2,
1277 &omap44xx_iva__l3_instr,
1280 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
1282 .pa_start = 0x5a000000,
1283 .pa_end = 0x5a07ffff,
1284 .flags = ADDR_TYPE_RT
1288 /* l3_main_2 -> iva */
1289 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
1290 .master = &omap44xx_l3_main_2_hwmod,
1291 .slave = &omap44xx_iva_hwmod,
1293 .addr = omap44xx_iva_addrs,
1294 .addr_cnt = ARRAY_SIZE(omap44xx_iva_addrs),
1295 .user = OCP_USER_MPU,
1298 /* iva slave ports */
1299 static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
1301 &omap44xx_l3_main_2__iva,
1304 /* Pseudo hwmod for reset control purpose only */
1305 static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
1307 .class = &omap44xx_iva_hwmod_class,
1308 .flags = HWMOD_INIT_NO_RESET,
1309 .rst_lines = omap44xx_iva_seq0_resets,
1310 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets),
1313 .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
1316 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1319 /* Pseudo hwmod for reset control purpose only */
1320 static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
1322 .class = &omap44xx_iva_hwmod_class,
1323 .flags = HWMOD_INIT_NO_RESET,
1324 .rst_lines = omap44xx_iva_seq1_resets,
1325 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets),
1328 .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
1331 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1334 static struct omap_hwmod omap44xx_iva_hwmod = {
1336 .class = &omap44xx_iva_hwmod_class,
1337 .mpu_irqs = omap44xx_iva_irqs,
1338 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iva_irqs),
1339 .rst_lines = omap44xx_iva_resets,
1340 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
1341 .main_clk = "iva_fck",
1344 .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1345 .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
1348 .slaves = omap44xx_iva_slaves,
1349 .slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves),
1350 .masters = omap44xx_iva_masters,
1351 .masters_cnt = ARRAY_SIZE(omap44xx_iva_masters),
1352 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1360 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
1365 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
1366 { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
1367 { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
1368 { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
1371 /* mpu master ports */
1372 static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
1373 &omap44xx_mpu__l3_main_1,
1374 &omap44xx_mpu__l4_abe,
1378 static struct omap_hwmod omap44xx_mpu_hwmod = {
1380 .class = &omap44xx_mpu_hwmod_class,
1381 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1382 .mpu_irqs = omap44xx_mpu_irqs,
1383 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mpu_irqs),
1384 .main_clk = "dpll_mpu_m2_ck",
1387 .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
1390 .masters = omap44xx_mpu_masters,
1391 .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters),
1392 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1397 * universal asynchronous receiver/transmitter (uart)
1400 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
1402 .sysc_offs = 0x0054,
1403 .syss_offs = 0x0058,
1404 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1405 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1406 SYSS_HAS_RESET_STATUS),
1407 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1409 .sysc_fields = &omap_hwmod_sysc_type1,
1412 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
1414 .sysc = &omap44xx_uart_sysc,
1418 static struct omap_hwmod omap44xx_uart1_hwmod;
1419 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
1420 { .irq = 72 + OMAP44XX_IRQ_GIC_START },
1423 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
1424 { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
1425 { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
1428 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
1430 .pa_start = 0x4806a000,
1431 .pa_end = 0x4806a0ff,
1432 .flags = ADDR_TYPE_RT
1436 /* l4_per -> uart1 */
1437 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
1438 .master = &omap44xx_l4_per_hwmod,
1439 .slave = &omap44xx_uart1_hwmod,
1441 .addr = omap44xx_uart1_addrs,
1442 .addr_cnt = ARRAY_SIZE(omap44xx_uart1_addrs),
1443 .user = OCP_USER_MPU | OCP_USER_SDMA,
1446 /* uart1 slave ports */
1447 static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
1448 &omap44xx_l4_per__uart1,
1451 static struct omap_hwmod omap44xx_uart1_hwmod = {
1453 .class = &omap44xx_uart_hwmod_class,
1454 .mpu_irqs = omap44xx_uart1_irqs,
1455 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart1_irqs),
1456 .sdma_reqs = omap44xx_uart1_sdma_reqs,
1457 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart1_sdma_reqs),
1458 .main_clk = "uart1_fck",
1461 .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
1464 .slaves = omap44xx_uart1_slaves,
1465 .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves),
1466 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1470 static struct omap_hwmod omap44xx_uart2_hwmod;
1471 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
1472 { .irq = 73 + OMAP44XX_IRQ_GIC_START },
1475 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
1476 { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
1477 { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
1480 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
1482 .pa_start = 0x4806c000,
1483 .pa_end = 0x4806c0ff,
1484 .flags = ADDR_TYPE_RT
1488 /* l4_per -> uart2 */
1489 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
1490 .master = &omap44xx_l4_per_hwmod,
1491 .slave = &omap44xx_uart2_hwmod,
1493 .addr = omap44xx_uart2_addrs,
1494 .addr_cnt = ARRAY_SIZE(omap44xx_uart2_addrs),
1495 .user = OCP_USER_MPU | OCP_USER_SDMA,
1498 /* uart2 slave ports */
1499 static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
1500 &omap44xx_l4_per__uart2,
1503 static struct omap_hwmod omap44xx_uart2_hwmod = {
1505 .class = &omap44xx_uart_hwmod_class,
1506 .mpu_irqs = omap44xx_uart2_irqs,
1507 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart2_irqs),
1508 .sdma_reqs = omap44xx_uart2_sdma_reqs,
1509 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart2_sdma_reqs),
1510 .main_clk = "uart2_fck",
1513 .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
1516 .slaves = omap44xx_uart2_slaves,
1517 .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves),
1518 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1522 static struct omap_hwmod omap44xx_uart3_hwmod;
1523 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
1524 { .irq = 74 + OMAP44XX_IRQ_GIC_START },
1527 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
1528 { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
1529 { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
1532 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
1534 .pa_start = 0x48020000,
1535 .pa_end = 0x480200ff,
1536 .flags = ADDR_TYPE_RT
1540 /* l4_per -> uart3 */
1541 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
1542 .master = &omap44xx_l4_per_hwmod,
1543 .slave = &omap44xx_uart3_hwmod,
1545 .addr = omap44xx_uart3_addrs,
1546 .addr_cnt = ARRAY_SIZE(omap44xx_uart3_addrs),
1547 .user = OCP_USER_MPU | OCP_USER_SDMA,
1550 /* uart3 slave ports */
1551 static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
1552 &omap44xx_l4_per__uart3,
1555 static struct omap_hwmod omap44xx_uart3_hwmod = {
1557 .class = &omap44xx_uart_hwmod_class,
1558 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1559 .mpu_irqs = omap44xx_uart3_irqs,
1560 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart3_irqs),
1561 .sdma_reqs = omap44xx_uart3_sdma_reqs,
1562 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart3_sdma_reqs),
1563 .main_clk = "uart3_fck",
1566 .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
1569 .slaves = omap44xx_uart3_slaves,
1570 .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves),
1571 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1575 static struct omap_hwmod omap44xx_uart4_hwmod;
1576 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
1577 { .irq = 70 + OMAP44XX_IRQ_GIC_START },
1580 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
1581 { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
1582 { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
1585 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
1587 .pa_start = 0x4806e000,
1588 .pa_end = 0x4806e0ff,
1589 .flags = ADDR_TYPE_RT
1593 /* l4_per -> uart4 */
1594 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
1595 .master = &omap44xx_l4_per_hwmod,
1596 .slave = &omap44xx_uart4_hwmod,
1598 .addr = omap44xx_uart4_addrs,
1599 .addr_cnt = ARRAY_SIZE(omap44xx_uart4_addrs),
1600 .user = OCP_USER_MPU | OCP_USER_SDMA,
1603 /* uart4 slave ports */
1604 static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
1605 &omap44xx_l4_per__uart4,
1608 static struct omap_hwmod omap44xx_uart4_hwmod = {
1610 .class = &omap44xx_uart_hwmod_class,
1611 .mpu_irqs = omap44xx_uart4_irqs,
1612 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart4_irqs),
1613 .sdma_reqs = omap44xx_uart4_sdma_reqs,
1614 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart4_sdma_reqs),
1615 .main_clk = "uart4_fck",
1618 .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
1621 .slaves = omap44xx_uart4_slaves,
1622 .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves),
1623 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1628 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1629 * overflow condition
1632 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
1634 .sysc_offs = 0x0010,
1635 .syss_offs = 0x0014,
1636 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1637 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1638 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1640 .sysc_fields = &omap_hwmod_sysc_type1,
1643 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
1645 .sysc = &omap44xx_wd_timer_sysc,
1646 .pre_shutdown = &omap2_wd_timer_disable
1650 static struct omap_hwmod omap44xx_wd_timer2_hwmod;
1651 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
1652 { .irq = 80 + OMAP44XX_IRQ_GIC_START },
1655 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
1657 .pa_start = 0x4a314000,
1658 .pa_end = 0x4a31407f,
1659 .flags = ADDR_TYPE_RT
1663 /* l4_wkup -> wd_timer2 */
1664 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
1665 .master = &omap44xx_l4_wkup_hwmod,
1666 .slave = &omap44xx_wd_timer2_hwmod,
1667 .clk = "l4_wkup_clk_mux_ck",
1668 .addr = omap44xx_wd_timer2_addrs,
1669 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer2_addrs),
1670 .user = OCP_USER_MPU | OCP_USER_SDMA,
1673 /* wd_timer2 slave ports */
1674 static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
1675 &omap44xx_l4_wkup__wd_timer2,
1678 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
1679 .name = "wd_timer2",
1680 .class = &omap44xx_wd_timer_hwmod_class,
1681 .mpu_irqs = omap44xx_wd_timer2_irqs,
1682 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
1683 .main_clk = "wd_timer2_fck",
1686 .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
1689 .slaves = omap44xx_wd_timer2_slaves,
1690 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
1691 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1695 static struct omap_hwmod omap44xx_wd_timer3_hwmod;
1696 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
1697 { .irq = 36 + OMAP44XX_IRQ_GIC_START },
1700 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
1702 .pa_start = 0x40130000,
1703 .pa_end = 0x4013007f,
1704 .flags = ADDR_TYPE_RT
1708 /* l4_abe -> wd_timer3 */
1709 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
1710 .master = &omap44xx_l4_abe_hwmod,
1711 .slave = &omap44xx_wd_timer3_hwmod,
1712 .clk = "ocp_abe_iclk",
1713 .addr = omap44xx_wd_timer3_addrs,
1714 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_addrs),
1715 .user = OCP_USER_MPU,
1718 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
1720 .pa_start = 0x49030000,
1721 .pa_end = 0x4903007f,
1722 .flags = ADDR_TYPE_RT
1726 /* l4_abe -> wd_timer3 (dma) */
1727 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
1728 .master = &omap44xx_l4_abe_hwmod,
1729 .slave = &omap44xx_wd_timer3_hwmod,
1730 .clk = "ocp_abe_iclk",
1731 .addr = omap44xx_wd_timer3_dma_addrs,
1732 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
1733 .user = OCP_USER_SDMA,
1736 /* wd_timer3 slave ports */
1737 static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
1738 &omap44xx_l4_abe__wd_timer3,
1739 &omap44xx_l4_abe__wd_timer3_dma,
1742 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
1743 .name = "wd_timer3",
1744 .class = &omap44xx_wd_timer_hwmod_class,
1745 .mpu_irqs = omap44xx_wd_timer3_irqs,
1746 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
1747 .main_clk = "wd_timer3_fck",
1750 .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
1753 .slaves = omap44xx_wd_timer3_slaves,
1754 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
1755 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1761 * dma controller for data exchange between memory to memory (i.e. internal or
1762 * external memory) and gp peripherals to memory or memory to gp peripherals
1765 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
1767 .sysc_offs = 0x002c,
1768 .syss_offs = 0x0028,
1769 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1770 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1771 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1772 SYSS_HAS_RESET_STATUS),
1773 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1774 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1775 .sysc_fields = &omap_hwmod_sysc_type1,
1778 /* dma attributes */
1779 static struct omap_dma_dev_attr dma_dev_attr = {
1780 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1781 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1785 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
1787 .sysc = &omap44xx_dma_sysc,
1791 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
1792 { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
1793 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
1794 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
1795 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
1798 /* dma_system master ports */
1799 static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
1800 &omap44xx_dma_system__l3_main_2,
1803 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
1805 .pa_start = 0x4a056000,
1806 .pa_end = 0x4a0560ff,
1807 .flags = ADDR_TYPE_RT
1811 /* l4_cfg -> dma_system */
1812 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
1813 .master = &omap44xx_l4_cfg_hwmod,
1814 .slave = &omap44xx_dma_system_hwmod,
1816 .addr = omap44xx_dma_system_addrs,
1817 .addr_cnt = ARRAY_SIZE(omap44xx_dma_system_addrs),
1818 .user = OCP_USER_MPU | OCP_USER_SDMA,
1821 /* dma_system slave ports */
1822 static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
1823 &omap44xx_l4_cfg__dma_system,
1826 static struct omap_hwmod omap44xx_dma_system_hwmod = {
1827 .name = "dma_system",
1828 .class = &omap44xx_dma_hwmod_class,
1829 .mpu_irqs = omap44xx_dma_system_irqs,
1830 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dma_system_irqs),
1831 .main_clk = "l3_div_ck",
1834 .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
1837 .slaves = omap44xx_dma_system_slaves,
1838 .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves),
1839 .masters = omap44xx_dma_system_masters,
1840 .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters),
1841 .dev_attr = &dma_dev_attr,
1842 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1845 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
1847 &omap44xx_dmm_hwmod,
1850 &omap44xx_emif_fw_hwmod,
1853 &omap44xx_l3_instr_hwmod,
1854 &omap44xx_l3_main_1_hwmod,
1855 &omap44xx_l3_main_2_hwmod,
1856 &omap44xx_l3_main_3_hwmod,
1859 &omap44xx_l4_abe_hwmod,
1860 &omap44xx_l4_cfg_hwmod,
1861 &omap44xx_l4_per_hwmod,
1862 &omap44xx_l4_wkup_hwmod,
1865 &omap44xx_dma_system_hwmod,
1868 &omap44xx_mpu_private_hwmod,
1871 &omap44xx_dsp_hwmod,
1872 &omap44xx_dsp_c0_hwmod,
1875 &omap44xx_gpio1_hwmod,
1876 &omap44xx_gpio2_hwmod,
1877 &omap44xx_gpio3_hwmod,
1878 &omap44xx_gpio4_hwmod,
1879 &omap44xx_gpio5_hwmod,
1880 &omap44xx_gpio6_hwmod,
1883 &omap44xx_i2c1_hwmod,
1884 &omap44xx_i2c2_hwmod,
1885 &omap44xx_i2c3_hwmod,
1886 &omap44xx_i2c4_hwmod,
1889 &omap44xx_iva_hwmod,
1890 &omap44xx_iva_seq0_hwmod,
1891 &omap44xx_iva_seq1_hwmod,
1894 &omap44xx_mpu_hwmod,
1897 &omap44xx_uart1_hwmod,
1898 &omap44xx_uart2_hwmod,
1899 &omap44xx_uart3_hwmod,
1900 &omap44xx_uart4_hwmod,
1902 /* wd_timer class */
1903 &omap44xx_wd_timer2_hwmod,
1904 &omap44xx_wd_timer3_hwmod,
1909 int __init omap44xx_hwmod_init(void)
1911 return omap_hwmod_init(omap44xx_hwmods);