arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2011 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22
  23 #include <plat/omap_hwmod.h>
  24 #include <plat/cpu.h>
  25 #include <plat/gpio.h>
  26 #include <plat/dma.h>
  27 #include <plat/mcspi.h>
  28 #include <plat/mcbsp.h>
  29 #include <plat/mmc.h>
  30
  31 #include "omap_hwmod_common_data.h"
  32
  33 #include "cm1_44xx.h"
  34 #include "cm2_44xx.h"
  35 #include "prm44xx.h"
  36 #include "prm-regbits-44xx.h"
  37 #include "wd_timer.h"
  38
  39 /* Base offset for all OMAP4 interrupts external to MPUSS */
  40 #define OMAP44XX_IRQ_GIC_START  32
  41
  42 /* Base offset for all OMAP4 dma requests */
  43 #define OMAP44XX_DMA_REQ_START  1
  44
  45 /* Backward references (IPs with Bus Master capability) */
  46 static struct omap_hwmod omap44xx_aess_hwmod;
  47 static struct omap_hwmod omap44xx_dma_system_hwmod;
  48 static struct omap_hwmod omap44xx_dmm_hwmod;
  49 static struct omap_hwmod omap44xx_dsp_hwmod;
  50 static struct omap_hwmod omap44xx_dss_hwmod;
  51 static struct omap_hwmod omap44xx_emif_fw_hwmod;
  52 static struct omap_hwmod omap44xx_hsi_hwmod;
  53 static struct omap_hwmod omap44xx_ipu_hwmod;
  54 static struct omap_hwmod omap44xx_iss_hwmod;
  55 static struct omap_hwmod omap44xx_iva_hwmod;
  56 static struct omap_hwmod omap44xx_l3_instr_hwmod;
  57 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
  58 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
  59 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
  60 static struct omap_hwmod omap44xx_l4_abe_hwmod;
  61 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
  62 static struct omap_hwmod omap44xx_l4_per_hwmod;
  63 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
  64 static struct omap_hwmod omap44xx_mmc1_hwmod;
  65 static struct omap_hwmod omap44xx_mmc2_hwmod;
  66 static struct omap_hwmod omap44xx_mpu_hwmod;
  67 static struct omap_hwmod omap44xx_mpu_private_hwmod;
  68 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
  69
  70 /*
  71  * Interconnects omap_hwmod structures
  72  * hwmods that compose the global OMAP interconnect
  73  */
  74
  75 /*
  76  * 'dmm' class
  77  * instance(s): dmm
  78  */
  79 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  80         .name   = "dmm",
  81 };
  82
  83 /* dmm interface data */
  84 /* l3_main_1 -> dmm */
  85 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
  86         .master         = &omap44xx_l3_main_1_hwmod,
  87         .slave          = &omap44xx_dmm_hwmod,
  88         .clk            = "l3_div_ck",
  89         .user           = OCP_USER_SDMA,
  90 };
  91
  92 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
  93         {
  94                 .pa_start       = 0x4e000000,
  95                 .pa_end         = 0x4e0007ff,
  96                 .flags          = ADDR_TYPE_RT
  97         },
  98 };
  99
 100 /* mpu -> dmm */
 101 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
 102         .master         = &omap44xx_mpu_hwmod,
 103         .slave          = &omap44xx_dmm_hwmod,
 104         .clk            = "l3_div_ck",
 105         .addr           = omap44xx_dmm_addrs,
 106         .addr_cnt       = ARRAY_SIZE(omap44xx_dmm_addrs),
 107         .user           = OCP_USER_MPU,
 108 };
 109
 110 /* dmm slave ports */
 111 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
 112         &omap44xx_l3_main_1__dmm,
 113         &omap44xx_mpu__dmm,
 114 };
 115
 116 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
 117         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
 118 };
 119
 120 static struct omap_hwmod omap44xx_dmm_hwmod = {
 121         .name           = "dmm",
 122         .class          = &omap44xx_dmm_hwmod_class,
 123         .slaves         = omap44xx_dmm_slaves,
 124         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmm_slaves),
 125         .mpu_irqs       = omap44xx_dmm_irqs,
 126         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dmm_irqs),
 127         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 128 };
 129
 130 /*
 131  * 'emif_fw' class
 132  * instance(s): emif_fw
 133  */
 134 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 135         .name   = "emif_fw",
 136 };
 137
 138 /* emif_fw interface data */
 139 /* dmm -> emif_fw */
 140 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
 141         .master         = &omap44xx_dmm_hwmod,
 142         .slave          = &omap44xx_emif_fw_hwmod,
 143         .clk            = "l3_div_ck",
 144         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 145 };
 146
 147 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
 148         {
 149                 .pa_start       = 0x4a20c000,
 150                 .pa_end         = 0x4a20c0ff,
 151                 .flags          = ADDR_TYPE_RT
 152         },
 153 };
 154
 155 /* l4_cfg -> emif_fw */
 156 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
 157         .master         = &omap44xx_l4_cfg_hwmod,
 158         .slave          = &omap44xx_emif_fw_hwmod,
 159         .clk            = "l4_div_ck",
 160         .addr           = omap44xx_emif_fw_addrs,
 161         .addr_cnt       = ARRAY_SIZE(omap44xx_emif_fw_addrs),
 162         .user           = OCP_USER_MPU,
 163 };
 164
 165 /* emif_fw slave ports */
 166 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
 167         &omap44xx_dmm__emif_fw,
 168         &omap44xx_l4_cfg__emif_fw,
 169 };
 170
 171 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 172         .name           = "emif_fw",
 173         .class          = &omap44xx_emif_fw_hwmod_class,
 174         .slaves         = omap44xx_emif_fw_slaves,
 175         .slaves_cnt     = ARRAY_SIZE(omap44xx_emif_fw_slaves),
 176         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 177 };
 178
 179 /*
 180  * 'l3' class
 181  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 182  */
 183 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 184         .name   = "l3",
 185 };
 186
 187 /* l3_instr interface data */
 188 /* iva -> l3_instr */
 189 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
 190         .master         = &omap44xx_iva_hwmod,
 191         .slave          = &omap44xx_l3_instr_hwmod,
 192         .clk            = "l3_div_ck",
 193         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 194 };
 195
 196 /* l3_main_3 -> l3_instr */
 197 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
 198         .master         = &omap44xx_l3_main_3_hwmod,
 199         .slave          = &omap44xx_l3_instr_hwmod,
 200         .clk            = "l3_div_ck",
 201         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 202 };
 203
 204 /* l3_instr slave ports */
 205 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
 206         &omap44xx_iva__l3_instr,
 207         &omap44xx_l3_main_3__l3_instr,
 208 };
 209
 210 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 211         .name           = "l3_instr",
 212         .class          = &omap44xx_l3_hwmod_class,
 213         .slaves         = omap44xx_l3_instr_slaves,
 214         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_instr_slaves),
 215         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 216 };
 217
 218 /* l3_main_1 interface data */
 219 /* dsp -> l3_main_1 */
 220 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
 221         .master         = &omap44xx_dsp_hwmod,
 222         .slave          = &omap44xx_l3_main_1_hwmod,
 223         .clk            = "l3_div_ck",
 224         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 225 };
 226
 227 /* dss -> l3_main_1 */
 228 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
 229         .master         = &omap44xx_dss_hwmod,
 230         .slave          = &omap44xx_l3_main_1_hwmod,
 231         .clk            = "l3_div_ck",
 232         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 233 };
 234
 235 /* l3_main_2 -> l3_main_1 */
 236 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
 237         .master         = &omap44xx_l3_main_2_hwmod,
 238         .slave          = &omap44xx_l3_main_1_hwmod,
 239         .clk            = "l3_div_ck",
 240         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 241 };
 242
 243 /* l4_cfg -> l3_main_1 */
 244 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
 245         .master         = &omap44xx_l4_cfg_hwmod,
 246         .slave          = &omap44xx_l3_main_1_hwmod,
 247         .clk            = "l4_div_ck",
 248         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 249 };
 250
 251 /* mmc1 -> l3_main_1 */
 252 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
 253         .master         = &omap44xx_mmc1_hwmod,
 254         .slave          = &omap44xx_l3_main_1_hwmod,
 255         .clk            = "l3_div_ck",
 256         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 257 };
 258
 259 /* mmc2 -> l3_main_1 */
 260 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
 261         .master         = &omap44xx_mmc2_hwmod,
 262         .slave          = &omap44xx_l3_main_1_hwmod,
 263         .clk            = "l3_div_ck",
 264         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 265 };
 266
 267 /* L3 target configuration and error log registers */
 268 static struct omap_hwmod_irq_info omap44xx_l3_targ_irqs[] = {
 269         { .irq = 9  + OMAP44XX_IRQ_GIC_START },
 270         { .irq = 10 + OMAP44XX_IRQ_GIC_START },
 271 };
 272
 273 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
 274         {
 275                 .pa_start       = 0x44000000,
 276                 .pa_end         = 0x44000fff,
 277                 .flags          = ADDR_TYPE_RT,
 278         },
 279 };
 280
 281 /* mpu -> l3_main_1 */
 282 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
 283         .master         = &omap44xx_mpu_hwmod,
 284         .slave          = &omap44xx_l3_main_1_hwmod,
 285         .clk            = "l3_div_ck",
 286         .addr           = omap44xx_l3_main_1_addrs,
 287         .addr_cnt       = ARRAY_SIZE(omap44xx_l3_main_1_addrs),
 288         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 289 };
 290
 291 /* l3_main_1 slave ports */
 292 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
 293         &omap44xx_dsp__l3_main_1,
 294         &omap44xx_dss__l3_main_1,
 295         &omap44xx_l3_main_2__l3_main_1,
 296         &omap44xx_l4_cfg__l3_main_1,
 297         &omap44xx_mmc1__l3_main_1,
 298         &omap44xx_mmc2__l3_main_1,
 299         &omap44xx_mpu__l3_main_1,
 300 };
 301
 302 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 303         .name           = "l3_main_1",
 304         .class          = &omap44xx_l3_hwmod_class,
 305         .mpu_irqs       = omap44xx_l3_targ_irqs,
 306         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_l3_targ_irqs),
 307         .slaves         = omap44xx_l3_main_1_slaves,
 308         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
 309         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 310 };
 311
 312 /* l3_main_2 interface data */
 313 /* dma_system -> l3_main_2 */
 314 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
 315         .master         = &omap44xx_dma_system_hwmod,
 316         .slave          = &omap44xx_l3_main_2_hwmod,
 317         .clk            = "l3_div_ck",
 318         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 319 };
 320
 321 /* hsi -> l3_main_2 */
 322 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
 323         .master         = &omap44xx_hsi_hwmod,
 324         .slave          = &omap44xx_l3_main_2_hwmod,
 325         .clk            = "l3_div_ck",
 326         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 327 };
 328
 329 /* ipu -> l3_main_2 */
 330 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
 331         .master         = &omap44xx_ipu_hwmod,
 332         .slave          = &omap44xx_l3_main_2_hwmod,
 333         .clk            = "l3_div_ck",
 334         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 335 };
 336
 337 /* iss -> l3_main_2 */
 338 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
 339         .master         = &omap44xx_iss_hwmod,
 340         .slave          = &omap44xx_l3_main_2_hwmod,
 341         .clk            = "l3_div_ck",
 342         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 343 };
 344
 345 /* iva -> l3_main_2 */
 346 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
 347         .master         = &omap44xx_iva_hwmod,
 348         .slave          = &omap44xx_l3_main_2_hwmod,
 349         .clk            = "l3_div_ck",
 350         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 351 };
 352
 353 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
 354         {
 355                 .pa_start       = 0x44800000,
 356                 .pa_end         = 0x44801fff,
 357                 .flags          = ADDR_TYPE_RT,
 358         },
 359 };
 360
 361 /* l3_main_1 -> l3_main_2 */
 362 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
 363         .master         = &omap44xx_l3_main_1_hwmod,
 364         .slave          = &omap44xx_l3_main_2_hwmod,
 365         .clk            = "l3_div_ck",
 366         .addr           = omap44xx_l3_main_2_addrs,
 367         .addr_cnt       = ARRAY_SIZE(omap44xx_l3_main_2_addrs),
 368         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 369 };
 370
 371 /* l4_cfg -> l3_main_2 */
 372 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
 373         .master         = &omap44xx_l4_cfg_hwmod,
 374         .slave          = &omap44xx_l3_main_2_hwmod,
 375         .clk            = "l4_div_ck",
 376         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 377 };
 378
 379 /* usb_otg_hs -> l3_main_2 */
 380 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
 381         .master         = &omap44xx_usb_otg_hs_hwmod,
 382         .slave          = &omap44xx_l3_main_2_hwmod,
 383         .clk            = "l3_div_ck",
 384         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 385 };
 386
 387 /* l3_main_2 slave ports */
 388 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
 389         &omap44xx_dma_system__l3_main_2,
 390         &omap44xx_hsi__l3_main_2,
 391         &omap44xx_ipu__l3_main_2,
 392         &omap44xx_iss__l3_main_2,
 393         &omap44xx_iva__l3_main_2,
 394         &omap44xx_l3_main_1__l3_main_2,
 395         &omap44xx_l4_cfg__l3_main_2,
 396         &omap44xx_usb_otg_hs__l3_main_2,
 397 };
 398
 399 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 400         .name           = "l3_main_2",
 401         .class          = &omap44xx_l3_hwmod_class,
 402         .slaves         = omap44xx_l3_main_2_slaves,
 403         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
 404         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 405 };
 406
 407 /* l3_main_3 interface data */
 408 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
 409         {
 410                 .pa_start       = 0x45000000,
 411                 .pa_end         = 0x45000fff,
 412                 .flags          = ADDR_TYPE_RT,
 413         },
 414 };
 415
 416 /* l3_main_1 -> l3_main_3 */
 417 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
 418         .master         = &omap44xx_l3_main_1_hwmod,
 419         .slave          = &omap44xx_l3_main_3_hwmod,
 420         .clk            = "l3_div_ck",
 421         .addr           = omap44xx_l3_main_3_addrs,
 422         .addr_cnt       = ARRAY_SIZE(omap44xx_l3_main_3_addrs),
 423         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 424 };
 425
 426 /* l3_main_2 -> l3_main_3 */
 427 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
 428         .master         = &omap44xx_l3_main_2_hwmod,
 429         .slave          = &omap44xx_l3_main_3_hwmod,
 430         .clk            = "l3_div_ck",
 431         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 432 };
 433
 434 /* l4_cfg -> l3_main_3 */
 435 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
 436         .master         = &omap44xx_l4_cfg_hwmod,
 437         .slave          = &omap44xx_l3_main_3_hwmod,
 438         .clk            = "l4_div_ck",
 439         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 440 };
 441
 442 /* l3_main_3 slave ports */
 443 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
 444         &omap44xx_l3_main_1__l3_main_3,
 445         &omap44xx_l3_main_2__l3_main_3,
 446         &omap44xx_l4_cfg__l3_main_3,
 447 };
 448
 449 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 450         .name           = "l3_main_3",
 451         .class          = &omap44xx_l3_hwmod_class,
 452         .slaves         = omap44xx_l3_main_3_slaves,
 453         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
 454         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 455 };
 456
 457 /*
 458  * 'l4' class
 459  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 460  */
 461 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 462         .name   = "l4",
 463 };
 464
 465 /* l4_abe interface data */
 466 /* aess -> l4_abe */
 467 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
 468         .master         = &omap44xx_aess_hwmod,
 469         .slave          = &omap44xx_l4_abe_hwmod,
 470         .clk            = "ocp_abe_iclk",
 471         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 472 };
 473
 474 /* dsp -> l4_abe */
 475 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
 476         .master         = &omap44xx_dsp_hwmod,
 477         .slave          = &omap44xx_l4_abe_hwmod,
 478         .clk            = "ocp_abe_iclk",
 479         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 480 };
 481
 482 /* l3_main_1 -> l4_abe */
 483 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
 484         .master         = &omap44xx_l3_main_1_hwmod,
 485         .slave          = &omap44xx_l4_abe_hwmod,
 486         .clk            = "l3_div_ck",
 487         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 488 };
 489
 490 /* mpu -> l4_abe */
 491 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
 492         .master         = &omap44xx_mpu_hwmod,
 493         .slave          = &omap44xx_l4_abe_hwmod,
 494         .clk            = "ocp_abe_iclk",
 495         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 496 };
 497
 498 /* l4_abe slave ports */
 499 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
 500         &omap44xx_aess__l4_abe,
 501         &omap44xx_dsp__l4_abe,
 502         &omap44xx_l3_main_1__l4_abe,
 503         &omap44xx_mpu__l4_abe,
 504 };
 505
 506 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 507         .name           = "l4_abe",
 508         .class          = &omap44xx_l4_hwmod_class,
 509         .slaves         = omap44xx_l4_abe_slaves,
 510         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_abe_slaves),
 511         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 512 };
 513
 514 /* l4_cfg interface data */
 515 /* l3_main_1 -> l4_cfg */
 516 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
 517         .master         = &omap44xx_l3_main_1_hwmod,
 518         .slave          = &omap44xx_l4_cfg_hwmod,
 519         .clk            = "l3_div_ck",
 520         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 521 };
 522
 523 /* l4_cfg slave ports */
 524 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
 525         &omap44xx_l3_main_1__l4_cfg,
 526 };
 527
 528 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 529         .name           = "l4_cfg",
 530         .class          = &omap44xx_l4_hwmod_class,
 531         .slaves         = omap44xx_l4_cfg_slaves,
 532         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
 533         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 534 };
 535
 536 /* l4_per interface data */
 537 /* l3_main_2 -> l4_per */
 538 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
 539         .master         = &omap44xx_l3_main_2_hwmod,
 540         .slave          = &omap44xx_l4_per_hwmod,
 541         .clk            = "l3_div_ck",
 542         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 543 };
 544
 545 /* l4_per slave ports */
 546 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
 547         &omap44xx_l3_main_2__l4_per,
 548 };
 549
 550 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 551         .name           = "l4_per",
 552         .class          = &omap44xx_l4_hwmod_class,
 553         .slaves         = omap44xx_l4_per_slaves,
 554         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_per_slaves),
 555         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 556 };
 557
 558 /* l4_wkup interface data */
 559 /* l4_cfg -> l4_wkup */
 560 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
 561         .master         = &omap44xx_l4_cfg_hwmod,
 562         .slave          = &omap44xx_l4_wkup_hwmod,
 563         .clk            = "l4_div_ck",
 564         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 565 };
 566
 567 /* l4_wkup slave ports */
 568 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
 569         &omap44xx_l4_cfg__l4_wkup,
 570 };
 571
 572 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 573         .name           = "l4_wkup",
 574         .class          = &omap44xx_l4_hwmod_class,
 575         .slaves         = omap44xx_l4_wkup_slaves,
 576         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
 577         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 578 };
 579
 580 /*
 581  * 'mpu_bus' class
 582  * instance(s): mpu_private
 583  */
 584 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 585         .name   = "mpu_bus",
 586 };
 587
 588 /* mpu_private interface data */
 589 /* mpu -> mpu_private */
 590 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
 591         .master         = &omap44xx_mpu_hwmod,
 592         .slave          = &omap44xx_mpu_private_hwmod,
 593         .clk            = "l3_div_ck",
 594         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 595 };
 596
 597 /* mpu_private slave ports */
 598 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
 599         &omap44xx_mpu__mpu_private,
 600 };
 601
 602 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 603         .name           = "mpu_private",
 604         .class          = &omap44xx_mpu_bus_hwmod_class,
 605         .slaves         = omap44xx_mpu_private_slaves,
 606         .slaves_cnt     = ARRAY_SIZE(omap44xx_mpu_private_slaves),
 607         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 608 };
 609
 610 /*
 611  * Modules omap_hwmod structures
 612  *
 613  * The following IPs are excluded for the moment because:
 614  * - They do not need an explicit SW control using omap_hwmod API.
 615  * - They still need to be validated with the driver
 616  *   properly adapted to omap_hwmod / omap_device
 617  *
 618  *  c2c
 619  *  c2c_target_fw
 620  *  cm_core
 621  *  cm_core_aon
 622  *  ctrl_module_core
 623  *  ctrl_module_pad_core
 624  *  ctrl_module_pad_wkup
 625  *  ctrl_module_wkup
 626  *  debugss
 627  *  efuse_ctrl_cust
 628  *  efuse_ctrl_std
 629  *  elm
 630  *  emif1
 631  *  emif2
 632  *  fdif
 633  *  gpmc
 634  *  gpu
 635  *  hdq1w
 636  *  hsi
 637  *  ocmc_ram
 638  *  ocp2scp_usb_phy
 639  *  ocp_wp_noc
 640  *  prcm_mpu
 641  *  prm
 642  *  scrm
 643  *  sl2if
 644  *  slimbus1
 645  *  slimbus2
 646  *  usb_host_fs
 647  *  usb_host_hs
 648  *  usb_phy_cm
 649  *  usb_tll_hs
 650  *  usim
 651  */
 652
 653 /*
 654  * 'aess' class
 655  * audio engine sub system
 656  */
 657
 658 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 659         .rev_offs       = 0x0000,
 660         .sysc_offs      = 0x0010,
 661         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 662         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 663                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 664                            MSTANDBY_SMART_WKUP),
 665         .sysc_fields    = &omap_hwmod_sysc_type2,
 666 };
 667
 668 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 669         .name   = "aess",
 670         .sysc   = &omap44xx_aess_sysc,
 671 };
 672
 673 /* aess */
 674 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 675         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 676 };
 677
 678 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 679         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 680         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 681         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 682         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 683         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 684         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 685         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 686         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 687 };
 688
 689 /* aess master ports */
 690 static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
 691         &omap44xx_aess__l4_abe,
 692 };
 693
 694 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
 695         {
 696                 .pa_start       = 0x401f1000,
 697                 .pa_end         = 0x401f13ff,
 698                 .flags          = ADDR_TYPE_RT
 699         },
 700 };
 701
 702 /* l4_abe -> aess */
 703 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
 704         .master         = &omap44xx_l4_abe_hwmod,
 705         .slave          = &omap44xx_aess_hwmod,
 706         .clk            = "ocp_abe_iclk",
 707         .addr           = omap44xx_aess_addrs,
 708         .addr_cnt       = ARRAY_SIZE(omap44xx_aess_addrs),
 709         .user           = OCP_USER_MPU,
 710 };
 711
 712 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
 713         {
 714                 .pa_start       = 0x490f1000,
 715                 .pa_end         = 0x490f13ff,
 716                 .flags          = ADDR_TYPE_RT
 717         },
 718 };
 719
 720 /* l4_abe -> aess (dma) */
 721 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
 722         .master         = &omap44xx_l4_abe_hwmod,
 723         .slave          = &omap44xx_aess_hwmod,
 724         .clk            = "ocp_abe_iclk",
 725         .addr           = omap44xx_aess_dma_addrs,
 726         .addr_cnt       = ARRAY_SIZE(omap44xx_aess_dma_addrs),
 727         .user           = OCP_USER_SDMA,
 728 };
 729
 730 /* aess slave ports */
 731 static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
 732         &omap44xx_l4_abe__aess,
 733         &omap44xx_l4_abe__aess_dma,
 734 };
 735
 736 static struct omap_hwmod omap44xx_aess_hwmod = {
 737         .name           = "aess",
 738         .class          = &omap44xx_aess_hwmod_class,
 739         .mpu_irqs       = omap44xx_aess_irqs,
 740         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_aess_irqs),
 741         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 742         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_aess_sdma_reqs),
 743         .main_clk       = "aess_fck",
 744         .prcm           = {
 745                 .omap4 = {
 746                         .clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
 747                 },
 748         },
 749         .slaves         = omap44xx_aess_slaves,
 750         .slaves_cnt     = ARRAY_SIZE(omap44xx_aess_slaves),
 751         .masters        = omap44xx_aess_masters,
 752         .masters_cnt    = ARRAY_SIZE(omap44xx_aess_masters),
 753         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 754 };
 755
 756 /*
 757  * 'bandgap' class
 758  * bangap reference for ldo regulators
 759  */
 760
 761 static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
 762         .name   = "bandgap",
 763 };
 764
 765 /* bandgap */
 766 static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
 767         { .role = "fclk", .clk = "bandgap_fclk" },
 768 };
 769
 770 static struct omap_hwmod omap44xx_bandgap_hwmod = {
 771         .name           = "bandgap",
 772         .class          = &omap44xx_bandgap_hwmod_class,
 773         .prcm           = {
 774                 .omap4 = {
 775                         .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
 776                 },
 777         },
 778         .opt_clks       = bandgap_opt_clks,
 779         .opt_clks_cnt   = ARRAY_SIZE(bandgap_opt_clks),
 780         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 781 };
 782
 783 /*
 784  * 'counter' class
 785  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 786  */
 787
 788 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 789         .rev_offs       = 0x0000,
 790         .sysc_offs      = 0x0004,
 791         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 792         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 793                            SIDLE_SMART_WKUP),
 794         .sysc_fields    = &omap_hwmod_sysc_type1,
 795 };
 796
 797 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 798         .name   = "counter",
 799         .sysc   = &omap44xx_counter_sysc,
 800 };
 801
 802 /* counter_32k */
 803 static struct omap_hwmod omap44xx_counter_32k_hwmod;
 804 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
 805         {
 806                 .pa_start       = 0x4a304000,
 807                 .pa_end         = 0x4a30401f,
 808                 .flags          = ADDR_TYPE_RT
 809         },
 810 };
 811
 812 /* l4_wkup -> counter_32k */
 813 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
 814         .master         = &omap44xx_l4_wkup_hwmod,
 815         .slave          = &omap44xx_counter_32k_hwmod,
 816         .clk            = "l4_wkup_clk_mux_ck",
 817         .addr           = omap44xx_counter_32k_addrs,
 818         .addr_cnt       = ARRAY_SIZE(omap44xx_counter_32k_addrs),
 819         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 820 };
 821
 822 /* counter_32k slave ports */
 823 static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
 824         &omap44xx_l4_wkup__counter_32k,
 825 };
 826
 827 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 828         .name           = "counter_32k",
 829         .class          = &omap44xx_counter_hwmod_class,
 830         .flags          = HWMOD_SWSUP_SIDLE,
 831         .main_clk       = "sys_32k_ck",
 832         .prcm           = {
 833                 .omap4 = {
 834                         .clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL,
 835                 },
 836         },
 837         .slaves         = omap44xx_counter_32k_slaves,
 838         .slaves_cnt     = ARRAY_SIZE(omap44xx_counter_32k_slaves),
 839         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 840 };
 841
 842 /*
 843  * 'dma' class
 844  * dma controller for data exchange between memory to memory (i.e. internal or
 845  * external memory) and gp peripherals to memory or memory to gp peripherals
 846  */
 847
 848 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 849         .rev_offs       = 0x0000,
 850         .sysc_offs      = 0x002c,
 851         .syss_offs      = 0x0028,
 852         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 853                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 854                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 855                            SYSS_HAS_RESET_STATUS),
 856         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 857                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 858         .sysc_fields    = &omap_hwmod_sysc_type1,
 859 };
 860
 861 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 862         .name   = "dma",
 863         .sysc   = &omap44xx_dma_sysc,
 864 };
 865
 866 /* dma dev_attr */
 867 static struct omap_dma_dev_attr dma_dev_attr = {
 868         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 869                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 870         .lch_count      = 32,
 871 };
 872
 873 /* dma_system */
 874 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 875         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 876         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 877         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 878         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 879 };
 880
 881 /* dma_system master ports */
 882 static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
 883         &omap44xx_dma_system__l3_main_2,
 884 };
 885
 886 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
 887         {
 888                 .pa_start       = 0x4a056000,
 889                 .pa_end         = 0x4a056fff,
 890                 .flags          = ADDR_TYPE_RT
 891         },
 892 };
 893
 894 /* l4_cfg -> dma_system */
 895 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
 896         .master         = &omap44xx_l4_cfg_hwmod,
 897         .slave          = &omap44xx_dma_system_hwmod,
 898         .clk            = "l4_div_ck",
 899         .addr           = omap44xx_dma_system_addrs,
 900         .addr_cnt       = ARRAY_SIZE(omap44xx_dma_system_addrs),
 901         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 902 };
 903
 904 /* dma_system slave ports */
 905 static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
 906         &omap44xx_l4_cfg__dma_system,
 907 };
 908
 909 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 910         .name           = "dma_system",
 911         .class          = &omap44xx_dma_hwmod_class,
 912         .mpu_irqs       = omap44xx_dma_system_irqs,
 913         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dma_system_irqs),
 914         .main_clk       = "l3_div_ck",
 915         .prcm = {
 916                 .omap4 = {
 917                         .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
 918                 },
 919         },
 920         .dev_attr       = &dma_dev_attr,
 921         .slaves         = omap44xx_dma_system_slaves,
 922         .slaves_cnt     = ARRAY_SIZE(omap44xx_dma_system_slaves),
 923         .masters        = omap44xx_dma_system_masters,
 924         .masters_cnt    = ARRAY_SIZE(omap44xx_dma_system_masters),
 925         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 926 };
 927
 928 /*
 929  * 'dmic' class
 930  * digital microphone controller
 931  */
 932
 933 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 934         .rev_offs       = 0x0000,
 935         .sysc_offs      = 0x0010,
 936         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 937                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 938         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 939                            SIDLE_SMART_WKUP),
 940         .sysc_fields    = &omap_hwmod_sysc_type2,
 941 };
 942
 943 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 944         .name   = "dmic",
 945         .sysc   = &omap44xx_dmic_sysc,
 946 };
 947
 948 /* dmic */
 949 static struct omap_hwmod omap44xx_dmic_hwmod;
 950 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
 951         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
 952 };
 953
 954 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
 955         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
 956 };
 957
 958 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
 959         {
 960                 .pa_start       = 0x4012e000,
 961                 .pa_end         = 0x4012e07f,
 962                 .flags          = ADDR_TYPE_RT
 963         },
 964 };
 965
 966 /* l4_abe -> dmic */
 967 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
 968         .master         = &omap44xx_l4_abe_hwmod,
 969         .slave          = &omap44xx_dmic_hwmod,
 970         .clk            = "ocp_abe_iclk",
 971         .addr           = omap44xx_dmic_addrs,
 972         .addr_cnt       = ARRAY_SIZE(omap44xx_dmic_addrs),
 973         .user           = OCP_USER_MPU,
 974 };
 975
 976 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
 977         {
 978                 .pa_start       = 0x4902e000,
 979                 .pa_end         = 0x4902e07f,
 980                 .flags          = ADDR_TYPE_RT
 981         },
 982 };
 983
 984 /* l4_abe -> dmic (dma) */
 985 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
 986         .master         = &omap44xx_l4_abe_hwmod,
 987         .slave          = &omap44xx_dmic_hwmod,
 988         .clk            = "ocp_abe_iclk",
 989         .addr           = omap44xx_dmic_dma_addrs,
 990         .addr_cnt       = ARRAY_SIZE(omap44xx_dmic_dma_addrs),
 991         .user           = OCP_USER_SDMA,
 992 };
 993
 994 /* dmic slave ports */
 995 static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
 996         &omap44xx_l4_abe__dmic,
 997         &omap44xx_l4_abe__dmic_dma,
 998 };
 999
1000 static struct omap_hwmod omap44xx_dmic_hwmod = {
1001         .name           = "dmic",
1002         .class          = &omap44xx_dmic_hwmod_class,
1003         .mpu_irqs       = omap44xx_dmic_irqs,
1004         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dmic_irqs),
1005         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
1006         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dmic_sdma_reqs),
1007         .main_clk       = "dmic_fck",
1008         .prcm           = {
1009                 .omap4 = {
1010                         .clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1011                 },
1012         },
1013         .slaves         = omap44xx_dmic_slaves,
1014         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmic_slaves),
1015         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1016 };
1017
1018 /*
1019  * 'dsp' class
1020  * dsp sub-system
1021  */
1022
1023 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
1024         .name   = "dsp",
1025 };
1026
1027 /* dsp */
1028 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
1029         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
1030 };
1031
1032 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
1033         { .name = "mmu_cache", .rst_shift = 1 },
1034 };
1035
1036 static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
1037         { .name = "dsp", .rst_shift = 0 },
1038 };
1039
1040 /* dsp -> iva */
1041 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
1042         .master         = &omap44xx_dsp_hwmod,
1043         .slave          = &omap44xx_iva_hwmod,
1044         .clk            = "dpll_iva_m5x2_ck",
1045 };
1046
1047 /* dsp master ports */
1048 static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
1049         &omap44xx_dsp__l3_main_1,
1050         &omap44xx_dsp__l4_abe,
1051         &omap44xx_dsp__iva,
1052 };
1053
1054 /* l4_cfg -> dsp */
1055 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
1056         .master         = &omap44xx_l4_cfg_hwmod,
1057         .slave          = &omap44xx_dsp_hwmod,
1058         .clk            = "l4_div_ck",
1059         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1060 };
1061
1062 /* dsp slave ports */
1063 static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
1064         &omap44xx_l4_cfg__dsp,
1065 };
1066
1067 /* Pseudo hwmod for reset control purpose only */
1068 static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
1069         .name           = "dsp_c0",
1070         .class          = &omap44xx_dsp_hwmod_class,
1071         .flags          = HWMOD_INIT_NO_RESET,
1072         .rst_lines      = omap44xx_dsp_c0_resets,
1073         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_c0_resets),
1074         .prcm = {
1075                 .omap4 = {
1076                         .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
1077                 },
1078         },
1079         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1080 };
1081
1082 static struct omap_hwmod omap44xx_dsp_hwmod = {
1083         .name           = "dsp",
1084         .class          = &omap44xx_dsp_hwmod_class,
1085         .mpu_irqs       = omap44xx_dsp_irqs,
1086         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dsp_irqs),
1087         .rst_lines      = omap44xx_dsp_resets,
1088         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
1089         .main_clk       = "dsp_fck",
1090         .prcm = {
1091                 .omap4 = {
1092                         .clkctrl_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1093                         .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
1094                 },
1095         },
1096         .slaves         = omap44xx_dsp_slaves,
1097         .slaves_cnt     = ARRAY_SIZE(omap44xx_dsp_slaves),
1098         .masters        = omap44xx_dsp_masters,
1099         .masters_cnt    = ARRAY_SIZE(omap44xx_dsp_masters),
1100         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1101 };
1102
1103 /*
1104  * 'dss' class
1105  * display sub-system
1106  */
1107
1108 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
1109         .rev_offs       = 0x0000,
1110         .syss_offs      = 0x0014,
1111         .sysc_flags     = SYSS_HAS_RESET_STATUS,
1112 };
1113
1114 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1115         .name   = "dss",
1116         .sysc   = &omap44xx_dss_sysc,
1117 };
1118
1119 /* dss */
1120 /* dss master ports */
1121 static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
1122         &omap44xx_dss__l3_main_1,
1123 };
1124
1125 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1126         {
1127                 .pa_start       = 0x58000000,
1128                 .pa_end         = 0x5800007f,
1129                 .flags          = ADDR_TYPE_RT
1130         },
1131 };
1132
1133 /* l3_main_2 -> dss */
1134 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1135         .master         = &omap44xx_l3_main_2_hwmod,
1136         .slave          = &omap44xx_dss_hwmod,
1137         .clk            = "l3_div_ck",
1138         .addr           = omap44xx_dss_dma_addrs,
1139         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dma_addrs),
1140         .user           = OCP_USER_SDMA,
1141 };
1142
1143 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1144         {
1145                 .pa_start       = 0x48040000,
1146                 .pa_end         = 0x4804007f,
1147                 .flags          = ADDR_TYPE_RT
1148         },
1149 };
1150
1151 /* l4_per -> dss */
1152 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1153         .master         = &omap44xx_l4_per_hwmod,
1154         .slave          = &omap44xx_dss_hwmod,
1155         .clk            = "l4_div_ck",
1156         .addr           = omap44xx_dss_addrs,
1157         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_addrs),
1158         .user           = OCP_USER_MPU,
1159 };
1160
1161 /* dss slave ports */
1162 static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1163         &omap44xx_l3_main_2__dss,
1164         &omap44xx_l4_per__dss,
1165 };
1166
1167 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1168         { .role = "sys_clk", .clk = "dss_sys_clk" },
1169         { .role = "tv_clk", .clk = "dss_tv_clk" },
1170         { .role = "dss_clk", .clk = "dss_dss_clk" },
1171         { .role = "video_clk", .clk = "dss_48mhz_clk" },
1172 };
1173
1174 static struct omap_hwmod omap44xx_dss_hwmod = {
1175         .name           = "dss_core",
1176         .class          = &omap44xx_dss_hwmod_class,
1177         .main_clk       = "dss_fck",
1178         .prcm = {
1179                 .omap4 = {
1180                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1181                 },
1182         },
1183         .opt_clks       = dss_opt_clks,
1184         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
1185         .slaves         = omap44xx_dss_slaves,
1186         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_slaves),
1187         .masters        = omap44xx_dss_masters,
1188         .masters_cnt    = ARRAY_SIZE(omap44xx_dss_masters),
1189         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1190 };
1191
1192 /*
1193  * 'dispc' class
1194  * display controller
1195  */
1196
1197 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
1198         .rev_offs       = 0x0000,
1199         .sysc_offs      = 0x0010,
1200         .syss_offs      = 0x0014,
1201         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1202                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
1203                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1204                            SYSS_HAS_RESET_STATUS),
1205         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1206                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1207         .sysc_fields    = &omap_hwmod_sysc_type1,
1208 };
1209
1210 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1211         .name   = "dispc",
1212         .sysc   = &omap44xx_dispc_sysc,
1213 };
1214
1215 /* dss_dispc */
1216 static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1217 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1218         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
1219 };
1220
1221 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1222         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
1223 };
1224
1225 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1226         {
1227                 .pa_start       = 0x58001000,
1228                 .pa_end         = 0x58001fff,
1229                 .flags          = ADDR_TYPE_RT
1230         },
1231 };
1232
1233 /* l3_main_2 -> dss_dispc */
1234 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1235         .master         = &omap44xx_l3_main_2_hwmod,
1236         .slave          = &omap44xx_dss_dispc_hwmod,
1237         .clk            = "l3_div_ck",
1238         .addr           = omap44xx_dss_dispc_dma_addrs,
1239         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dispc_dma_addrs),
1240         .user           = OCP_USER_SDMA,
1241 };
1242
1243 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1244         {
1245                 .pa_start       = 0x48041000,
1246                 .pa_end         = 0x48041fff,
1247                 .flags          = ADDR_TYPE_RT
1248         },
1249 };
1250
1251 /* l4_per -> dss_dispc */
1252 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1253         .master         = &omap44xx_l4_per_hwmod,
1254         .slave          = &omap44xx_dss_dispc_hwmod,
1255         .clk            = "l4_div_ck",
1256         .addr           = omap44xx_dss_dispc_addrs,
1257         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dispc_addrs),
1258         .user           = OCP_USER_MPU,
1259 };
1260
1261 /* dss_dispc slave ports */
1262 static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1263         &omap44xx_l3_main_2__dss_dispc,
1264         &omap44xx_l4_per__dss_dispc,
1265 };
1266
1267 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1268         .name           = "dss_dispc",
1269         .class          = &omap44xx_dispc_hwmod_class,
1270         .mpu_irqs       = omap44xx_dss_dispc_irqs,
1271         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dss_dispc_irqs),
1272         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
1273         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_dispc_sdma_reqs),
1274         .main_clk       = "dss_fck",
1275         .prcm = {
1276                 .omap4 = {
1277                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1278                 },
1279         },
1280         .slaves         = omap44xx_dss_dispc_slaves,
1281         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1282         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1283 };
1284
1285 /*
1286  * 'dsi' class
1287  * display serial interface controller
1288  */
1289
1290 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
1291         .rev_offs       = 0x0000,
1292         .sysc_offs      = 0x0010,
1293         .syss_offs      = 0x0014,
1294         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1295                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1296                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1297         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1298         .sysc_fields    = &omap_hwmod_sysc_type1,
1299 };
1300
1301 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1302         .name   = "dsi",
1303         .sysc   = &omap44xx_dsi_sysc,
1304 };
1305
1306 /* dss_dsi1 */
1307 static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1308 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1309         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
1310 };
1311
1312 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1313         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
1314 };
1315
1316 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1317         {
1318                 .pa_start       = 0x58004000,
1319                 .pa_end         = 0x580041ff,
1320                 .flags          = ADDR_TYPE_RT
1321         },
1322 };
1323
1324 /* l3_main_2 -> dss_dsi1 */
1325 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1326         .master         = &omap44xx_l3_main_2_hwmod,
1327         .slave          = &omap44xx_dss_dsi1_hwmod,
1328         .clk            = "l3_div_ck",
1329         .addr           = omap44xx_dss_dsi1_dma_addrs,
1330         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dsi1_dma_addrs),
1331         .user           = OCP_USER_SDMA,
1332 };
1333
1334 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1335         {
1336                 .pa_start       = 0x48044000,
1337                 .pa_end         = 0x480441ff,
1338                 .flags          = ADDR_TYPE_RT
1339         },
1340 };
1341
1342 /* l4_per -> dss_dsi1 */
1343 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1344         .master         = &omap44xx_l4_per_hwmod,
1345         .slave          = &omap44xx_dss_dsi1_hwmod,
1346         .clk            = "l4_div_ck",
1347         .addr           = omap44xx_dss_dsi1_addrs,
1348         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dsi1_addrs),
1349         .user           = OCP_USER_MPU,
1350 };
1351
1352 /* dss_dsi1 slave ports */
1353 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1354         &omap44xx_l3_main_2__dss_dsi1,
1355         &omap44xx_l4_per__dss_dsi1,
1356 };
1357
1358 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1359         .name           = "dss_dsi1",
1360         .class          = &omap44xx_dsi_hwmod_class,
1361         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
1362         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dss_dsi1_irqs),
1363         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
1364         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs),
1365         .main_clk       = "dss_fck",
1366         .prcm = {
1367                 .omap4 = {
1368                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1369                 },
1370         },
1371         .slaves         = omap44xx_dss_dsi1_slaves,
1372         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1373         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1374 };
1375
1376 /* dss_dsi2 */
1377 static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1378 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1379         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1380 };
1381
1382 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1383         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
1384 };
1385
1386 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1387         {
1388                 .pa_start       = 0x58005000,
1389                 .pa_end         = 0x580051ff,
1390                 .flags          = ADDR_TYPE_RT
1391         },
1392 };
1393
1394 /* l3_main_2 -> dss_dsi2 */
1395 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1396         .master         = &omap44xx_l3_main_2_hwmod,
1397         .slave          = &omap44xx_dss_dsi2_hwmod,
1398         .clk            = "l3_div_ck",
1399         .addr           = omap44xx_dss_dsi2_dma_addrs,
1400         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dsi2_dma_addrs),
1401         .user           = OCP_USER_SDMA,
1402 };
1403
1404 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1405         {
1406                 .pa_start       = 0x48045000,
1407                 .pa_end         = 0x480451ff,
1408                 .flags          = ADDR_TYPE_RT
1409         },
1410 };
1411
1412 /* l4_per -> dss_dsi2 */
1413 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1414         .master         = &omap44xx_l4_per_hwmod,
1415         .slave          = &omap44xx_dss_dsi2_hwmod,
1416         .clk            = "l4_div_ck",
1417         .addr           = omap44xx_dss_dsi2_addrs,
1418         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dsi2_addrs),
1419         .user           = OCP_USER_MPU,
1420 };
1421
1422 /* dss_dsi2 slave ports */
1423 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1424         &omap44xx_l3_main_2__dss_dsi2,
1425         &omap44xx_l4_per__dss_dsi2,
1426 };
1427
1428 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1429         .name           = "dss_dsi2",
1430         .class          = &omap44xx_dsi_hwmod_class,
1431         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
1432         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dss_dsi2_irqs),
1433         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
1434         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_dsi2_sdma_reqs),
1435         .main_clk       = "dss_fck",
1436         .prcm = {
1437                 .omap4 = {
1438                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1439                 },
1440         },
1441         .slaves         = omap44xx_dss_dsi2_slaves,
1442         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1443         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1444 };
1445
1446 /*
1447  * 'hdmi' class
1448  * hdmi controller
1449  */
1450
1451 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1452         .rev_offs       = 0x0000,
1453         .sysc_offs      = 0x0010,
1454         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1455                            SYSC_HAS_SOFTRESET),
1456         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1457                            SIDLE_SMART_WKUP),
1458         .sysc_fields    = &omap_hwmod_sysc_type2,
1459 };
1460
1461 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1462         .name   = "hdmi",
1463         .sysc   = &omap44xx_hdmi_sysc,
1464 };
1465
1466 /* dss_hdmi */
1467 static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1468 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1469         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1470 };
1471
1472 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1473         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1474 };
1475
1476 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1477         {
1478                 .pa_start       = 0x58006000,
1479                 .pa_end         = 0x58006fff,
1480                 .flags          = ADDR_TYPE_RT
1481         },
1482 };
1483
1484 /* l3_main_2 -> dss_hdmi */
1485 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1486         .master         = &omap44xx_l3_main_2_hwmod,
1487         .slave          = &omap44xx_dss_hdmi_hwmod,
1488         .clk            = "l3_div_ck",
1489         .addr           = omap44xx_dss_hdmi_dma_addrs,
1490         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_hdmi_dma_addrs),
1491         .user           = OCP_USER_SDMA,
1492 };
1493
1494 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1495         {
1496                 .pa_start       = 0x48046000,
1497                 .pa_end         = 0x48046fff,
1498                 .flags          = ADDR_TYPE_RT
1499         },
1500 };
1501
1502 /* l4_per -> dss_hdmi */
1503 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1504         .master         = &omap44xx_l4_per_hwmod,
1505         .slave          = &omap44xx_dss_hdmi_hwmod,
1506         .clk            = "l4_div_ck",
1507         .addr           = omap44xx_dss_hdmi_addrs,
1508         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_hdmi_addrs),
1509         .user           = OCP_USER_MPU,
1510 };
1511
1512 /* dss_hdmi slave ports */
1513 static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1514         &omap44xx_l3_main_2__dss_hdmi,
1515         &omap44xx_l4_per__dss_hdmi,
1516 };
1517
1518 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1519         .name           = "dss_hdmi",
1520         .class          = &omap44xx_hdmi_hwmod_class,
1521         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
1522         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dss_hdmi_irqs),
1523         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
1524         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_hdmi_sdma_reqs),
1525         .main_clk       = "dss_fck",
1526         .prcm = {
1527                 .omap4 = {
1528                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1529                 },
1530         },
1531         .slaves         = omap44xx_dss_hdmi_slaves,
1532         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1533         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1534 };
1535
1536 /*
1537  * 'rfbi' class
1538  * remote frame buffer interface
1539  */
1540
1541 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1542         .rev_offs       = 0x0000,
1543         .sysc_offs      = 0x0010,
1544         .syss_offs      = 0x0014,
1545         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1546                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1547         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1548         .sysc_fields    = &omap_hwmod_sysc_type1,
1549 };
1550
1551 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1552         .name   = "rfbi",
1553         .sysc   = &omap44xx_rfbi_sysc,
1554 };
1555
1556 /* dss_rfbi */
1557 static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1558 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1559         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1560 };
1561
1562 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1563         {
1564                 .pa_start       = 0x58002000,
1565                 .pa_end         = 0x580020ff,
1566                 .flags          = ADDR_TYPE_RT
1567         },
1568 };
1569
1570 /* l3_main_2 -> dss_rfbi */
1571 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1572         .master         = &omap44xx_l3_main_2_hwmod,
1573         .slave          = &omap44xx_dss_rfbi_hwmod,
1574         .clk            = "l3_div_ck",
1575         .addr           = omap44xx_dss_rfbi_dma_addrs,
1576         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_rfbi_dma_addrs),
1577         .user           = OCP_USER_SDMA,
1578 };
1579
1580 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1581         {
1582                 .pa_start       = 0x48042000,
1583                 .pa_end         = 0x480420ff,
1584                 .flags          = ADDR_TYPE_RT
1585         },
1586 };
1587
1588 /* l4_per -> dss_rfbi */
1589 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1590         .master         = &omap44xx_l4_per_hwmod,
1591         .slave          = &omap44xx_dss_rfbi_hwmod,
1592         .clk            = "l4_div_ck",
1593         .addr           = omap44xx_dss_rfbi_addrs,
1594         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_rfbi_addrs),
1595         .user           = OCP_USER_MPU,
1596 };
1597
1598 /* dss_rfbi slave ports */
1599 static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1600         &omap44xx_l3_main_2__dss_rfbi,
1601         &omap44xx_l4_per__dss_rfbi,
1602 };
1603
1604 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1605         .name           = "dss_rfbi",
1606         .class          = &omap44xx_rfbi_hwmod_class,
1607         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
1608         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_rfbi_sdma_reqs),
1609         .main_clk       = "dss_fck",
1610         .prcm = {
1611                 .omap4 = {
1612                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1613                 },
1614         },
1615         .slaves         = omap44xx_dss_rfbi_slaves,
1616         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1617         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1618 };
1619
1620 /*
1621  * 'venc' class
1622  * video encoder
1623  */
1624
1625 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1626         .name   = "venc",
1627 };
1628
1629 /* dss_venc */
1630 static struct omap_hwmod omap44xx_dss_venc_hwmod;
1631 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1632         {
1633                 .pa_start       = 0x58003000,
1634                 .pa_end         = 0x580030ff,
1635                 .flags          = ADDR_TYPE_RT
1636         },
1637 };
1638
1639 /* l3_main_2 -> dss_venc */
1640 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1641         .master         = &omap44xx_l3_main_2_hwmod,
1642         .slave          = &omap44xx_dss_venc_hwmod,
1643         .clk            = "l3_div_ck",
1644         .addr           = omap44xx_dss_venc_dma_addrs,
1645         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_venc_dma_addrs),
1646         .user           = OCP_USER_SDMA,
1647 };
1648
1649 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1650         {
1651                 .pa_start       = 0x48043000,
1652                 .pa_end         = 0x480430ff,
1653                 .flags          = ADDR_TYPE_RT
1654         },
1655 };
1656
1657 /* l4_per -> dss_venc */
1658 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1659         .master         = &omap44xx_l4_per_hwmod,
1660         .slave          = &omap44xx_dss_venc_hwmod,
1661         .clk            = "l4_div_ck",
1662         .addr           = omap44xx_dss_venc_addrs,
1663         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_venc_addrs),
1664         .user           = OCP_USER_MPU,
1665 };
1666
1667 /* dss_venc slave ports */
1668 static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1669         &omap44xx_l3_main_2__dss_venc,
1670         &omap44xx_l4_per__dss_venc,
1671 };
1672
1673 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1674         .name           = "dss_venc",
1675         .class          = &omap44xx_venc_hwmod_class,
1676         .main_clk       = "dss_fck",
1677         .prcm = {
1678                 .omap4 = {
1679                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1680                 },
1681         },
1682         .slaves         = omap44xx_dss_venc_slaves,
1683         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1684         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1685 };
1686
1687 /*
1688  * 'gpio' class
1689  * general purpose io module
1690  */
1691
1692 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1693         .rev_offs       = 0x0000,
1694         .sysc_offs      = 0x0010,
1695         .syss_offs      = 0x0114,
1696         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1697                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1698                            SYSS_HAS_RESET_STATUS),
1699         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1700                            SIDLE_SMART_WKUP),
1701         .sysc_fields    = &omap_hwmod_sysc_type1,
1702 };
1703
1704 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1705         .name   = "gpio",
1706         .sysc   = &omap44xx_gpio_sysc,
1707         .rev    = 2,
1708 };
1709
1710 /* gpio dev_attr */
1711 static struct omap_gpio_dev_attr gpio_dev_attr = {
1712         .bank_width     = 32,
1713         .dbck_flag      = true,
1714 };
1715
1716 /* gpio1 */
1717 static struct omap_hwmod omap44xx_gpio1_hwmod;
1718 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1719         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1720 };
1721
1722 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1723         {
1724                 .pa_start       = 0x4a310000,
1725                 .pa_end         = 0x4a3101ff,
1726                 .flags          = ADDR_TYPE_RT
1727         },
1728 };
1729
1730 /* l4_wkup -> gpio1 */
1731 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1732         .master         = &omap44xx_l4_wkup_hwmod,
1733         .slave          = &omap44xx_gpio1_hwmod,
1734         .clk            = "l4_wkup_clk_mux_ck",
1735         .addr           = omap44xx_gpio1_addrs,
1736         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio1_addrs),
1737         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1738 };
1739
1740 /* gpio1 slave ports */
1741 static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1742         &omap44xx_l4_wkup__gpio1,
1743 };
1744
1745 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1746         { .role = "dbclk", .clk = "gpio1_dbclk" },
1747 };
1748
1749 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1750         .name           = "gpio1",
1751         .class          = &omap44xx_gpio_hwmod_class,
1752         .mpu_irqs       = omap44xx_gpio1_irqs,
1753         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio1_irqs),
1754         .main_clk       = "gpio1_ick",
1755         .prcm = {
1756                 .omap4 = {
1757                         .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1758                 },
1759         },
1760         .opt_clks       = gpio1_opt_clks,
1761         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1762         .dev_attr       = &gpio_dev_attr,
1763         .slaves         = omap44xx_gpio1_slaves,
1764         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio1_slaves),
1765         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1766 };
1767
1768 /* gpio2 */
1769 static struct omap_hwmod omap44xx_gpio2_hwmod;
1770 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1771         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1772 };
1773
1774 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1775         {
1776                 .pa_start       = 0x48055000,
1777                 .pa_end         = 0x480551ff,
1778                 .flags          = ADDR_TYPE_RT
1779         },
1780 };
1781
1782 /* l4_per -> gpio2 */
1783 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1784         .master         = &omap44xx_l4_per_hwmod,
1785         .slave          = &omap44xx_gpio2_hwmod,
1786         .clk            = "l4_div_ck",
1787         .addr           = omap44xx_gpio2_addrs,
1788         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio2_addrs),
1789         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1790 };
1791
1792 /* gpio2 slave ports */
1793 static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1794         &omap44xx_l4_per__gpio2,
1795 };
1796
1797 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1798         { .role = "dbclk", .clk = "gpio2_dbclk" },
1799 };
1800
1801 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1802         .name           = "gpio2",
1803         .class          = &omap44xx_gpio_hwmod_class,
1804         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1805         .mpu_irqs       = omap44xx_gpio2_irqs,
1806         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio2_irqs),
1807         .main_clk       = "gpio2_ick",
1808         .prcm = {
1809                 .omap4 = {
1810                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1811                 },
1812         },
1813         .opt_clks       = gpio2_opt_clks,
1814         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1815         .dev_attr       = &gpio_dev_attr,
1816         .slaves         = omap44xx_gpio2_slaves,
1817         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio2_slaves),
1818         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1819 };
1820
1821 /* gpio3 */
1822 static struct omap_hwmod omap44xx_gpio3_hwmod;
1823 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1824         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1825 };
1826
1827 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1828         {
1829                 .pa_start       = 0x48057000,
1830                 .pa_end         = 0x480571ff,
1831                 .flags          = ADDR_TYPE_RT
1832         },
1833 };
1834
1835 /* l4_per -> gpio3 */
1836 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1837         .master         = &omap44xx_l4_per_hwmod,
1838         .slave          = &omap44xx_gpio3_hwmod,
1839         .clk            = "l4_div_ck",
1840         .addr           = omap44xx_gpio3_addrs,
1841         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio3_addrs),
1842         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1843 };
1844
1845 /* gpio3 slave ports */
1846 static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1847         &omap44xx_l4_per__gpio3,
1848 };
1849
1850 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1851         { .role = "dbclk", .clk = "gpio3_dbclk" },
1852 };
1853
1854 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1855         .name           = "gpio3",
1856         .class          = &omap44xx_gpio_hwmod_class,
1857         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1858         .mpu_irqs       = omap44xx_gpio3_irqs,
1859         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio3_irqs),
1860         .main_clk       = "gpio3_ick",
1861         .prcm = {
1862                 .omap4 = {
1863                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1864                 },
1865         },
1866         .opt_clks       = gpio3_opt_clks,
1867         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1868         .dev_attr       = &gpio_dev_attr,
1869         .slaves         = omap44xx_gpio3_slaves,
1870         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio3_slaves),
1871         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1872 };
1873
1874 /* gpio4 */
1875 static struct omap_hwmod omap44xx_gpio4_hwmod;
1876 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1877         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1878 };
1879
1880 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
1881         {
1882                 .pa_start       = 0x48059000,
1883                 .pa_end         = 0x480591ff,
1884                 .flags          = ADDR_TYPE_RT
1885         },
1886 };
1887
1888 /* l4_per -> gpio4 */
1889 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
1890         .master         = &omap44xx_l4_per_hwmod,
1891         .slave          = &omap44xx_gpio4_hwmod,
1892         .clk            = "l4_div_ck",
1893         .addr           = omap44xx_gpio4_addrs,
1894         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio4_addrs),
1895         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1896 };
1897
1898 /* gpio4 slave ports */
1899 static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
1900         &omap44xx_l4_per__gpio4,
1901 };
1902
1903 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1904         { .role = "dbclk", .clk = "gpio4_dbclk" },
1905 };
1906
1907 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1908         .name           = "gpio4",
1909         .class          = &omap44xx_gpio_hwmod_class,
1910         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1911         .mpu_irqs       = omap44xx_gpio4_irqs,
1912         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio4_irqs),
1913         .main_clk       = "gpio4_ick",
1914         .prcm = {
1915                 .omap4 = {
1916                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1917                 },
1918         },
1919         .opt_clks       = gpio4_opt_clks,
1920         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1921         .dev_attr       = &gpio_dev_attr,
1922         .slaves         = omap44xx_gpio4_slaves,
1923         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio4_slaves),
1924         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1925 };
1926
1927 /* gpio5 */
1928 static struct omap_hwmod omap44xx_gpio5_hwmod;
1929 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1930         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1931 };
1932
1933 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
1934         {
1935                 .pa_start       = 0x4805b000,
1936                 .pa_end         = 0x4805b1ff,
1937                 .flags          = ADDR_TYPE_RT
1938         },
1939 };
1940
1941 /* l4_per -> gpio5 */
1942 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
1943         .master         = &omap44xx_l4_per_hwmod,
1944         .slave          = &omap44xx_gpio5_hwmod,
1945         .clk            = "l4_div_ck",
1946         .addr           = omap44xx_gpio5_addrs,
1947         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio5_addrs),
1948         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1949 };
1950
1951 /* gpio5 slave ports */
1952 static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
1953         &omap44xx_l4_per__gpio5,
1954 };
1955
1956 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1957         { .role = "dbclk", .clk = "gpio5_dbclk" },
1958 };
1959
1960 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1961         .name           = "gpio5",
1962         .class          = &omap44xx_gpio_hwmod_class,
1963         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1964         .mpu_irqs       = omap44xx_gpio5_irqs,
1965         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio5_irqs),
1966         .main_clk       = "gpio5_ick",
1967         .prcm = {
1968                 .omap4 = {
1969                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1970                 },
1971         },
1972         .opt_clks       = gpio5_opt_clks,
1973         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1974         .dev_attr       = &gpio_dev_attr,
1975         .slaves         = omap44xx_gpio5_slaves,
1976         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio5_slaves),
1977         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1978 };
1979
1980 /* gpio6 */
1981 static struct omap_hwmod omap44xx_gpio6_hwmod;
1982 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1983         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1984 };
1985
1986 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
1987         {
1988                 .pa_start       = 0x4805d000,
1989                 .pa_end         = 0x4805d1ff,
1990                 .flags          = ADDR_TYPE_RT
1991         },
1992 };
1993
1994 /* l4_per -> gpio6 */
1995 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
1996         .master         = &omap44xx_l4_per_hwmod,
1997         .slave          = &omap44xx_gpio6_hwmod,
1998         .clk            = "l4_div_ck",
1999         .addr           = omap44xx_gpio6_addrs,
2000         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio6_addrs),
2001         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2002 };
2003
2004 /* gpio6 slave ports */
2005 static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
2006         &omap44xx_l4_per__gpio6,
2007 };
2008
2009 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2010         { .role = "dbclk", .clk = "gpio6_dbclk" },
2011 };
2012
2013 static struct omap_hwmod omap44xx_gpio6_hwmod = {
2014         .name           = "gpio6",
2015         .class          = &omap44xx_gpio_hwmod_class,
2016         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2017         .mpu_irqs       = omap44xx_gpio6_irqs,
2018         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio6_irqs),
2019         .main_clk       = "gpio6_ick",
2020         .prcm = {
2021                 .omap4 = {
2022                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
2023                 },
2024         },
2025         .opt_clks       = gpio6_opt_clks,
2026         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
2027         .dev_attr       = &gpio_dev_attr,
2028         .slaves         = omap44xx_gpio6_slaves,
2029         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio6_slaves),
2030         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2031 };
2032
2033 /*
2034  * 'hsi' class
2035  * mipi high-speed synchronous serial interface (multichannel and full-duplex
2036  * serial if)
2037  */
2038
2039 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
2040         .rev_offs       = 0x0000,
2041         .sysc_offs      = 0x0010,
2042         .syss_offs      = 0x0014,
2043         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
2044                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2045                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2046         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2047                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2048                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2049         .sysc_fields    = &omap_hwmod_sysc_type1,
2050 };
2051
2052 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
2053         .name   = "hsi",
2054         .sysc   = &omap44xx_hsi_sysc,
2055 };
2056
2057 /* hsi */
2058 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2059         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
2060         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
2061         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
2062 };
2063
2064 /* hsi master ports */
2065 static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
2066         &omap44xx_hsi__l3_main_2,
2067 };
2068
2069 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2070         {
2071                 .pa_start       = 0x4a058000,
2072                 .pa_end         = 0x4a05bfff,
2073                 .flags          = ADDR_TYPE_RT
2074         },
2075 };
2076
2077 /* l4_cfg -> hsi */
2078 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2079         .master         = &omap44xx_l4_cfg_hwmod,
2080         .slave          = &omap44xx_hsi_hwmod,
2081         .clk            = "l4_div_ck",
2082         .addr           = omap44xx_hsi_addrs,
2083         .addr_cnt       = ARRAY_SIZE(omap44xx_hsi_addrs),
2084         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2085 };
2086
2087 /* hsi slave ports */
2088 static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2089         &omap44xx_l4_cfg__hsi,
2090 };
2091
2092 static struct omap_hwmod omap44xx_hsi_hwmod = {
2093         .name           = "hsi",
2094         .class          = &omap44xx_hsi_hwmod_class,
2095         .mpu_irqs       = omap44xx_hsi_irqs,
2096         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_hsi_irqs),
2097         .main_clk       = "hsi_fck",
2098         .prcm           = {
2099                 .omap4 = {
2100                         .clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
2101                 },
2102         },
2103         .slaves         = omap44xx_hsi_slaves,
2104         .slaves_cnt     = ARRAY_SIZE(omap44xx_hsi_slaves),
2105         .masters        = omap44xx_hsi_masters,
2106         .masters_cnt    = ARRAY_SIZE(omap44xx_hsi_masters),
2107         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2108 };
2109
2110 /*
2111  * 'i2c' class
2112  * multimaster high-speed i2c controller
2113  */
2114
2115 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
2116         .sysc_offs      = 0x0010,
2117         .syss_offs      = 0x0090,
2118         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2119                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2120                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2121         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2122                            SIDLE_SMART_WKUP),
2123         .sysc_fields    = &omap_hwmod_sysc_type1,
2124 };
2125
2126 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
2127         .name   = "i2c",
2128         .sysc   = &omap44xx_i2c_sysc,
2129 };
2130
2131 /* i2c1 */
2132 static struct omap_hwmod omap44xx_i2c1_hwmod;
2133 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
2134         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
2135 };
2136
2137 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
2138         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
2139         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
2140 };
2141
2142 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
2143         {
2144                 .pa_start       = 0x48070000,
2145                 .pa_end         = 0x480700ff,
2146                 .flags          = ADDR_TYPE_RT
2147         },
2148 };
2149
2150 /* l4_per -> i2c1 */
2151 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
2152         .master         = &omap44xx_l4_per_hwmod,
2153         .slave          = &omap44xx_i2c1_hwmod,
2154         .clk            = "l4_div_ck",
2155         .addr           = omap44xx_i2c1_addrs,
2156         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c1_addrs),
2157         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2158 };
2159
2160 /* i2c1 slave ports */
2161 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
2162         &omap44xx_l4_per__i2c1,
2163 };
2164
2165 static struct omap_hwmod omap44xx_i2c1_hwmod = {
2166         .name           = "i2c1",
2167         .class          = &omap44xx_i2c_hwmod_class,
2168         .flags          = HWMOD_INIT_NO_RESET,
2169         .mpu_irqs       = omap44xx_i2c1_irqs,
2170         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c1_irqs),
2171         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
2172         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
2173         .main_clk       = "i2c1_fck",
2174         .prcm = {
2175                 .omap4 = {
2176                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
2177                 },
2178         },
2179         .slaves         = omap44xx_i2c1_slaves,
2180         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c1_slaves),
2181         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2182 };
2183
2184 /* i2c2 */
2185 static struct omap_hwmod omap44xx_i2c2_hwmod;
2186 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
2187         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
2188 };
2189
2190 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2191         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
2192         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
2193 };
2194
2195 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
2196         {
2197                 .pa_start       = 0x48072000,
2198                 .pa_end         = 0x480720ff,
2199                 .flags          = ADDR_TYPE_RT
2200         },
2201 };
2202
2203 /* l4_per -> i2c2 */
2204 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
2205         .master         = &omap44xx_l4_per_hwmod,
2206         .slave          = &omap44xx_i2c2_hwmod,
2207         .clk            = "l4_div_ck",
2208         .addr           = omap44xx_i2c2_addrs,
2209         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c2_addrs),
2210         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2211 };
2212
2213 /* i2c2 slave ports */
2214 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
2215         &omap44xx_l4_per__i2c2,
2216 };
2217
2218 static struct omap_hwmod omap44xx_i2c2_hwmod = {
2219         .name           = "i2c2",
2220         .class          = &omap44xx_i2c_hwmod_class,
2221         .flags          = HWMOD_INIT_NO_RESET,
2222         .mpu_irqs       = omap44xx_i2c2_irqs,
2223         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c2_irqs),
2224         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
2225         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
2226         .main_clk       = "i2c2_fck",
2227         .prcm = {
2228                 .omap4 = {
2229                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
2230                 },
2231         },
2232         .slaves         = omap44xx_i2c2_slaves,
2233         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c2_slaves),
2234         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2235 };
2236
2237 /* i2c3 */
2238 static struct omap_hwmod omap44xx_i2c3_hwmod;
2239 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2240         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
2241 };
2242
2243 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2244         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
2245         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
2246 };
2247
2248 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
2249         {
2250                 .pa_start       = 0x48060000,
2251                 .pa_end         = 0x480600ff,
2252                 .flags          = ADDR_TYPE_RT
2253         },
2254 };
2255
2256 /* l4_per -> i2c3 */
2257 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
2258         .master         = &omap44xx_l4_per_hwmod,
2259         .slave          = &omap44xx_i2c3_hwmod,
2260         .clk            = "l4_div_ck",
2261         .addr           = omap44xx_i2c3_addrs,
2262         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c3_addrs),
2263         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2264 };
2265
2266 /* i2c3 slave ports */
2267 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
2268         &omap44xx_l4_per__i2c3,
2269 };
2270
2271 static struct omap_hwmod omap44xx_i2c3_hwmod = {
2272         .name           = "i2c3",
2273         .class          = &omap44xx_i2c_hwmod_class,
2274         .flags          = HWMOD_INIT_NO_RESET,
2275         .mpu_irqs       = omap44xx_i2c3_irqs,
2276         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c3_irqs),
2277         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
2278         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
2279         .main_clk       = "i2c3_fck",
2280         .prcm = {
2281                 .omap4 = {
2282                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
2283                 },
2284         },
2285         .slaves         = omap44xx_i2c3_slaves,
2286         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c3_slaves),
2287         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2288 };
2289
2290 /* i2c4 */
2291 static struct omap_hwmod omap44xx_i2c4_hwmod;
2292 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2293         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
2294 };
2295
2296 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2297         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
2298         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
2299 };
2300
2301 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
2302         {
2303                 .pa_start       = 0x48350000,
2304                 .pa_end         = 0x483500ff,
2305                 .flags          = ADDR_TYPE_RT
2306         },
2307 };
2308
2309 /* l4_per -> i2c4 */
2310 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2311         .master         = &omap44xx_l4_per_hwmod,
2312         .slave          = &omap44xx_i2c4_hwmod,
2313         .clk            = "l4_div_ck",
2314         .addr           = omap44xx_i2c4_addrs,
2315         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c4_addrs),
2316         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2317 };
2318
2319 /* i2c4 slave ports */
2320 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
2321         &omap44xx_l4_per__i2c4,
2322 };
2323
2324 static struct omap_hwmod omap44xx_i2c4_hwmod = {
2325         .name           = "i2c4",
2326         .class          = &omap44xx_i2c_hwmod_class,
2327         .flags          = HWMOD_INIT_NO_RESET,
2328         .mpu_irqs       = omap44xx_i2c4_irqs,
2329         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c4_irqs),
2330         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
2331         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
2332         .main_clk       = "i2c4_fck",
2333         .prcm = {
2334                 .omap4 = {
2335                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
2336                 },
2337         },
2338         .slaves         = omap44xx_i2c4_slaves,
2339         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c4_slaves),
2340         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2341 };
2342
2343 /*
2344  * 'ipu' class
2345  * imaging processor unit
2346  */
2347
2348 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2349         .name   = "ipu",
2350 };
2351
2352 /* ipu */
2353 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2354         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
2355 };
2356
2357 static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
2358         { .name = "cpu0", .rst_shift = 0 },
2359 };
2360
2361 static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
2362         { .name = "cpu1", .rst_shift = 1 },
2363 };
2364
2365 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2366         { .name = "mmu_cache", .rst_shift = 2 },
2367 };
2368
2369 /* ipu master ports */
2370 static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
2371         &omap44xx_ipu__l3_main_2,
2372 };
2373
2374 /* l3_main_2 -> ipu */
2375 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2376         .master         = &omap44xx_l3_main_2_hwmod,
2377         .slave          = &omap44xx_ipu_hwmod,
2378         .clk            = "l3_div_ck",
2379         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2380 };
2381
2382 /* ipu slave ports */
2383 static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2384         &omap44xx_l3_main_2__ipu,
2385 };
2386
2387 /* Pseudo hwmod for reset control purpose only */
2388 static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2389         .name           = "ipu_c0",
2390         .class          = &omap44xx_ipu_hwmod_class,
2391         .flags          = HWMOD_INIT_NO_RESET,
2392         .rst_lines      = omap44xx_ipu_c0_resets,
2393         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c0_resets),
2394         .prcm           = {
2395                 .omap4 = {
2396                         .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2397                 },
2398         },
2399         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2400 };
2401
2402 /* Pseudo hwmod for reset control purpose only */
2403 static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2404         .name           = "ipu_c1",
2405         .class          = &omap44xx_ipu_hwmod_class,
2406         .flags          = HWMOD_INIT_NO_RESET,
2407         .rst_lines      = omap44xx_ipu_c1_resets,
2408         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c1_resets),
2409         .prcm           = {
2410                 .omap4 = {
2411                         .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2412                 },
2413         },
2414         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2415 };
2416
2417 static struct omap_hwmod omap44xx_ipu_hwmod = {
2418         .name           = "ipu",
2419         .class          = &omap44xx_ipu_hwmod_class,
2420         .mpu_irqs       = omap44xx_ipu_irqs,
2421         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_ipu_irqs),
2422         .rst_lines      = omap44xx_ipu_resets,
2423         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
2424         .main_clk       = "ipu_fck",
2425         .prcm           = {
2426                 .omap4 = {
2427                         .clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
2428                         .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2429                 },
2430         },
2431         .slaves         = omap44xx_ipu_slaves,
2432         .slaves_cnt     = ARRAY_SIZE(omap44xx_ipu_slaves),
2433         .masters        = omap44xx_ipu_masters,
2434         .masters_cnt    = ARRAY_SIZE(omap44xx_ipu_masters),
2435         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2436 };
2437
2438 /*
2439  * 'iss' class
2440  * external images sensor pixel data processor
2441  */
2442
2443 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2444         .rev_offs       = 0x0000,
2445         .sysc_offs      = 0x0010,
2446         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
2447                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2448         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2449                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2450                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2451         .sysc_fields    = &omap_hwmod_sysc_type2,
2452 };
2453
2454 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2455         .name   = "iss",
2456         .sysc   = &omap44xx_iss_sysc,
2457 };
2458
2459 /* iss */
2460 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2461         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
2462 };
2463
2464 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2465         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
2466         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2467         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2468         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
2469 };
2470
2471 /* iss master ports */
2472 static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
2473         &omap44xx_iss__l3_main_2,
2474 };
2475
2476 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2477         {
2478                 .pa_start       = 0x52000000,
2479                 .pa_end         = 0x520000ff,
2480                 .flags          = ADDR_TYPE_RT
2481         },
2482 };
2483
2484 /* l3_main_2 -> iss */
2485 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2486         .master         = &omap44xx_l3_main_2_hwmod,
2487         .slave          = &omap44xx_iss_hwmod,
2488         .clk            = "l3_div_ck",
2489         .addr           = omap44xx_iss_addrs,
2490         .addr_cnt       = ARRAY_SIZE(omap44xx_iss_addrs),
2491         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2492 };
2493
2494 /* iss slave ports */
2495 static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
2496         &omap44xx_l3_main_2__iss,
2497 };
2498
2499 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2500         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2501 };
2502
2503 static struct omap_hwmod omap44xx_iss_hwmod = {
2504         .name           = "iss",
2505         .class          = &omap44xx_iss_hwmod_class,
2506         .mpu_irqs       = omap44xx_iss_irqs,
2507         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_iss_irqs),
2508         .sdma_reqs      = omap44xx_iss_sdma_reqs,
2509         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_iss_sdma_reqs),
2510         .main_clk       = "iss_fck",
2511         .prcm           = {
2512                 .omap4 = {
2513                         .clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
2514                 },
2515         },
2516         .opt_clks       = iss_opt_clks,
2517         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
2518         .slaves         = omap44xx_iss_slaves,
2519         .slaves_cnt     = ARRAY_SIZE(omap44xx_iss_slaves),
2520         .masters        = omap44xx_iss_masters,
2521         .masters_cnt    = ARRAY_SIZE(omap44xx_iss_masters),
2522         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2523 };
2524
2525 /*
2526  * 'iva' class
2527  * multi-standard video encoder/decoder hardware accelerator
2528  */
2529
2530 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
2531         .name   = "iva",
2532 };
2533
2534 /* iva */
2535 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2536         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
2537         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
2538         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
2539 };
2540
2541 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2542         { .name = "logic", .rst_shift = 2 },
2543 };
2544
2545 static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
2546         { .name = "seq0", .rst_shift = 0 },
2547 };
2548
2549 static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
2550         { .name = "seq1", .rst_shift = 1 },
2551 };
2552
2553 /* iva master ports */
2554 static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
2555         &omap44xx_iva__l3_main_2,
2556         &omap44xx_iva__l3_instr,
2557 };
2558
2559 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2560         {
2561                 .pa_start       = 0x5a000000,
2562                 .pa_end         = 0x5a07ffff,
2563                 .flags          = ADDR_TYPE_RT
2564         },
2565 };
2566
2567 /* l3_main_2 -> iva */
2568 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2569         .master         = &omap44xx_l3_main_2_hwmod,
2570         .slave          = &omap44xx_iva_hwmod,
2571         .clk            = "l3_div_ck",
2572         .addr           = omap44xx_iva_addrs,
2573         .addr_cnt       = ARRAY_SIZE(omap44xx_iva_addrs),
2574         .user           = OCP_USER_MPU,
2575 };
2576
2577 /* iva slave ports */
2578 static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2579         &omap44xx_dsp__iva,
2580         &omap44xx_l3_main_2__iva,
2581 };
2582
2583 /* Pseudo hwmod for reset control purpose only */
2584 static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2585         .name           = "iva_seq0",
2586         .class          = &omap44xx_iva_hwmod_class,
2587         .flags          = HWMOD_INIT_NO_RESET,
2588         .rst_lines      = omap44xx_iva_seq0_resets,
2589         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2590         .prcm = {
2591                 .omap4 = {
2592                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2593                 },
2594         },
2595         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2596 };
2597
2598 /* Pseudo hwmod for reset control purpose only */
2599 static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2600         .name           = "iva_seq1",
2601         .class          = &omap44xx_iva_hwmod_class,
2602         .flags          = HWMOD_INIT_NO_RESET,
2603         .rst_lines      = omap44xx_iva_seq1_resets,
2604         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2605         .prcm = {
2606                 .omap4 = {
2607                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2608                 },
2609         },
2610         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2611 };
2612
2613 static struct omap_hwmod omap44xx_iva_hwmod = {
2614         .name           = "iva",
2615         .class          = &omap44xx_iva_hwmod_class,
2616         .mpu_irqs       = omap44xx_iva_irqs,
2617         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_iva_irqs),
2618         .rst_lines      = omap44xx_iva_resets,
2619         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
2620         .main_clk       = "iva_fck",
2621         .prcm = {
2622                 .omap4 = {
2623                         .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
2624                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2625                 },
2626         },
2627         .slaves         = omap44xx_iva_slaves,
2628         .slaves_cnt     = ARRAY_SIZE(omap44xx_iva_slaves),
2629         .masters        = omap44xx_iva_masters,
2630         .masters_cnt    = ARRAY_SIZE(omap44xx_iva_masters),
2631         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2632 };
2633
2634 /*
2635  * 'kbd' class
2636  * keyboard controller
2637  */
2638
2639 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
2640         .rev_offs       = 0x0000,
2641         .sysc_offs      = 0x0010,
2642         .syss_offs      = 0x0014,
2643         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2644                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2645                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2646                            SYSS_HAS_RESET_STATUS),
2647         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2648         .sysc_fields    = &omap_hwmod_sysc_type1,
2649 };
2650
2651 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2652         .name   = "kbd",
2653         .sysc   = &omap44xx_kbd_sysc,
2654 };
2655
2656 /* kbd */
2657 static struct omap_hwmod omap44xx_kbd_hwmod;
2658 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2659         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
2660 };
2661
2662 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2663         {
2664                 .pa_start       = 0x4a31c000,
2665                 .pa_end         = 0x4a31c07f,
2666                 .flags          = ADDR_TYPE_RT
2667         },
2668 };
2669
2670 /* l4_wkup -> kbd */
2671 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2672         .master         = &omap44xx_l4_wkup_hwmod,
2673         .slave          = &omap44xx_kbd_hwmod,
2674         .clk            = "l4_wkup_clk_mux_ck",
2675         .addr           = omap44xx_kbd_addrs,
2676         .addr_cnt       = ARRAY_SIZE(omap44xx_kbd_addrs),
2677         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2678 };
2679
2680 /* kbd slave ports */
2681 static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2682         &omap44xx_l4_wkup__kbd,
2683 };
2684
2685 static struct omap_hwmod omap44xx_kbd_hwmod = {
2686         .name           = "kbd",
2687         .class          = &omap44xx_kbd_hwmod_class,
2688         .mpu_irqs       = omap44xx_kbd_irqs,
2689         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_kbd_irqs),
2690         .main_clk       = "kbd_fck",
2691         .prcm           = {
2692                 .omap4 = {
2693                         .clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
2694                 },
2695         },
2696         .slaves         = omap44xx_kbd_slaves,
2697         .slaves_cnt     = ARRAY_SIZE(omap44xx_kbd_slaves),
2698         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2699 };
2700
2701 /*
2702  * 'mailbox' class
2703  * mailbox module allowing communication between the on-chip processors using a
2704  * queued mailbox-interrupt mechanism.
2705  */
2706
2707 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
2708         .rev_offs       = 0x0000,
2709         .sysc_offs      = 0x0010,
2710         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2711                            SYSC_HAS_SOFTRESET),
2712         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2713         .sysc_fields    = &omap_hwmod_sysc_type2,
2714 };
2715
2716 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2717         .name   = "mailbox",
2718         .sysc   = &omap44xx_mailbox_sysc,
2719 };
2720
2721 /* mailbox */
2722 static struct omap_hwmod omap44xx_mailbox_hwmod;
2723 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2724         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
2725 };
2726
2727 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2728         {
2729                 .pa_start       = 0x4a0f4000,
2730                 .pa_end         = 0x4a0f41ff,
2731                 .flags          = ADDR_TYPE_RT
2732         },
2733 };
2734
2735 /* l4_cfg -> mailbox */
2736 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2737         .master         = &omap44xx_l4_cfg_hwmod,
2738         .slave          = &omap44xx_mailbox_hwmod,
2739         .clk            = "l4_div_ck",
2740         .addr           = omap44xx_mailbox_addrs,
2741         .addr_cnt       = ARRAY_SIZE(omap44xx_mailbox_addrs),
2742         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2743 };
2744
2745 /* mailbox slave ports */
2746 static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2747         &omap44xx_l4_cfg__mailbox,
2748 };
2749
2750 static struct omap_hwmod omap44xx_mailbox_hwmod = {
2751         .name           = "mailbox",
2752         .class          = &omap44xx_mailbox_hwmod_class,
2753         .mpu_irqs       = omap44xx_mailbox_irqs,
2754         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mailbox_irqs),
2755         .prcm           = {
2756                 .omap4 = {
2757                         .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL,
2758                 },
2759         },
2760         .slaves         = omap44xx_mailbox_slaves,
2761         .slaves_cnt     = ARRAY_SIZE(omap44xx_mailbox_slaves),
2762         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2763 };
2764
2765 /*
2766  * 'mcbsp' class
2767  * multi channel buffered serial port controller
2768  */
2769
2770 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
2771         .sysc_offs      = 0x008c,
2772         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2773                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2774         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2775         .sysc_fields    = &omap_hwmod_sysc_type1,
2776 };
2777
2778 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2779         .name   = "mcbsp",
2780         .sysc   = &omap44xx_mcbsp_sysc,
2781         .rev    = MCBSP_CONFIG_TYPE4,
2782 };
2783
2784 /* mcbsp1 */
2785 static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2786 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2787         { .irq = 17 + OMAP44XX_IRQ_GIC_START },
2788 };
2789
2790 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2791         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
2792         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
2793 };
2794
2795 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2796         {
2797                 .name           = "mpu",
2798                 .pa_start       = 0x40122000,
2799                 .pa_end         = 0x401220ff,
2800                 .flags          = ADDR_TYPE_RT
2801         },
2802 };
2803
2804 /* l4_abe -> mcbsp1 */
2805 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2806         .master         = &omap44xx_l4_abe_hwmod,
2807         .slave          = &omap44xx_mcbsp1_hwmod,
2808         .clk            = "ocp_abe_iclk",
2809         .addr           = omap44xx_mcbsp1_addrs,
2810         .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp1_addrs),
2811         .user           = OCP_USER_MPU,
2812 };
2813
2814 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2815         {
2816                 .name           = "dma",
2817                 .pa_start       = 0x49022000,
2818                 .pa_end         = 0x490220ff,
2819                 .flags          = ADDR_TYPE_RT
2820         },
2821 };
2822
2823 /* l4_abe -> mcbsp1 (dma) */
2824 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
2825         .master         = &omap44xx_l4_abe_hwmod,
2826         .slave          = &omap44xx_mcbsp1_hwmod,
2827         .clk            = "ocp_abe_iclk",
2828         .addr           = omap44xx_mcbsp1_dma_addrs,
2829         .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp1_dma_addrs),
2830         .user           = OCP_USER_SDMA,
2831 };
2832
2833 /* mcbsp1 slave ports */
2834 static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
2835         &omap44xx_l4_abe__mcbsp1,
2836         &omap44xx_l4_abe__mcbsp1_dma,
2837 };
2838
2839 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
2840         .name           = "mcbsp1",
2841         .class          = &omap44xx_mcbsp_hwmod_class,
2842         .mpu_irqs       = omap44xx_mcbsp1_irqs,
2843         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcbsp1_irqs),
2844         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
2845         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcbsp1_sdma_reqs),
2846         .main_clk       = "mcbsp1_fck",
2847         .prcm = {
2848                 .omap4 = {
2849                         .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
2850                 },
2851         },
2852         .slaves         = omap44xx_mcbsp1_slaves,
2853         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
2854         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2855 };
2856
2857 /* mcbsp2 */
2858 static struct omap_hwmod omap44xx_mcbsp2_hwmod;
2859 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
2860         { .irq = 22 + OMAP44XX_IRQ_GIC_START },
2861 };
2862
2863 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
2864         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
2865         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
2866 };
2867
2868 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
2869         {
2870                 .name           = "mpu",
2871                 .pa_start       = 0x40124000,
2872                 .pa_end         = 0x401240ff,
2873                 .flags          = ADDR_TYPE_RT
2874         },
2875 };
2876
2877 /* l4_abe -> mcbsp2 */
2878 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
2879         .master         = &omap44xx_l4_abe_hwmod,
2880         .slave          = &omap44xx_mcbsp2_hwmod,
2881         .clk            = "ocp_abe_iclk",
2882         .addr           = omap44xx_mcbsp2_addrs,
2883         .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp2_addrs),
2884         .user           = OCP_USER_MPU,
2885 };
2886
2887 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
2888         {
2889                 .name           = "dma",
2890                 .pa_start       = 0x49024000,
2891                 .pa_end         = 0x490240ff,
2892                 .flags          = ADDR_TYPE_RT
2893         },
2894 };
2895
2896 /* l4_abe -> mcbsp2 (dma) */
2897 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
2898         .master         = &omap44xx_l4_abe_hwmod,
2899         .slave          = &omap44xx_mcbsp2_hwmod,
2900         .clk            = "ocp_abe_iclk",
2901         .addr           = omap44xx_mcbsp2_dma_addrs,
2902         .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp2_dma_addrs),
2903         .user           = OCP_USER_SDMA,
2904 };
2905
2906 /* mcbsp2 slave ports */
2907 static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
2908         &omap44xx_l4_abe__mcbsp2,
2909         &omap44xx_l4_abe__mcbsp2_dma,
2910 };
2911
2912 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2913         .name           = "mcbsp2",
2914         .class          = &omap44xx_mcbsp_hwmod_class,
2915         .mpu_irqs       = omap44xx_mcbsp2_irqs,
2916         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcbsp2_irqs),
2917         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
2918         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcbsp2_sdma_reqs),
2919         .main_clk       = "mcbsp2_fck",
2920         .prcm = {
2921                 .omap4 = {
2922                         .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
2923                 },
2924         },
2925         .slaves         = omap44xx_mcbsp2_slaves,
2926         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
2927         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2928 };
2929
2930 /* mcbsp3 */
2931 static struct omap_hwmod omap44xx_mcbsp3_hwmod;
2932 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2933         { .irq = 23 + OMAP44XX_IRQ_GIC_START },
2934 };
2935
2936 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2937         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2938         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2939 };
2940
2941 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
2942         {
2943                 .name           = "mpu",
2944                 .pa_start       = 0x40126000,
2945                 .pa_end         = 0x401260ff,
2946                 .flags          = ADDR_TYPE_RT
2947         },
2948 };
2949
2950 /* l4_abe -> mcbsp3 */
2951 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
2952         .master         = &omap44xx_l4_abe_hwmod,
2953         .slave          = &omap44xx_mcbsp3_hwmod,
2954         .clk            = "ocp_abe_iclk",
2955         .addr           = omap44xx_mcbsp3_addrs,
2956         .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp3_addrs),
2957         .user           = OCP_USER_MPU,
2958 };
2959
2960 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
2961         {
2962                 .name           = "dma",
2963                 .pa_start       = 0x49026000,
2964                 .pa_end         = 0x490260ff,
2965                 .flags          = ADDR_TYPE_RT
2966         },
2967 };
2968
2969 /* l4_abe -> mcbsp3 (dma) */
2970 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
2971         .master         = &omap44xx_l4_abe_hwmod,
2972         .slave          = &omap44xx_mcbsp3_hwmod,
2973         .clk            = "ocp_abe_iclk",
2974         .addr           = omap44xx_mcbsp3_dma_addrs,
2975         .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp3_dma_addrs),
2976         .user           = OCP_USER_SDMA,
2977 };
2978
2979 /* mcbsp3 slave ports */
2980 static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
2981         &omap44xx_l4_abe__mcbsp3,
2982         &omap44xx_l4_abe__mcbsp3_dma,
2983 };
2984
2985 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2986         .name           = "mcbsp3",
2987         .class          = &omap44xx_mcbsp_hwmod_class,
2988         .mpu_irqs       = omap44xx_mcbsp3_irqs,
2989         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcbsp3_irqs),
2990         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
2991         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcbsp3_sdma_reqs),
2992         .main_clk       = "mcbsp3_fck",
2993         .prcm = {
2994                 .omap4 = {
2995                         .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
2996                 },
2997         },
2998         .slaves         = omap44xx_mcbsp3_slaves,
2999         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
3000         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3001 };
3002
3003 /* mcbsp4 */
3004 static struct omap_hwmod omap44xx_mcbsp4_hwmod;
3005 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
3006         { .irq = 16 + OMAP44XX_IRQ_GIC_START },
3007 };
3008
3009 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
3010         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
3011         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
3012 };
3013
3014 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
3015         {
3016                 .pa_start       = 0x48096000,
3017                 .pa_end         = 0x480960ff,
3018                 .flags          = ADDR_TYPE_RT
3019         },
3020 };
3021
3022 /* l4_per -> mcbsp4 */
3023 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
3024         .master         = &omap44xx_l4_per_hwmod,
3025         .slave          = &omap44xx_mcbsp4_hwmod,
3026         .clk            = "l4_div_ck",
3027         .addr           = omap44xx_mcbsp4_addrs,
3028         .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp4_addrs),
3029         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3030 };
3031
3032 /* mcbsp4 slave ports */
3033 static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
3034         &omap44xx_l4_per__mcbsp4,
3035 };
3036
3037 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
3038         .name           = "mcbsp4",
3039         .class          = &omap44xx_mcbsp_hwmod_class,
3040         .mpu_irqs       = omap44xx_mcbsp4_irqs,
3041         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcbsp4_irqs),
3042         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
3043         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcbsp4_sdma_reqs),
3044         .main_clk       = "mcbsp4_fck",
3045         .prcm = {
3046                 .omap4 = {
3047                         .clkctrl_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
3048                 },
3049         },
3050         .slaves         = omap44xx_mcbsp4_slaves,
3051         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
3052         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3053 };
3054
3055 /*
3056  * 'mcpdm' class
3057  * multi channel pdm controller (proprietary interface with phoenix power
3058  * ic)
3059  */
3060
3061 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
3062         .rev_offs       = 0x0000,
3063         .sysc_offs      = 0x0010,
3064         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3065                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3066         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3067                            SIDLE_SMART_WKUP),
3068         .sysc_fields    = &omap_hwmod_sysc_type2,
3069 };
3070
3071 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
3072         .name   = "mcpdm",
3073         .sysc   = &omap44xx_mcpdm_sysc,
3074 };
3075
3076 /* mcpdm */
3077 static struct omap_hwmod omap44xx_mcpdm_hwmod;
3078 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
3079         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
3080 };
3081
3082 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
3083         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
3084         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
3085 };
3086
3087 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3088         {
3089                 .pa_start       = 0x40132000,
3090                 .pa_end         = 0x4013207f,
3091                 .flags          = ADDR_TYPE_RT
3092         },
3093 };
3094
3095 /* l4_abe -> mcpdm */
3096 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3097         .master         = &omap44xx_l4_abe_hwmod,
3098         .slave          = &omap44xx_mcpdm_hwmod,
3099         .clk            = "ocp_abe_iclk",
3100         .addr           = omap44xx_mcpdm_addrs,
3101         .addr_cnt       = ARRAY_SIZE(omap44xx_mcpdm_addrs),
3102         .user           = OCP_USER_MPU,
3103 };
3104
3105 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3106         {
3107                 .pa_start       = 0x49032000,
3108                 .pa_end         = 0x4903207f,
3109                 .flags          = ADDR_TYPE_RT
3110         },
3111 };
3112
3113 /* l4_abe -> mcpdm (dma) */
3114 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3115         .master         = &omap44xx_l4_abe_hwmod,
3116         .slave          = &omap44xx_mcpdm_hwmod,
3117         .clk            = "ocp_abe_iclk",
3118         .addr           = omap44xx_mcpdm_dma_addrs,
3119         .addr_cnt       = ARRAY_SIZE(omap44xx_mcpdm_dma_addrs),
3120         .user           = OCP_USER_SDMA,
3121 };
3122
3123 /* mcpdm slave ports */
3124 static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
3125         &omap44xx_l4_abe__mcpdm,
3126         &omap44xx_l4_abe__mcpdm_dma,
3127 };
3128
3129 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3130         .name           = "mcpdm",
3131         .class          = &omap44xx_mcpdm_hwmod_class,
3132         .mpu_irqs       = omap44xx_mcpdm_irqs,
3133         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcpdm_irqs),
3134         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
3135         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcpdm_sdma_reqs),
3136         .main_clk       = "mcpdm_fck",
3137         .prcm           = {
3138                 .omap4 = {
3139                         .clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
3140                 },
3141         },
3142         .slaves         = omap44xx_mcpdm_slaves,
3143         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcpdm_slaves),
3144         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3145 };
3146
3147 /*
3148  * 'mcspi' class
3149  * multichannel serial port interface (mcspi) / master/slave synchronous serial
3150  * bus
3151  */
3152
3153 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
3154         .rev_offs       = 0x0000,
3155         .sysc_offs      = 0x0010,
3156         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3157                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3158         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3159                            SIDLE_SMART_WKUP),
3160         .sysc_fields    = &omap_hwmod_sysc_type2,
3161 };
3162
3163 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
3164         .name   = "mcspi",
3165         .sysc   = &omap44xx_mcspi_sysc,
3166         .rev    = OMAP4_MCSPI_REV,
3167 };
3168
3169 /* mcspi1 */
3170 static struct omap_hwmod omap44xx_mcspi1_hwmod;
3171 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
3172         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
3173 };
3174
3175 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
3176         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
3177         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
3178         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
3179         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
3180         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
3181         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
3182         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
3183         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
3184 };
3185
3186 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
3187         {
3188                 .pa_start       = 0x48098000,
3189                 .pa_end         = 0x480981ff,
3190                 .flags          = ADDR_TYPE_RT
3191         },
3192 };
3193
3194 /* l4_per -> mcspi1 */
3195 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3196         .master         = &omap44xx_l4_per_hwmod,
3197         .slave          = &omap44xx_mcspi1_hwmod,
3198         .clk            = "l4_div_ck",
3199         .addr           = omap44xx_mcspi1_addrs,
3200         .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi1_addrs),
3201         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3202 };
3203
3204 /* mcspi1 slave ports */
3205 static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
3206         &omap44xx_l4_per__mcspi1,
3207 };
3208
3209 /* mcspi1 dev_attr */
3210 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
3211         .num_chipselect = 4,
3212 };
3213
3214 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3215         .name           = "mcspi1",
3216         .class          = &omap44xx_mcspi_hwmod_class,
3217         .mpu_irqs       = omap44xx_mcspi1_irqs,
3218         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi1_irqs),
3219         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
3220         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs),
3221         .main_clk       = "mcspi1_fck",
3222         .prcm = {
3223                 .omap4 = {
3224                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
3225                 },
3226         },
3227         .dev_attr       = &mcspi1_dev_attr,
3228         .slaves         = omap44xx_mcspi1_slaves,
3229         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi1_slaves),
3230         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3231 };
3232
3233 /* mcspi2 */
3234 static struct omap_hwmod omap44xx_mcspi2_hwmod;
3235 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
3236         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
3237 };
3238
3239 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
3240         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
3241         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
3242         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
3243         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
3244 };
3245
3246 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
3247         {
3248                 .pa_start       = 0x4809a000,
3249                 .pa_end         = 0x4809a1ff,
3250                 .flags          = ADDR_TYPE_RT
3251         },
3252 };
3253
3254 /* l4_per -> mcspi2 */
3255 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3256         .master         = &omap44xx_l4_per_hwmod,
3257         .slave          = &omap44xx_mcspi2_hwmod,
3258         .clk            = "l4_div_ck",
3259         .addr           = omap44xx_mcspi2_addrs,
3260         .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi2_addrs),
3261         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3262 };
3263
3264 /* mcspi2 slave ports */
3265 static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
3266         &omap44xx_l4_per__mcspi2,
3267 };
3268
3269 /* mcspi2 dev_attr */
3270 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
3271         .num_chipselect = 2,
3272 };
3273
3274 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3275         .name           = "mcspi2",
3276         .class          = &omap44xx_mcspi_hwmod_class,
3277         .mpu_irqs       = omap44xx_mcspi2_irqs,
3278         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi2_irqs),
3279         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
3280         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs),
3281         .main_clk       = "mcspi2_fck",
3282         .prcm = {
3283                 .omap4 = {
3284                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
3285                 },
3286         },
3287         .dev_attr       = &mcspi2_dev_attr,
3288         .slaves         = omap44xx_mcspi2_slaves,
3289         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi2_slaves),
3290         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3291 };
3292
3293 /* mcspi3 */
3294 static struct omap_hwmod omap44xx_mcspi3_hwmod;
3295 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
3296         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
3297 };
3298
3299 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
3300         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
3301         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
3302         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
3303         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
3304 };
3305
3306 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
3307         {
3308                 .pa_start       = 0x480b8000,
3309                 .pa_end         = 0x480b81ff,
3310                 .flags          = ADDR_TYPE_RT
3311         },
3312 };
3313
3314 /* l4_per -> mcspi3 */
3315 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3316         .master         = &omap44xx_l4_per_hwmod,
3317         .slave          = &omap44xx_mcspi3_hwmod,
3318         .clk            = "l4_div_ck",
3319         .addr           = omap44xx_mcspi3_addrs,
3320         .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi3_addrs),
3321         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3322 };
3323
3324 /* mcspi3 slave ports */
3325 static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
3326         &omap44xx_l4_per__mcspi3,
3327 };
3328
3329 /* mcspi3 dev_attr */
3330 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
3331         .num_chipselect = 2,
3332 };
3333
3334 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3335         .name           = "mcspi3",
3336         .class          = &omap44xx_mcspi_hwmod_class,
3337         .mpu_irqs       = omap44xx_mcspi3_irqs,
3338         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi3_irqs),
3339         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
3340         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs),
3341         .main_clk       = "mcspi3_fck",
3342         .prcm = {
3343                 .omap4 = {
3344                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
3345                 },
3346         },
3347         .dev_attr       = &mcspi3_dev_attr,
3348         .slaves         = omap44xx_mcspi3_slaves,
3349         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi3_slaves),
3350         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3351 };
3352
3353 /* mcspi4 */
3354 static struct omap_hwmod omap44xx_mcspi4_hwmod;
3355 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
3356         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
3357 };
3358
3359 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
3360         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
3361         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
3362 };
3363
3364 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
3365         {
3366                 .pa_start       = 0x480ba000,
3367                 .pa_end         = 0x480ba1ff,
3368                 .flags          = ADDR_TYPE_RT
3369         },
3370 };
3371
3372 /* l4_per -> mcspi4 */
3373 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3374         .master         = &omap44xx_l4_per_hwmod,
3375         .slave          = &omap44xx_mcspi4_hwmod,
3376         .clk            = "l4_div_ck",
3377         .addr           = omap44xx_mcspi4_addrs,
3378         .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi4_addrs),
3379         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3380 };
3381
3382 /* mcspi4 slave ports */
3383 static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
3384         &omap44xx_l4_per__mcspi4,
3385 };
3386
3387 /* mcspi4 dev_attr */
3388 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
3389         .num_chipselect = 1,
3390 };
3391
3392 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3393         .name           = "mcspi4",
3394         .class          = &omap44xx_mcspi_hwmod_class,
3395         .mpu_irqs       = omap44xx_mcspi4_irqs,
3396         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi4_irqs),
3397         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
3398         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs),
3399         .main_clk       = "mcspi4_fck",
3400         .prcm = {
3401                 .omap4 = {
3402                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
3403                 },
3404         },
3405         .dev_attr       = &mcspi4_dev_attr,
3406         .slaves         = omap44xx_mcspi4_slaves,
3407         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi4_slaves),
3408         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3409 };
3410
3411 /*
3412  * 'mmc' class
3413  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
3414  */
3415
3416 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
3417         .rev_offs       = 0x0000,
3418         .sysc_offs      = 0x0010,
3419         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
3420                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
3421                            SYSC_HAS_SOFTRESET),
3422         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3423                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3424                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3425         .sysc_fields    = &omap_hwmod_sysc_type2,
3426 };
3427
3428 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
3429         .name   = "mmc",
3430         .sysc   = &omap44xx_mmc_sysc,
3431 };
3432
3433 /* mmc1 */
3434
3435 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
3436         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
3437 };
3438
3439 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
3440         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
3441         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
3442 };
3443
3444 /* mmc1 master ports */
3445 static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
3446         &omap44xx_mmc1__l3_main_1,
3447 };
3448
3449 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
3450         {
3451                 .pa_start       = 0x4809c000,
3452                 .pa_end         = 0x4809c3ff,
3453                 .flags          = ADDR_TYPE_RT
3454         },
3455 };
3456
3457 /* l4_per -> mmc1 */
3458 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3459         .master         = &omap44xx_l4_per_hwmod,
3460         .slave          = &omap44xx_mmc1_hwmod,
3461         .clk            = "l4_div_ck",
3462         .addr           = omap44xx_mmc1_addrs,
3463         .addr_cnt       = ARRAY_SIZE(omap44xx_mmc1_addrs),
3464         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3465 };
3466
3467 /* mmc1 slave ports */
3468 static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
3469         &omap44xx_l4_per__mmc1,
3470 };
3471
3472 /* mmc1 dev_attr */
3473 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3474         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3475 };
3476
3477 static struct omap_hwmod omap44xx_mmc1_hwmod = {
3478         .name           = "mmc1",
3479         .class          = &omap44xx_mmc_hwmod_class,
3480         .mpu_irqs       = omap44xx_mmc1_irqs,
3481         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc1_irqs),
3482         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
3483         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc1_sdma_reqs),
3484         .main_clk       = "mmc1_fck",
3485         .prcm           = {
3486                 .omap4 = {
3487                         .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
3488                 },
3489         },
3490         .dev_attr       = &mmc1_dev_attr,
3491         .slaves         = omap44xx_mmc1_slaves,
3492         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc1_slaves),
3493         .masters        = omap44xx_mmc1_masters,
3494         .masters_cnt    = ARRAY_SIZE(omap44xx_mmc1_masters),
3495         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3496 };
3497
3498 /* mmc2 */
3499 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
3500         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
3501 };
3502
3503 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
3504         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
3505         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
3506 };
3507
3508 /* mmc2 master ports */
3509 static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
3510         &omap44xx_mmc2__l3_main_1,
3511 };
3512
3513 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
3514         {
3515                 .pa_start       = 0x480b4000,
3516                 .pa_end         = 0x480b43ff,
3517                 .flags          = ADDR_TYPE_RT
3518         },
3519 };
3520
3521 /* l4_per -> mmc2 */
3522 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3523         .master         = &omap44xx_l4_per_hwmod,
3524         .slave          = &omap44xx_mmc2_hwmod,
3525         .clk            = "l4_div_ck",
3526         .addr           = omap44xx_mmc2_addrs,
3527         .addr_cnt       = ARRAY_SIZE(omap44xx_mmc2_addrs),
3528         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3529 };
3530
3531 /* mmc2 slave ports */
3532 static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
3533         &omap44xx_l4_per__mmc2,
3534 };
3535
3536 static struct omap_hwmod omap44xx_mmc2_hwmod = {
3537         .name           = "mmc2",
3538         .class          = &omap44xx_mmc_hwmod_class,
3539         .mpu_irqs       = omap44xx_mmc2_irqs,
3540         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc2_irqs),
3541         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
3542         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc2_sdma_reqs),
3543         .main_clk       = "mmc2_fck",
3544         .prcm           = {
3545                 .omap4 = {
3546                         .clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
3547                 },
3548         },
3549         .slaves         = omap44xx_mmc2_slaves,
3550         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc2_slaves),
3551         .masters        = omap44xx_mmc2_masters,
3552         .masters_cnt    = ARRAY_SIZE(omap44xx_mmc2_masters),
3553         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3554 };
3555
3556 /* mmc3 */
3557 static struct omap_hwmod omap44xx_mmc3_hwmod;
3558 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
3559         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
3560 };
3561
3562 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
3563         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
3564         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
3565 };
3566
3567 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
3568         {
3569                 .pa_start       = 0x480ad000,
3570                 .pa_end         = 0x480ad3ff,
3571                 .flags          = ADDR_TYPE_RT
3572         },
3573 };
3574
3575 /* l4_per -> mmc3 */
3576 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3577         .master         = &omap44xx_l4_per_hwmod,
3578         .slave          = &omap44xx_mmc3_hwmod,
3579         .clk            = "l4_div_ck",
3580         .addr           = omap44xx_mmc3_addrs,
3581         .addr_cnt       = ARRAY_SIZE(omap44xx_mmc3_addrs),
3582         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3583 };
3584
3585 /* mmc3 slave ports */
3586 static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
3587         &omap44xx_l4_per__mmc3,
3588 };
3589
3590 static struct omap_hwmod omap44xx_mmc3_hwmod = {
3591         .name           = "mmc3",
3592         .class          = &omap44xx_mmc_hwmod_class,
3593         .mpu_irqs       = omap44xx_mmc3_irqs,
3594         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc3_irqs),
3595         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
3596         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc3_sdma_reqs),
3597         .main_clk       = "mmc3_fck",
3598         .prcm           = {
3599                 .omap4 = {
3600                         .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
3601                 },
3602         },
3603         .slaves         = omap44xx_mmc3_slaves,
3604         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc3_slaves),
3605         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3606 };
3607
3608 /* mmc4 */
3609 static struct omap_hwmod omap44xx_mmc4_hwmod;
3610 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
3611         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
3612 };
3613
3614 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
3615         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
3616         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
3617 };
3618
3619 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
3620         {
3621                 .pa_start       = 0x480d1000,
3622                 .pa_end         = 0x480d13ff,
3623                 .flags          = ADDR_TYPE_RT
3624         },
3625 };
3626
3627 /* l4_per -> mmc4 */
3628 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3629         .master         = &omap44xx_l4_per_hwmod,
3630         .slave          = &omap44xx_mmc4_hwmod,
3631         .clk            = "l4_div_ck",
3632         .addr           = omap44xx_mmc4_addrs,
3633         .addr_cnt       = ARRAY_SIZE(omap44xx_mmc4_addrs),
3634         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3635 };
3636
3637 /* mmc4 slave ports */
3638 static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
3639         &omap44xx_l4_per__mmc4,
3640 };
3641
3642 static struct omap_hwmod omap44xx_mmc4_hwmod = {
3643         .name           = "mmc4",
3644         .class          = &omap44xx_mmc_hwmod_class,
3645         .mpu_irqs       = omap44xx_mmc4_irqs,
3646         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc4_irqs),
3647         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
3648         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc4_sdma_reqs),
3649         .main_clk       = "mmc4_fck",
3650         .prcm           = {
3651                 .omap4 = {
3652                         .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
3653                 },
3654         },
3655         .slaves         = omap44xx_mmc4_slaves,
3656         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc4_slaves),
3657         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3658 };
3659
3660 /* mmc5 */
3661 static struct omap_hwmod omap44xx_mmc5_hwmod;
3662 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
3663         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
3664 };
3665
3666 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
3667         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
3668         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
3669 };
3670
3671 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
3672         {
3673                 .pa_start       = 0x480d5000,
3674                 .pa_end         = 0x480d53ff,
3675                 .flags          = ADDR_TYPE_RT
3676         },
3677 };
3678
3679 /* l4_per -> mmc5 */
3680 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3681         .master         = &omap44xx_l4_per_hwmod,
3682         .slave          = &omap44xx_mmc5_hwmod,
3683         .clk            = "l4_div_ck",
3684         .addr           = omap44xx_mmc5_addrs,
3685         .addr_cnt       = ARRAY_SIZE(omap44xx_mmc5_addrs),
3686         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3687 };
3688
3689 /* mmc5 slave ports */
3690 static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
3691         &omap44xx_l4_per__mmc5,
3692 };
3693
3694 static struct omap_hwmod omap44xx_mmc5_hwmod = {
3695         .name           = "mmc5",
3696         .class          = &omap44xx_mmc_hwmod_class,
3697         .mpu_irqs       = omap44xx_mmc5_irqs,
3698         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc5_irqs),
3699         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
3700         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc5_sdma_reqs),
3701         .main_clk       = "mmc5_fck",
3702         .prcm           = {
3703                 .omap4 = {
3704                         .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
3705                 },
3706         },
3707         .slaves         = omap44xx_mmc5_slaves,
3708         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc5_slaves),
3709         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3710 };
3711
3712 /*
3713  * 'mpu' class
3714  * mpu sub-system
3715  */
3716
3717 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
3718         .name   = "mpu",
3719 };
3720
3721 /* mpu */
3722 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
3723         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
3724         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
3725         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
3726 };
3727
3728 /* mpu master ports */
3729 static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
3730         &omap44xx_mpu__l3_main_1,
3731         &omap44xx_mpu__l4_abe,
3732         &omap44xx_mpu__dmm,
3733 };
3734
3735 static struct omap_hwmod omap44xx_mpu_hwmod = {
3736         .name           = "mpu",
3737         .class          = &omap44xx_mpu_hwmod_class,
3738         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
3739         .mpu_irqs       = omap44xx_mpu_irqs,
3740         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mpu_irqs),
3741         .main_clk       = "dpll_mpu_m2_ck",
3742         .prcm = {
3743                 .omap4 = {
3744                         .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
3745                 },
3746         },
3747         .masters        = omap44xx_mpu_masters,
3748         .masters_cnt    = ARRAY_SIZE(omap44xx_mpu_masters),
3749         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3750 };
3751
3752 /*
3753  * 'smartreflex' class
3754  * smartreflex module (monitor silicon performance and outputs a measure of
3755  * performance error)
3756  */
3757
3758 /* The IP is not compliant to type1 / type2 scheme */
3759 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
3760         .sidle_shift    = 24,
3761         .enwkup_shift   = 26,
3762 };
3763
3764 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
3765         .sysc_offs      = 0x0038,
3766         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
3767         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3768                            SIDLE_SMART_WKUP),
3769         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
3770 };
3771
3772 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
3773         .name   = "smartreflex",
3774         .sysc   = &omap44xx_smartreflex_sysc,
3775         .rev    = 2,
3776 };
3777
3778 /* smartreflex_core */
3779 static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
3780 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
3781         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
3782 };
3783
3784 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
3785         {
3786                 .pa_start       = 0x4a0dd000,
3787                 .pa_end         = 0x4a0dd03f,
3788                 .flags          = ADDR_TYPE_RT
3789         },
3790 };
3791
3792 /* l4_cfg -> smartreflex_core */
3793 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
3794         .master         = &omap44xx_l4_cfg_hwmod,
3795         .slave          = &omap44xx_smartreflex_core_hwmod,
3796         .clk            = "l4_div_ck",
3797         .addr           = omap44xx_smartreflex_core_addrs,
3798         .addr_cnt       = ARRAY_SIZE(omap44xx_smartreflex_core_addrs),
3799         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3800 };
3801
3802 /* smartreflex_core slave ports */
3803 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
3804         &omap44xx_l4_cfg__smartreflex_core,
3805 };
3806
3807 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
3808         .name           = "smartreflex_core",
3809         .class          = &omap44xx_smartreflex_hwmod_class,
3810         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
3811         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_smartreflex_core_irqs),
3812         .main_clk       = "smartreflex_core_fck",
3813         .vdd_name       = "core",
3814         .prcm = {
3815                 .omap4 = {
3816                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
3817                 },
3818         },
3819         .slaves         = omap44xx_smartreflex_core_slaves,
3820         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
3821         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3822 };
3823
3824 /* smartreflex_iva */
3825 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
3826 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
3827         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
3828 };
3829
3830 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
3831         {
3832                 .pa_start       = 0x4a0db000,
3833                 .pa_end         = 0x4a0db03f,
3834                 .flags          = ADDR_TYPE_RT
3835         },
3836 };
3837
3838 /* l4_cfg -> smartreflex_iva */
3839 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
3840         .master         = &omap44xx_l4_cfg_hwmod,
3841         .slave          = &omap44xx_smartreflex_iva_hwmod,
3842         .clk            = "l4_div_ck",
3843         .addr           = omap44xx_smartreflex_iva_addrs,
3844         .addr_cnt       = ARRAY_SIZE(omap44xx_smartreflex_iva_addrs),
3845         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3846 };
3847
3848 /* smartreflex_iva slave ports */
3849 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
3850         &omap44xx_l4_cfg__smartreflex_iva,
3851 };
3852
3853 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
3854         .name           = "smartreflex_iva",
3855         .class          = &omap44xx_smartreflex_hwmod_class,
3856         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
3857         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs),
3858         .main_clk       = "smartreflex_iva_fck",
3859         .vdd_name       = "iva",
3860         .prcm = {
3861                 .omap4 = {
3862                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
3863                 },
3864         },
3865         .slaves         = omap44xx_smartreflex_iva_slaves,
3866         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
3867         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3868 };
3869
3870 /* smartreflex_mpu */
3871 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
3872 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
3873         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
3874 };
3875
3876 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
3877         {
3878                 .pa_start       = 0x4a0d9000,
3879                 .pa_end         = 0x4a0d903f,
3880                 .flags          = ADDR_TYPE_RT
3881         },
3882 };
3883
3884 /* l4_cfg -> smartreflex_mpu */
3885 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
3886         .master         = &omap44xx_l4_cfg_hwmod,
3887         .slave          = &omap44xx_smartreflex_mpu_hwmod,
3888         .clk            = "l4_div_ck",
3889         .addr           = omap44xx_smartreflex_mpu_addrs,
3890         .addr_cnt       = ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs),
3891         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3892 };
3893
3894 /* smartreflex_mpu slave ports */
3895 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
3896         &omap44xx_l4_cfg__smartreflex_mpu,
3897 };
3898
3899 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3900         .name           = "smartreflex_mpu",
3901         .class          = &omap44xx_smartreflex_hwmod_class,
3902         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
3903         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs),
3904         .main_clk       = "smartreflex_mpu_fck",
3905         .vdd_name       = "mpu",
3906         .prcm = {
3907                 .omap4 = {
3908                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
3909                 },
3910         },
3911         .slaves         = omap44xx_smartreflex_mpu_slaves,
3912         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
3913         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3914 };
3915
3916 /*
3917  * 'spinlock' class
3918  * spinlock provides hardware assistance for synchronizing the processes
3919  * running on multiple processors
3920  */
3921
3922 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
3923         .rev_offs       = 0x0000,
3924         .sysc_offs      = 0x0010,
3925         .syss_offs      = 0x0014,
3926         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3927                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3928                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3929         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3930                            SIDLE_SMART_WKUP),
3931         .sysc_fields    = &omap_hwmod_sysc_type1,
3932 };
3933
3934 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
3935         .name   = "spinlock",
3936         .sysc   = &omap44xx_spinlock_sysc,
3937 };
3938
3939 /* spinlock */
3940 static struct omap_hwmod omap44xx_spinlock_hwmod;
3941 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
3942         {
3943                 .pa_start       = 0x4a0f6000,
3944                 .pa_end         = 0x4a0f6fff,
3945                 .flags          = ADDR_TYPE_RT
3946         },
3947 };
3948
3949 /* l4_cfg -> spinlock */
3950 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
3951         .master         = &omap44xx_l4_cfg_hwmod,
3952         .slave          = &omap44xx_spinlock_hwmod,
3953         .clk            = "l4_div_ck",
3954         .addr           = omap44xx_spinlock_addrs,
3955         .addr_cnt       = ARRAY_SIZE(omap44xx_spinlock_addrs),
3956         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3957 };
3958
3959 /* spinlock slave ports */
3960 static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
3961         &omap44xx_l4_cfg__spinlock,
3962 };
3963
3964 static struct omap_hwmod omap44xx_spinlock_hwmod = {
3965         .name           = "spinlock",
3966         .class          = &omap44xx_spinlock_hwmod_class,
3967         .prcm = {
3968                 .omap4 = {
3969                         .clkctrl_reg = OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL,
3970                 },
3971         },
3972         .slaves         = omap44xx_spinlock_slaves,
3973         .slaves_cnt     = ARRAY_SIZE(omap44xx_spinlock_slaves),
3974         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3975 };
3976
3977 /*
3978  * 'timer' class
3979  * general purpose timer module with accurate 1ms tick
3980  * This class contains several variants: ['timer_1ms', 'timer']
3981  */
3982
3983 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
3984         .rev_offs       = 0x0000,
3985         .sysc_offs      = 0x0010,
3986         .syss_offs      = 0x0014,
3987         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3988                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
3989                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3990                            SYSS_HAS_RESET_STATUS),
3991         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3992         .sysc_fields    = &omap_hwmod_sysc_type1,
3993 };
3994
3995 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
3996         .name   = "timer",
3997         .sysc   = &omap44xx_timer_1ms_sysc,
3998 };
3999
4000 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
4001         .rev_offs       = 0x0000,
4002         .sysc_offs      = 0x0010,
4003         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
4004                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
4005         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4006                            SIDLE_SMART_WKUP),
4007         .sysc_fields    = &omap_hwmod_sysc_type2,
4008 };
4009
4010 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
4011         .name   = "timer",
4012         .sysc   = &omap44xx_timer_sysc,
4013 };
4014
4015 /* timer1 */
4016 static struct omap_hwmod omap44xx_timer1_hwmod;
4017 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
4018         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
4019 };
4020
4021 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
4022         {
4023                 .pa_start       = 0x4a318000,
4024                 .pa_end         = 0x4a31807f,
4025                 .flags          = ADDR_TYPE_RT
4026         },
4027 };
4028
4029 /* l4_wkup -> timer1 */
4030 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4031         .master         = &omap44xx_l4_wkup_hwmod,
4032         .slave          = &omap44xx_timer1_hwmod,
4033         .clk            = "l4_wkup_clk_mux_ck",
4034         .addr           = omap44xx_timer1_addrs,
4035         .addr_cnt       = ARRAY_SIZE(omap44xx_timer1_addrs),
4036         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4037 };
4038
4039 /* timer1 slave ports */
4040 static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
4041         &omap44xx_l4_wkup__timer1,
4042 };
4043
4044 static struct omap_hwmod omap44xx_timer1_hwmod = {
4045         .name           = "timer1",
4046         .class          = &omap44xx_timer_1ms_hwmod_class,
4047         .mpu_irqs       = omap44xx_timer1_irqs,
4048         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer1_irqs),
4049         .main_clk       = "timer1_fck",
4050         .prcm = {
4051                 .omap4 = {
4052                         .clkctrl_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
4053                 },
4054         },
4055         .slaves         = omap44xx_timer1_slaves,
4056         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer1_slaves),
4057         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4058 };
4059
4060 /* timer2 */
4061 static struct omap_hwmod omap44xx_timer2_hwmod;
4062 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
4063         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
4064 };
4065
4066 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
4067         {
4068                 .pa_start       = 0x48032000,
4069                 .pa_end         = 0x4803207f,
4070                 .flags          = ADDR_TYPE_RT
4071         },
4072 };
4073
4074 /* l4_per -> timer2 */
4075 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4076         .master         = &omap44xx_l4_per_hwmod,
4077         .slave          = &omap44xx_timer2_hwmod,
4078         .clk            = "l4_div_ck",
4079         .addr           = omap44xx_timer2_addrs,
4080         .addr_cnt       = ARRAY_SIZE(omap44xx_timer2_addrs),
4081         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4082 };
4083
4084 /* timer2 slave ports */
4085 static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
4086         &omap44xx_l4_per__timer2,
4087 };
4088
4089 static struct omap_hwmod omap44xx_timer2_hwmod = {
4090         .name           = "timer2",
4091         .class          = &omap44xx_timer_1ms_hwmod_class,
4092         .mpu_irqs       = omap44xx_timer2_irqs,
4093         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer2_irqs),
4094         .main_clk       = "timer2_fck",
4095         .prcm = {
4096                 .omap4 = {
4097                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
4098                 },
4099         },
4100         .slaves         = omap44xx_timer2_slaves,
4101         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer2_slaves),
4102         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4103 };
4104
4105 /* timer3 */
4106 static struct omap_hwmod omap44xx_timer3_hwmod;
4107 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
4108         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
4109 };
4110
4111 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
4112         {
4113                 .pa_start       = 0x48034000,
4114                 .pa_end         = 0x4803407f,
4115                 .flags          = ADDR_TYPE_RT
4116         },
4117 };
4118
4119 /* l4_per -> timer3 */
4120 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4121         .master         = &omap44xx_l4_per_hwmod,
4122         .slave          = &omap44xx_timer3_hwmod,
4123         .clk            = "l4_div_ck",
4124         .addr           = omap44xx_timer3_addrs,
4125         .addr_cnt       = ARRAY_SIZE(omap44xx_timer3_addrs),
4126         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4127 };
4128
4129 /* timer3 slave ports */
4130 static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
4131         &omap44xx_l4_per__timer3,
4132 };
4133
4134 static struct omap_hwmod omap44xx_timer3_hwmod = {
4135         .name           = "timer3",
4136         .class          = &omap44xx_timer_hwmod_class,
4137         .mpu_irqs       = omap44xx_timer3_irqs,
4138         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer3_irqs),
4139         .main_clk       = "timer3_fck",
4140         .prcm = {
4141                 .omap4 = {
4142                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
4143                 },
4144         },
4145         .slaves         = omap44xx_timer3_slaves,
4146         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer3_slaves),
4147         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4148 };
4149
4150 /* timer4 */
4151 static struct omap_hwmod omap44xx_timer4_hwmod;
4152 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
4153         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
4154 };
4155
4156 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
4157         {
4158                 .pa_start       = 0x48036000,
4159                 .pa_end         = 0x4803607f,
4160                 .flags          = ADDR_TYPE_RT
4161         },
4162 };
4163
4164 /* l4_per -> timer4 */
4165 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4166         .master         = &omap44xx_l4_per_hwmod,
4167         .slave          = &omap44xx_timer4_hwmod,
4168         .clk            = "l4_div_ck",
4169         .addr           = omap44xx_timer4_addrs,
4170         .addr_cnt       = ARRAY_SIZE(omap44xx_timer4_addrs),
4171         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4172 };
4173
4174 /* timer4 slave ports */
4175 static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
4176         &omap44xx_l4_per__timer4,
4177 };
4178
4179 static struct omap_hwmod omap44xx_timer4_hwmod = {
4180         .name           = "timer4",
4181         .class          = &omap44xx_timer_hwmod_class,
4182         .mpu_irqs       = omap44xx_timer4_irqs,
4183         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer4_irqs),
4184         .main_clk       = "timer4_fck",
4185         .prcm = {
4186                 .omap4 = {
4187                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
4188                 },
4189         },
4190         .slaves         = omap44xx_timer4_slaves,
4191         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer4_slaves),
4192         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4193 };
4194
4195 /* timer5 */
4196 static struct omap_hwmod omap44xx_timer5_hwmod;
4197 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
4198         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
4199 };
4200
4201 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
4202         {
4203                 .pa_start       = 0x40138000,
4204                 .pa_end         = 0x4013807f,
4205                 .flags          = ADDR_TYPE_RT
4206         },
4207 };
4208
4209 /* l4_abe -> timer5 */
4210 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4211         .master         = &omap44xx_l4_abe_hwmod,
4212         .slave          = &omap44xx_timer5_hwmod,
4213         .clk            = "ocp_abe_iclk",
4214         .addr           = omap44xx_timer5_addrs,
4215         .addr_cnt       = ARRAY_SIZE(omap44xx_timer5_addrs),
4216         .user           = OCP_USER_MPU,
4217 };
4218
4219 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
4220         {
4221                 .pa_start       = 0x49038000,
4222                 .pa_end         = 0x4903807f,
4223                 .flags          = ADDR_TYPE_RT
4224         },
4225 };
4226
4227 /* l4_abe -> timer5 (dma) */
4228 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4229         .master         = &omap44xx_l4_abe_hwmod,
4230         .slave          = &omap44xx_timer5_hwmod,
4231         .clk            = "ocp_abe_iclk",
4232         .addr           = omap44xx_timer5_dma_addrs,
4233         .addr_cnt       = ARRAY_SIZE(omap44xx_timer5_dma_addrs),
4234         .user           = OCP_USER_SDMA,
4235 };
4236
4237 /* timer5 slave ports */
4238 static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
4239         &omap44xx_l4_abe__timer5,
4240         &omap44xx_l4_abe__timer5_dma,
4241 };
4242
4243 static struct omap_hwmod omap44xx_timer5_hwmod = {
4244         .name           = "timer5",
4245         .class          = &omap44xx_timer_hwmod_class,
4246         .mpu_irqs       = omap44xx_timer5_irqs,
4247         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer5_irqs),
4248         .main_clk       = "timer5_fck",
4249         .prcm = {
4250                 .omap4 = {
4251                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
4252                 },
4253         },
4254         .slaves         = omap44xx_timer5_slaves,
4255         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer5_slaves),
4256         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4257 };
4258
4259 /* timer6 */
4260 static struct omap_hwmod omap44xx_timer6_hwmod;
4261 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
4262         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
4263 };
4264
4265 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
4266         {
4267                 .pa_start       = 0x4013a000,
4268                 .pa_end         = 0x4013a07f,
4269                 .flags          = ADDR_TYPE_RT
4270         },
4271 };
4272
4273 /* l4_abe -> timer6 */
4274 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4275         .master         = &omap44xx_l4_abe_hwmod,
4276         .slave          = &omap44xx_timer6_hwmod,
4277         .clk            = "ocp_abe_iclk",
4278         .addr           = omap44xx_timer6_addrs,
4279         .addr_cnt       = ARRAY_SIZE(omap44xx_timer6_addrs),
4280         .user           = OCP_USER_MPU,
4281 };
4282
4283 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
4284         {
4285                 .pa_start       = 0x4903a000,
4286                 .pa_end         = 0x4903a07f,
4287                 .flags          = ADDR_TYPE_RT
4288         },
4289 };
4290
4291 /* l4_abe -> timer6 (dma) */
4292 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4293         .master         = &omap44xx_l4_abe_hwmod,
4294         .slave          = &omap44xx_timer6_hwmod,
4295         .clk            = "ocp_abe_iclk",
4296         .addr           = omap44xx_timer6_dma_addrs,
4297         .addr_cnt       = ARRAY_SIZE(omap44xx_timer6_dma_addrs),
4298         .user           = OCP_USER_SDMA,
4299 };
4300
4301 /* timer6 slave ports */
4302 static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
4303         &omap44xx_l4_abe__timer6,
4304         &omap44xx_l4_abe__timer6_dma,
4305 };
4306
4307 static struct omap_hwmod omap44xx_timer6_hwmod = {
4308         .name           = "timer6",
4309         .class          = &omap44xx_timer_hwmod_class,
4310         .mpu_irqs       = omap44xx_timer6_irqs,
4311         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer6_irqs),
4312         .main_clk       = "timer6_fck",
4313         .prcm = {
4314                 .omap4 = {
4315                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
4316                 },
4317         },
4318         .slaves         = omap44xx_timer6_slaves,
4319         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer6_slaves),
4320         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4321 };
4322
4323 /* timer7 */
4324 static struct omap_hwmod omap44xx_timer7_hwmod;
4325 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
4326         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
4327 };
4328
4329 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
4330         {
4331                 .pa_start       = 0x4013c000,
4332                 .pa_end         = 0x4013c07f,
4333                 .flags          = ADDR_TYPE_RT
4334         },
4335 };
4336
4337 /* l4_abe -> timer7 */
4338 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4339         .master         = &omap44xx_l4_abe_hwmod,
4340         .slave          = &omap44xx_timer7_hwmod,
4341         .clk            = "ocp_abe_iclk",
4342         .addr           = omap44xx_timer7_addrs,
4343         .addr_cnt       = ARRAY_SIZE(omap44xx_timer7_addrs),
4344         .user           = OCP_USER_MPU,
4345 };
4346
4347 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
4348         {
4349                 .pa_start       = 0x4903c000,
4350                 .pa_end         = 0x4903c07f,
4351                 .flags          = ADDR_TYPE_RT
4352         },
4353 };
4354
4355 /* l4_abe -> timer7 (dma) */
4356 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4357         .master         = &omap44xx_l4_abe_hwmod,
4358         .slave          = &omap44xx_timer7_hwmod,
4359         .clk            = "ocp_abe_iclk",
4360         .addr           = omap44xx_timer7_dma_addrs,
4361         .addr_cnt       = ARRAY_SIZE(omap44xx_timer7_dma_addrs),
4362         .user           = OCP_USER_SDMA,
4363 };
4364
4365 /* timer7 slave ports */
4366 static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
4367         &omap44xx_l4_abe__timer7,
4368         &omap44xx_l4_abe__timer7_dma,
4369 };
4370
4371 static struct omap_hwmod omap44xx_timer7_hwmod = {
4372         .name           = "timer7",
4373         .class          = &omap44xx_timer_hwmod_class,
4374         .mpu_irqs       = omap44xx_timer7_irqs,
4375         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer7_irqs),
4376         .main_clk       = "timer7_fck",
4377         .prcm = {
4378                 .omap4 = {
4379                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
4380                 },
4381         },
4382         .slaves         = omap44xx_timer7_slaves,
4383         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer7_slaves),
4384         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4385 };
4386
4387 /* timer8 */
4388 static struct omap_hwmod omap44xx_timer8_hwmod;
4389 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
4390         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
4391 };
4392
4393 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
4394         {
4395                 .pa_start       = 0x4013e000,
4396                 .pa_end         = 0x4013e07f,
4397                 .flags          = ADDR_TYPE_RT
4398         },
4399 };
4400
4401 /* l4_abe -> timer8 */
4402 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4403         .master         = &omap44xx_l4_abe_hwmod,
4404         .slave          = &omap44xx_timer8_hwmod,
4405         .clk            = "ocp_abe_iclk",
4406         .addr           = omap44xx_timer8_addrs,
4407         .addr_cnt       = ARRAY_SIZE(omap44xx_timer8_addrs),
4408         .user           = OCP_USER_MPU,
4409 };
4410
4411 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
4412         {
4413                 .pa_start       = 0x4903e000,
4414                 .pa_end         = 0x4903e07f,
4415                 .flags          = ADDR_TYPE_RT
4416         },
4417 };
4418
4419 /* l4_abe -> timer8 (dma) */
4420 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4421         .master         = &omap44xx_l4_abe_hwmod,
4422         .slave          = &omap44xx_timer8_hwmod,
4423         .clk            = "ocp_abe_iclk",
4424         .addr           = omap44xx_timer8_dma_addrs,
4425         .addr_cnt       = ARRAY_SIZE(omap44xx_timer8_dma_addrs),
4426         .user           = OCP_USER_SDMA,
4427 };
4428
4429 /* timer8 slave ports */
4430 static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
4431         &omap44xx_l4_abe__timer8,
4432         &omap44xx_l4_abe__timer8_dma,
4433 };
4434
4435 static struct omap_hwmod omap44xx_timer8_hwmod = {
4436         .name           = "timer8",
4437         .class          = &omap44xx_timer_hwmod_class,
4438         .mpu_irqs       = omap44xx_timer8_irqs,
4439         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer8_irqs),
4440         .main_clk       = "timer8_fck",
4441         .prcm = {
4442                 .omap4 = {
4443                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
4444                 },
4445         },
4446         .slaves         = omap44xx_timer8_slaves,
4447         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer8_slaves),
4448         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4449 };
4450
4451 /* timer9 */
4452 static struct omap_hwmod omap44xx_timer9_hwmod;
4453 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
4454         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
4455 };
4456
4457 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
4458         {
4459                 .pa_start       = 0x4803e000,
4460                 .pa_end         = 0x4803e07f,
4461                 .flags          = ADDR_TYPE_RT
4462         },
4463 };
4464
4465 /* l4_per -> timer9 */
4466 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4467         .master         = &omap44xx_l4_per_hwmod,
4468         .slave          = &omap44xx_timer9_hwmod,
4469         .clk            = "l4_div_ck",
4470         .addr           = omap44xx_timer9_addrs,
4471         .addr_cnt       = ARRAY_SIZE(omap44xx_timer9_addrs),
4472         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4473 };
4474
4475 /* timer9 slave ports */
4476 static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
4477         &omap44xx_l4_per__timer9,
4478 };
4479
4480 static struct omap_hwmod omap44xx_timer9_hwmod = {
4481         .name           = "timer9",
4482         .class          = &omap44xx_timer_hwmod_class,
4483         .mpu_irqs       = omap44xx_timer9_irqs,
4484         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer9_irqs),
4485         .main_clk       = "timer9_fck",
4486         .prcm = {
4487                 .omap4 = {
4488                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
4489                 },
4490         },
4491         .slaves         = omap44xx_timer9_slaves,
4492         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer9_slaves),
4493         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4494 };
4495
4496 /* timer10 */
4497 static struct omap_hwmod omap44xx_timer10_hwmod;
4498 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
4499         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
4500 };
4501
4502 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
4503         {
4504                 .pa_start       = 0x48086000,
4505                 .pa_end         = 0x4808607f,
4506                 .flags          = ADDR_TYPE_RT
4507         },
4508 };
4509
4510 /* l4_per -> timer10 */
4511 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4512         .master         = &omap44xx_l4_per_hwmod,
4513         .slave          = &omap44xx_timer10_hwmod,
4514         .clk            = "l4_div_ck",
4515         .addr           = omap44xx_timer10_addrs,
4516         .addr_cnt       = ARRAY_SIZE(omap44xx_timer10_addrs),
4517         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4518 };
4519
4520 /* timer10 slave ports */
4521 static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
4522         &omap44xx_l4_per__timer10,
4523 };
4524
4525 static struct omap_hwmod omap44xx_timer10_hwmod = {
4526         .name           = "timer10",
4527         .class          = &omap44xx_timer_1ms_hwmod_class,
4528         .mpu_irqs       = omap44xx_timer10_irqs,
4529         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer10_irqs),
4530         .main_clk       = "timer10_fck",
4531         .prcm = {
4532                 .omap4 = {
4533                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
4534                 },
4535         },
4536         .slaves         = omap44xx_timer10_slaves,
4537         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer10_slaves),
4538         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4539 };
4540
4541 /* timer11 */
4542 static struct omap_hwmod omap44xx_timer11_hwmod;
4543 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
4544         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
4545 };
4546
4547 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
4548         {
4549                 .pa_start       = 0x48088000,
4550                 .pa_end         = 0x4808807f,
4551                 .flags          = ADDR_TYPE_RT
4552         },
4553 };
4554
4555 /* l4_per -> timer11 */
4556 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4557         .master         = &omap44xx_l4_per_hwmod,
4558         .slave          = &omap44xx_timer11_hwmod,
4559         .clk            = "l4_div_ck",
4560         .addr           = omap44xx_timer11_addrs,
4561         .addr_cnt       = ARRAY_SIZE(omap44xx_timer11_addrs),
4562         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4563 };
4564
4565 /* timer11 slave ports */
4566 static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
4567         &omap44xx_l4_per__timer11,
4568 };
4569
4570 static struct omap_hwmod omap44xx_timer11_hwmod = {
4571         .name           = "timer11",
4572         .class          = &omap44xx_timer_hwmod_class,
4573         .mpu_irqs       = omap44xx_timer11_irqs,
4574         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer11_irqs),
4575         .main_clk       = "timer11_fck",
4576         .prcm = {
4577                 .omap4 = {
4578                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
4579                 },
4580         },
4581         .slaves         = omap44xx_timer11_slaves,
4582         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer11_slaves),
4583         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4584 };
4585
4586 /*
4587  * 'uart' class
4588  * universal asynchronous receiver/transmitter (uart)
4589  */
4590
4591 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
4592         .rev_offs       = 0x0050,
4593         .sysc_offs      = 0x0054,
4594         .syss_offs      = 0x0058,
4595         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4596                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4597                            SYSS_HAS_RESET_STATUS),
4598         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4599                            SIDLE_SMART_WKUP),
4600         .sysc_fields    = &omap_hwmod_sysc_type1,
4601 };
4602
4603 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
4604         .name   = "uart",
4605         .sysc   = &omap44xx_uart_sysc,
4606 };
4607
4608 /* uart1 */
4609 static struct omap_hwmod omap44xx_uart1_hwmod;
4610 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
4611         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
4612 };
4613
4614 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
4615         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
4616         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
4617 };
4618
4619 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
4620         {
4621                 .pa_start       = 0x4806a000,
4622                 .pa_end         = 0x4806a0ff,
4623                 .flags          = ADDR_TYPE_RT
4624         },
4625 };
4626
4627 /* l4_per -> uart1 */
4628 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4629         .master         = &omap44xx_l4_per_hwmod,
4630         .slave          = &omap44xx_uart1_hwmod,
4631         .clk            = "l4_div_ck",
4632         .addr           = omap44xx_uart1_addrs,
4633         .addr_cnt       = ARRAY_SIZE(omap44xx_uart1_addrs),
4634         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4635 };
4636
4637 /* uart1 slave ports */
4638 static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
4639         &omap44xx_l4_per__uart1,
4640 };
4641
4642 static struct omap_hwmod omap44xx_uart1_hwmod = {
4643         .name           = "uart1",
4644         .class          = &omap44xx_uart_hwmod_class,
4645         .mpu_irqs       = omap44xx_uart1_irqs,
4646         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart1_irqs),
4647         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
4648         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart1_sdma_reqs),
4649         .main_clk       = "uart1_fck",
4650         .prcm = {
4651                 .omap4 = {
4652                         .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
4653                 },
4654         },
4655         .slaves         = omap44xx_uart1_slaves,
4656         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart1_slaves),
4657         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4658 };
4659
4660 /* uart2 */
4661 static struct omap_hwmod omap44xx_uart2_hwmod;
4662 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
4663         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
4664 };
4665
4666 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
4667         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
4668         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
4669 };
4670
4671 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
4672         {
4673                 .pa_start       = 0x4806c000,
4674                 .pa_end         = 0x4806c0ff,
4675                 .flags          = ADDR_TYPE_RT
4676         },
4677 };
4678
4679 /* l4_per -> uart2 */
4680 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4681         .master         = &omap44xx_l4_per_hwmod,
4682         .slave          = &omap44xx_uart2_hwmod,
4683         .clk            = "l4_div_ck",
4684         .addr           = omap44xx_uart2_addrs,
4685         .addr_cnt       = ARRAY_SIZE(omap44xx_uart2_addrs),
4686         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4687 };
4688
4689 /* uart2 slave ports */
4690 static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
4691         &omap44xx_l4_per__uart2,
4692 };
4693
4694 static struct omap_hwmod omap44xx_uart2_hwmod = {
4695         .name           = "uart2",
4696         .class          = &omap44xx_uart_hwmod_class,
4697         .mpu_irqs       = omap44xx_uart2_irqs,
4698         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart2_irqs),
4699         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
4700         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart2_sdma_reqs),
4701         .main_clk       = "uart2_fck",
4702         .prcm = {
4703                 .omap4 = {
4704                         .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
4705                 },
4706         },
4707         .slaves         = omap44xx_uart2_slaves,
4708         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart2_slaves),
4709         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4710 };
4711
4712 /* uart3 */
4713 static struct omap_hwmod omap44xx_uart3_hwmod;
4714 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
4715         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
4716 };
4717
4718 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
4719         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
4720         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
4721 };
4722
4723 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
4724         {
4725                 .pa_start       = 0x48020000,
4726                 .pa_end         = 0x480200ff,
4727                 .flags          = ADDR_TYPE_RT
4728         },
4729 };
4730
4731 /* l4_per -> uart3 */
4732 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4733         .master         = &omap44xx_l4_per_hwmod,
4734         .slave          = &omap44xx_uart3_hwmod,
4735         .clk            = "l4_div_ck",
4736         .addr           = omap44xx_uart3_addrs,
4737         .addr_cnt       = ARRAY_SIZE(omap44xx_uart3_addrs),
4738         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4739 };
4740
4741 /* uart3 slave ports */
4742 static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
4743         &omap44xx_l4_per__uart3,
4744 };
4745
4746 static struct omap_hwmod omap44xx_uart3_hwmod = {
4747         .name           = "uart3",
4748         .class          = &omap44xx_uart_hwmod_class,
4749         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
4750         .mpu_irqs       = omap44xx_uart3_irqs,
4751         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart3_irqs),
4752         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
4753         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart3_sdma_reqs),
4754         .main_clk       = "uart3_fck",
4755         .prcm = {
4756                 .omap4 = {
4757                         .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
4758                 },
4759         },
4760         .slaves         = omap44xx_uart3_slaves,
4761         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart3_slaves),
4762         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4763 };
4764
4765 /* uart4 */
4766 static struct omap_hwmod omap44xx_uart4_hwmod;
4767 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
4768         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
4769 };
4770
4771 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
4772         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
4773         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
4774 };
4775
4776 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
4777         {
4778                 .pa_start       = 0x4806e000,
4779                 .pa_end         = 0x4806e0ff,
4780                 .flags          = ADDR_TYPE_RT
4781         },
4782 };
4783
4784 /* l4_per -> uart4 */
4785 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
4786         .master         = &omap44xx_l4_per_hwmod,
4787         .slave          = &omap44xx_uart4_hwmod,
4788         .clk            = "l4_div_ck",
4789         .addr           = omap44xx_uart4_addrs,
4790         .addr_cnt       = ARRAY_SIZE(omap44xx_uart4_addrs),
4791         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4792 };
4793
4794 /* uart4 slave ports */
4795 static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
4796         &omap44xx_l4_per__uart4,
4797 };
4798
4799 static struct omap_hwmod omap44xx_uart4_hwmod = {
4800         .name           = "uart4",
4801         .class          = &omap44xx_uart_hwmod_class,
4802         .mpu_irqs       = omap44xx_uart4_irqs,
4803         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart4_irqs),
4804         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
4805         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart4_sdma_reqs),
4806         .main_clk       = "uart4_fck",
4807         .prcm = {
4808                 .omap4 = {
4809                         .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
4810                 },
4811         },
4812         .slaves         = omap44xx_uart4_slaves,
4813         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart4_slaves),
4814         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4815 };
4816
4817 /*
4818  * 'usb_otg_hs' class
4819  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
4820  */
4821
4822 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
4823         .rev_offs       = 0x0400,
4824         .sysc_offs      = 0x0404,
4825         .syss_offs      = 0x0408,
4826         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4827                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
4828                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4829         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4830                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
4831                            MSTANDBY_SMART),
4832         .sysc_fields    = &omap_hwmod_sysc_type1,
4833 };
4834
4835 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
4836         .name = "usb_otg_hs",
4837         .sysc = &omap44xx_usb_otg_hs_sysc,
4838 };
4839
4840 /* usb_otg_hs */
4841 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
4842         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
4843         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
4844 };
4845
4846 /* usb_otg_hs master ports */
4847 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
4848         &omap44xx_usb_otg_hs__l3_main_2,
4849 };
4850
4851 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
4852         {
4853                 .pa_start       = 0x4a0ab000,
4854                 .pa_end         = 0x4a0ab003,
4855                 .flags          = ADDR_TYPE_RT
4856         },
4857 };
4858
4859 /* l4_cfg -> usb_otg_hs */
4860 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
4861         .master         = &omap44xx_l4_cfg_hwmod,
4862         .slave          = &omap44xx_usb_otg_hs_hwmod,
4863         .clk            = "l4_div_ck",
4864         .addr           = omap44xx_usb_otg_hs_addrs,
4865         .addr_cnt       = ARRAY_SIZE(omap44xx_usb_otg_hs_addrs),
4866         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4867 };
4868
4869 /* usb_otg_hs slave ports */
4870 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
4871         &omap44xx_l4_cfg__usb_otg_hs,
4872 };
4873
4874 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
4875         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
4876 };
4877
4878 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
4879         .name           = "usb_otg_hs",
4880         .class          = &omap44xx_usb_otg_hs_hwmod_class,
4881         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
4882         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
4883         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_usb_otg_hs_irqs),
4884         .main_clk       = "usb_otg_hs_ick",
4885         .prcm = {
4886                 .omap4 = {
4887                         .clkctrl_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
4888                 },
4889         },
4890         .opt_clks       = usb_otg_hs_opt_clks,
4891         .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
4892         .slaves         = omap44xx_usb_otg_hs_slaves,
4893         .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
4894         .masters        = omap44xx_usb_otg_hs_masters,
4895         .masters_cnt    = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
4896         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4897 };
4898
4899 /*
4900  * 'wd_timer' class
4901  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
4902  * overflow condition
4903  */
4904
4905 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
4906         .rev_offs       = 0x0000,
4907         .sysc_offs      = 0x0010,
4908         .syss_offs      = 0x0014,
4909         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
4910                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4911         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4912                            SIDLE_SMART_WKUP),
4913         .sysc_fields    = &omap_hwmod_sysc_type1,
4914 };
4915
4916 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
4917         .name           = "wd_timer",
4918         .sysc           = &omap44xx_wd_timer_sysc,
4919         .pre_shutdown   = &omap2_wd_timer_disable,
4920 };
4921
4922 /* wd_timer2 */
4923 static struct omap_hwmod omap44xx_wd_timer2_hwmod;
4924 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
4925         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
4926 };
4927
4928 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
4929         {
4930                 .pa_start       = 0x4a314000,
4931                 .pa_end         = 0x4a31407f,
4932                 .flags          = ADDR_TYPE_RT
4933         },
4934 };
4935
4936 /* l4_wkup -> wd_timer2 */
4937 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
4938         .master         = &omap44xx_l4_wkup_hwmod,
4939         .slave          = &omap44xx_wd_timer2_hwmod,
4940         .clk            = "l4_wkup_clk_mux_ck",
4941         .addr           = omap44xx_wd_timer2_addrs,
4942         .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer2_addrs),
4943         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4944 };
4945
4946 /* wd_timer2 slave ports */
4947 static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
4948         &omap44xx_l4_wkup__wd_timer2,
4949 };
4950
4951 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
4952         .name           = "wd_timer2",
4953         .class          = &omap44xx_wd_timer_hwmod_class,
4954         .mpu_irqs       = omap44xx_wd_timer2_irqs,
4955         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
4956         .main_clk       = "wd_timer2_fck",
4957         .prcm = {
4958                 .omap4 = {
4959                         .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
4960                 },
4961         },
4962         .slaves         = omap44xx_wd_timer2_slaves,
4963         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
4964         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4965 };
4966
4967 /* wd_timer3 */
4968 static struct omap_hwmod omap44xx_wd_timer3_hwmod;
4969 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
4970         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
4971 };
4972
4973 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
4974         {
4975                 .pa_start       = 0x40130000,
4976                 .pa_end         = 0x4013007f,
4977                 .flags          = ADDR_TYPE_RT
4978         },
4979 };
4980
4981 /* l4_abe -> wd_timer3 */
4982 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
4983         .master         = &omap44xx_l4_abe_hwmod,
4984         .slave          = &omap44xx_wd_timer3_hwmod,
4985         .clk            = "ocp_abe_iclk",
4986         .addr           = omap44xx_wd_timer3_addrs,
4987         .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer3_addrs),
4988         .user           = OCP_USER_MPU,
4989 };
4990
4991 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
4992         {
4993                 .pa_start       = 0x49030000,
4994                 .pa_end         = 0x4903007f,
4995                 .flags          = ADDR_TYPE_RT
4996         },
4997 };
4998
4999 /* l4_abe -> wd_timer3 (dma) */
5000 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5001         .master         = &omap44xx_l4_abe_hwmod,
5002         .slave          = &omap44xx_wd_timer3_hwmod,
5003         .clk            = "ocp_abe_iclk",
5004         .addr           = omap44xx_wd_timer3_dma_addrs,
5005         .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
5006         .user           = OCP_USER_SDMA,
5007 };
5008
5009 /* wd_timer3 slave ports */
5010 static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
5011         &omap44xx_l4_abe__wd_timer3,
5012         &omap44xx_l4_abe__wd_timer3_dma,
5013 };
5014
5015 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
5016         .name           = "wd_timer3",
5017         .class          = &omap44xx_wd_timer_hwmod_class,
5018         .mpu_irqs       = omap44xx_wd_timer3_irqs,
5019         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
5020         .main_clk       = "wd_timer3_fck",
5021         .prcm = {
5022                 .omap4 = {
5023                         .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
5024                 },
5025         },
5026         .slaves         = omap44xx_wd_timer3_slaves,
5027         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
5028         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
5029 };
5030
5031 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
5032
5033         /* dmm class */
5034         &omap44xx_dmm_hwmod,
5035
5036         /* emif_fw class */
5037         &omap44xx_emif_fw_hwmod,
5038
5039         /* l3 class */
5040         &omap44xx_l3_instr_hwmod,
5041         &omap44xx_l3_main_1_hwmod,
5042         &omap44xx_l3_main_2_hwmod,
5043         &omap44xx_l3_main_3_hwmod,
5044
5045         /* l4 class */
5046         &omap44xx_l4_abe_hwmod,
5047         &omap44xx_l4_cfg_hwmod,
5048         &omap44xx_l4_per_hwmod,
5049         &omap44xx_l4_wkup_hwmod,
5050
5051         /* mpu_bus class */
5052         &omap44xx_mpu_private_hwmod,
5053
5054         /* aess class */
5055 /*      &omap44xx_aess_hwmod, */
5056
5057         /* bandgap class */
5058         &omap44xx_bandgap_hwmod,
5059
5060         /* counter class */
5061 /*      &omap44xx_counter_32k_hwmod, */
5062
5063         /* dma class */
5064         &omap44xx_dma_system_hwmod,
5065
5066         /* dmic class */
5067         &omap44xx_dmic_hwmod,
5068
5069         /* dsp class */
5070         &omap44xx_dsp_hwmod,
5071         &omap44xx_dsp_c0_hwmod,
5072
5073         /* dss class */
5074         &omap44xx_dss_hwmod,
5075         &omap44xx_dss_dispc_hwmod,
5076         &omap44xx_dss_dsi1_hwmod,
5077         &omap44xx_dss_dsi2_hwmod,
5078         &omap44xx_dss_hdmi_hwmod,
5079         &omap44xx_dss_rfbi_hwmod,
5080         &omap44xx_dss_venc_hwmod,
5081
5082         /* gpio class */
5083         &omap44xx_gpio1_hwmod,
5084         &omap44xx_gpio2_hwmod,
5085         &omap44xx_gpio3_hwmod,
5086         &omap44xx_gpio4_hwmod,
5087         &omap44xx_gpio5_hwmod,
5088         &omap44xx_gpio6_hwmod,
5089
5090         /* hsi class */
5091 /*      &omap44xx_hsi_hwmod, */
5092
5093         /* i2c class */
5094         &omap44xx_i2c1_hwmod,
5095         &omap44xx_i2c2_hwmod,
5096         &omap44xx_i2c3_hwmod,
5097         &omap44xx_i2c4_hwmod,
5098
5099         /* ipu class */
5100         &omap44xx_ipu_hwmod,
5101         &omap44xx_ipu_c0_hwmod,
5102         &omap44xx_ipu_c1_hwmod,
5103
5104         /* iss class */
5105 /*      &omap44xx_iss_hwmod, */
5106
5107         /* iva class */
5108         &omap44xx_iva_hwmod,
5109         &omap44xx_iva_seq0_hwmod,
5110         &omap44xx_iva_seq1_hwmod,
5111
5112         /* kbd class */
5113         &omap44xx_kbd_hwmod,
5114
5115         /* mailbox class */
5116         &omap44xx_mailbox_hwmod,
5117
5118         /* mcbsp class */
5119         &omap44xx_mcbsp1_hwmod,
5120         &omap44xx_mcbsp2_hwmod,
5121         &omap44xx_mcbsp3_hwmod,
5122         &omap44xx_mcbsp4_hwmod,
5123
5124         /* mcpdm class */
5125 /*      &omap44xx_mcpdm_hwmod, */
5126
5127         /* mcspi class */
5128         &omap44xx_mcspi1_hwmod,
5129         &omap44xx_mcspi2_hwmod,
5130         &omap44xx_mcspi3_hwmod,
5131         &omap44xx_mcspi4_hwmod,
5132
5133         /* mmc class */
5134         &omap44xx_mmc1_hwmod,
5135         &omap44xx_mmc2_hwmod,
5136         &omap44xx_mmc3_hwmod,
5137         &omap44xx_mmc4_hwmod,
5138         &omap44xx_mmc5_hwmod,
5139
5140         /* mpu class */
5141         &omap44xx_mpu_hwmod,
5142
5143         /* smartreflex class */
5144         &omap44xx_smartreflex_core_hwmod,
5145         &omap44xx_smartreflex_iva_hwmod,
5146         &omap44xx_smartreflex_mpu_hwmod,
5147
5148         /* spinlock class */
5149         &omap44xx_spinlock_hwmod,
5150
5151         /* timer class */
5152         &omap44xx_timer1_hwmod,
5153         &omap44xx_timer2_hwmod,
5154         &omap44xx_timer3_hwmod,
5155         &omap44xx_timer4_hwmod,
5156         &omap44xx_timer5_hwmod,
5157         &omap44xx_timer6_hwmod,
5158         &omap44xx_timer7_hwmod,
5159         &omap44xx_timer8_hwmod,
5160         &omap44xx_timer9_hwmod,
5161         &omap44xx_timer10_hwmod,
5162         &omap44xx_timer11_hwmod,
5163
5164         /* uart class */
5165         &omap44xx_uart1_hwmod,
5166         &omap44xx_uart2_hwmod,
5167         &omap44xx_uart3_hwmod,
5168         &omap44xx_uart4_hwmod,
5169
5170         /* usb_otg_hs class */
5171         &omap44xx_usb_otg_hs_hwmod,
5172
5173         /* wd_timer class */
5174         &omap44xx_wd_timer2_hwmod,
5175         &omap44xx_wd_timer3_hwmod,
5176
5177         NULL,
5178 };
5179
5180 int __init omap44xx_hwmod_init(void)
5181 {
5182         return omap_hwmod_register(omap44xx_hwmods);
5183 }
5184