2 * linux/arch/arm/mach-omap2/mmc-twl4030.c
4 * Copyright (C) 2007-2008 Texas Instruments
5 * Copyright (C) 2008 Nokia Corporation
6 * Author: Texas Instruments
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 #include <linux/err.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/interrupt.h>
17 #include <linux/delay.h>
18 #include <linux/gpio.h>
19 #include <linux/i2c/twl4030.h>
21 #include <mach/hardware.h>
22 #include <mach/control.h>
24 #include <mach/board.h>
26 #include "mmc-twl4030.h"
28 #if defined(CONFIG_TWL4030_CORE) && \
29 (defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE))
32 #define VSEL_S2_CLR 0x40
34 #define VMMC1_DEV_GRP 0x27
35 #define VMMC1_CLR 0x00
36 #define VMMC1_315V 0x03
37 #define VMMC1_300V 0x02
38 #define VMMC1_285V 0x01
39 #define VMMC1_185V 0x00
40 #define VMMC1_DEDICATED 0x2A
42 #define VMMC2_DEV_GRP 0x2B
43 #define VMMC2_CLR 0x40
44 #define VMMC2_315V 0x0c
45 #define VMMC2_300V 0x0b
46 #define VMMC2_285V 0x0a
47 #define VMMC2_280V 0x09
48 #define VMMC2_260V 0x08
49 #define VMMC2_185V 0x06
50 #define VMMC2_DEDICATED 0x2E
52 #define VMMC_DEV_GRP_P1 0x20
54 static u16 control_pbias_offset;
55 static u16 control_devconf1_offset;
57 #define HSMMC_NAME_LEN 9
59 static struct twl_mmc_controller {
60 struct omap_mmc_platform_data *mmc;
63 char name[HSMMC_NAME_LEN + 1];
66 .twl_vmmc_dev_grp = VMMC1_DEV_GRP,
67 .twl_mmc_dedicated = VMMC1_DEDICATED,
70 .twl_vmmc_dev_grp = VMMC2_DEV_GRP,
71 .twl_mmc_dedicated = VMMC2_DEDICATED,
75 static int twl_mmc_card_detect(int irq)
79 for (i = 0; i < ARRAY_SIZE(hsmmc); i++) {
80 struct omap_mmc_platform_data *mmc;
85 if (irq != mmc->slots[0].card_detect_irq)
88 /* NOTE: assumes card detect signal is active-low */
89 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
94 static int twl_mmc_get_ro(struct device *dev, int slot)
96 struct omap_mmc_platform_data *mmc = dev->platform_data;
98 /* NOTE: assumes write protect signal is active-high */
99 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
103 * MMC Slot Initialization.
105 static int twl_mmc_late_init(struct device *dev)
107 struct omap_mmc_platform_data *mmc = dev->platform_data;
111 ret = gpio_request(mmc->slots[0].switch_pin, "mmc_cd");
114 ret = gpio_direction_input(mmc->slots[0].switch_pin);
118 for (i = 0; i < ARRAY_SIZE(hsmmc); i++) {
119 if (hsmmc[i].name == mmc->slots[0].name) {
128 gpio_free(mmc->slots[0].switch_pin);
130 mmc->slots[0].card_detect_irq = 0;
131 mmc->slots[0].card_detect = NULL;
133 dev_err(dev, "err %d configuring card detect\n", ret);
137 static void twl_mmc_cleanup(struct device *dev)
139 struct omap_mmc_platform_data *mmc = dev->platform_data;
141 gpio_free(mmc->slots[0].switch_pin);
146 static int twl_mmc_suspend(struct device *dev, int slot)
148 struct omap_mmc_platform_data *mmc = dev->platform_data;
150 disable_irq(mmc->slots[0].card_detect_irq);
154 static int twl_mmc_resume(struct device *dev, int slot)
156 struct omap_mmc_platform_data *mmc = dev->platform_data;
158 enable_irq(mmc->slots[0].card_detect_irq);
163 #define twl_mmc_suspend NULL
164 #define twl_mmc_resume NULL
168 * Sets the MMC voltage in twl4030
171 #define MMC1_OCR (MMC_VDD_165_195 \
172 |MMC_VDD_28_29|MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32)
173 #define MMC2_OCR (MMC_VDD_165_195 \
174 |MMC_VDD_25_26|MMC_VDD_26_27|MMC_VDD_27_28 \
175 |MMC_VDD_28_29|MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32)
177 static int twl_mmc_set_voltage(struct twl_mmc_controller *c, int vdd)
180 u8 vmmc, dev_grp_val;
182 if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP) {
183 /* VMMC1: max 220 mA. And for 8-bit mode,
187 case MMC_VDD_165_195:
202 /* error if VSIM needed */
208 } else if (c->twl_vmmc_dev_grp == VMMC2_DEV_GRP) {
209 /* VMMC2: max 100 mA */
211 case MMC_VDD_165_195:
240 dev_grp_val = VMMC_DEV_GRP_P1; /* Power up */
242 dev_grp_val = LDO_CLR; /* Power down */
244 ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
245 dev_grp_val, c->twl_vmmc_dev_grp);
249 ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
250 vmmc, c->twl_mmc_dedicated);
255 static int twl_mmc1_set_power(struct device *dev, int slot, int power_on,
260 struct twl_mmc_controller *c = &hsmmc[0];
261 struct omap_mmc_platform_data *mmc = dev->platform_data;
264 * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
265 * card using the same TWL VMMC1 supply (hsmmc[0]); OMAP has both
266 * 1.8V and 3.0V modes, controlled by the PBIAS register.
268 * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
269 * is most naturally TWL VSIM; those pins also use PBIAS.
272 if (cpu_is_omap2430()) {
273 reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
274 if ((1 << vdd) >= MMC_VDD_30_31)
275 reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
277 reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
278 omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
281 if (mmc->slots[0].internal_clock) {
282 reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
283 reg |= OMAP2_MMCSDIO1ADPCLKISEL;
284 omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
287 reg = omap_ctrl_readl(control_pbias_offset);
288 reg |= OMAP2_PBIASSPEEDCTRL0;
289 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
290 omap_ctrl_writel(reg, control_pbias_offset);
292 ret = twl_mmc_set_voltage(c, vdd);
294 /* 100ms delay required for PBIAS configuration */
296 reg = omap_ctrl_readl(control_pbias_offset);
297 reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
298 if ((1 << vdd) <= MMC_VDD_165_195)
299 reg &= ~OMAP2_PBIASLITEVMODE0;
301 reg |= OMAP2_PBIASLITEVMODE0;
302 omap_ctrl_writel(reg, control_pbias_offset);
304 reg = omap_ctrl_readl(control_pbias_offset);
305 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
306 omap_ctrl_writel(reg, control_pbias_offset);
308 ret = twl_mmc_set_voltage(c, 0);
310 /* 100ms delay required for PBIAS configuration */
312 reg = omap_ctrl_readl(control_pbias_offset);
313 reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
314 OMAP2_PBIASLITEVMODE0);
315 omap_ctrl_writel(reg, control_pbias_offset);
321 static int twl_mmc2_set_power(struct device *dev, int slot, int power_on, int vdd)
324 struct twl_mmc_controller *c = &hsmmc[1];
325 struct omap_mmc_platform_data *mmc = dev->platform_data;
328 * Assume TWL VMMC2 (hsmmc[1]) is used only to power the card ... OMAP
329 * VDDS is used to power the pins, optionally with a transceiver to
330 * support cards using voltages other than VDDS (1.8V nominal). When a
331 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
334 if (mmc->slots[0].internal_clock) {
337 reg = omap_ctrl_readl(control_devconf1_offset);
338 reg |= OMAP2_MMCSDIO2ADPCLKISEL;
339 omap_ctrl_writel(reg, control_devconf1_offset);
341 ret = twl_mmc_set_voltage(c, vdd);
343 ret = twl_mmc_set_voltage(c, 0);
349 static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata;
351 void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers)
353 struct twl4030_hsmmc_info *c;
354 int nr_hsmmc = ARRAY_SIZE(hsmmc_data);
356 if (cpu_is_omap2430()) {
357 control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
358 control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
361 control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
362 control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
365 for (c = controllers; c->mmc; c++) {
366 struct twl_mmc_controller *twl = hsmmc + c->mmc - 1;
367 struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];
369 if (!c->mmc || c->mmc > nr_hsmmc) {
370 pr_debug("MMC%d: no such controller\n", c->mmc);
374 pr_debug("MMC%d: already configured\n", c->mmc);
378 mmc = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
380 pr_err("Cannot allocate memory for mmc device!\n");
384 snprintf(twl->name, ARRAY_SIZE(twl->name), "mmc%islot%i",
386 mmc->slots[0].name = twl->name;
388 mmc->slots[0].wires = c->wires;
389 mmc->slots[0].internal_clock = !c->ext_clock;
390 mmc->dma_mask = 0xffffffff;
392 /* note: twl4030 card detect GPIOs normally switch VMMCx ... */
393 if (gpio_is_valid(c->gpio_cd)) {
394 mmc->init = twl_mmc_late_init;
395 mmc->cleanup = twl_mmc_cleanup;
396 mmc->suspend = twl_mmc_suspend;
397 mmc->resume = twl_mmc_resume;
399 mmc->slots[0].switch_pin = c->gpio_cd;
400 mmc->slots[0].card_detect_irq = gpio_to_irq(c->gpio_cd);
401 mmc->slots[0].card_detect = twl_mmc_card_detect;
403 mmc->slots[0].switch_pin = -EINVAL;
405 /* write protect normally uses an OMAP gpio */
406 if (gpio_is_valid(c->gpio_wp)) {
407 gpio_request(c->gpio_wp, "mmc_wp");
408 gpio_direction_input(c->gpio_wp);
410 mmc->slots[0].gpio_wp = c->gpio_wp;
411 mmc->slots[0].get_ro = twl_mmc_get_ro;
413 mmc->slots[0].gpio_wp = -EINVAL;
415 /* NOTE: we assume OMAP's MMC1 and MMC2 use
416 * the TWL4030's VMMC1 and VMMC2, respectively;
417 * and that OMAP's MMC3 isn't used.
422 mmc->slots[0].set_power = twl_mmc1_set_power;
423 mmc->slots[0].ocr_mask = MMC1_OCR;
426 mmc->slots[0].set_power = twl_mmc2_set_power;
428 mmc->slots[0].ocr_mask = MMC2_OCR;
430 mmc->slots[0].ocr_mask = MMC_VDD_165_195;
433 pr_err("MMC%d configuration not supported!\n", c->mmc);
436 hsmmc_data[c->mmc - 1] = mmc;
439 omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC);