2 * linux/arch/arm/mach-omap2/hsmmc.c
4 * Copyright (C) 2007-2008 Texas Instruments
5 * Copyright (C) 2008 Nokia Corporation
6 * Author: Texas Instruments
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/slab.h>
14 #include <linux/string.h>
15 #include <linux/delay.h>
16 #include <mach/hardware.h>
18 #include <plat/omap-pm.h>
23 #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
25 static u16 control_pbias_offset;
26 static u16 control_devconf1_offset;
27 static u16 control_mmc1;
29 #define HSMMC_NAME_LEN 9
31 static struct hsmmc_controller {
32 char name[HSMMC_NAME_LEN + 1];
33 } hsmmc[OMAP34XX_NR_MMC];
35 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
37 static int hsmmc_get_context_loss(struct device *dev)
39 return omap_pm_get_dev_context_loss_count(dev);
43 #define hsmmc_get_context_loss NULL
46 static void omap_hsmmc1_before_set_reg(struct device *dev, int slot,
47 int power_on, int vdd)
50 struct omap_mmc_platform_data *mmc = dev->platform_data;
52 if (mmc->slots[0].remux)
53 mmc->slots[0].remux(dev, slot, power_on);
56 * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
57 * card with Vcc regulator (from twl4030 or whatever). OMAP has both
58 * 1.8V and 3.0V modes, controlled by the PBIAS register.
60 * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
61 * is most naturally TWL VSIM; those pins also use PBIAS.
63 * FIXME handle VMMC1A as needed ...
66 if (cpu_is_omap2430()) {
67 reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
68 if ((1 << vdd) >= MMC_VDD_30_31)
69 reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
71 reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
72 omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
75 if (mmc->slots[0].internal_clock) {
76 reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
77 reg |= OMAP2_MMCSDIO1ADPCLKISEL;
78 omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
81 reg = omap_ctrl_readl(control_pbias_offset);
82 if (cpu_is_omap3630()) {
83 /* Set MMC I/O to 52Mhz */
84 prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
85 prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
86 omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
88 reg |= OMAP2_PBIASSPEEDCTRL0;
90 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
91 omap_ctrl_writel(reg, control_pbias_offset);
93 reg = omap_ctrl_readl(control_pbias_offset);
94 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
95 omap_ctrl_writel(reg, control_pbias_offset);
99 static void omap_hsmmc1_after_set_reg(struct device *dev, int slot,
100 int power_on, int vdd)
104 /* 100ms delay required for PBIAS configuration */
108 reg = omap_ctrl_readl(control_pbias_offset);
109 reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
110 if ((1 << vdd) <= MMC_VDD_165_195)
111 reg &= ~OMAP2_PBIASLITEVMODE0;
113 reg |= OMAP2_PBIASLITEVMODE0;
114 omap_ctrl_writel(reg, control_pbias_offset);
116 reg = omap_ctrl_readl(control_pbias_offset);
117 reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
118 OMAP2_PBIASLITEVMODE0);
119 omap_ctrl_writel(reg, control_pbias_offset);
123 static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
124 int power_on, int vdd)
129 * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
130 * card with Vcc regulator (from twl4030 or whatever). OMAP has both
131 * 1.8V and 3.0V modes, controlled by the PBIAS register.
133 * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
134 * is most naturally TWL VSIM; those pins also use PBIAS.
136 * FIXME handle VMMC1A as needed ...
138 reg = omap4_ctrl_pad_readl(control_pbias_offset);
139 reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
140 OMAP4_MMC1_PWRDNZ_MASK |
141 OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
142 omap4_ctrl_pad_writel(reg, control_pbias_offset);
145 static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
146 int power_on, int vdd)
151 reg = omap4_ctrl_pad_readl(control_pbias_offset);
152 reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK;
153 if ((1 << vdd) <= MMC_VDD_165_195)
154 reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK;
156 reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK;
157 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
158 OMAP4_MMC1_PWRDNZ_MASK |
159 OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
160 omap4_ctrl_pad_writel(reg, control_pbias_offset);
161 /* 4 microsec delay for comparator to generate an error*/
163 reg = omap4_ctrl_pad_readl(control_pbias_offset);
164 if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {
165 pr_err("Pbias Voltage is not same as LDO\n");
166 /* Caution : On VMODE_ERROR Power Down MMC IO */
167 reg &= ~(OMAP4_MMC1_PWRDNZ_MASK |
168 OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
169 omap4_ctrl_pad_writel(reg, control_pbias_offset);
172 reg = omap4_ctrl_pad_readl(control_pbias_offset);
173 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
174 OMAP4_MMC1_PWRDNZ_MASK |
175 OMAP4_MMC1_PBIASLITE_VMODE_MASK |
176 OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
177 omap4_ctrl_pad_writel(reg, control_pbias_offset);
181 static void hsmmc23_before_set_reg(struct device *dev, int slot,
182 int power_on, int vdd)
184 struct omap_mmc_platform_data *mmc = dev->platform_data;
186 if (mmc->slots[0].remux)
187 mmc->slots[0].remux(dev, slot, power_on);
190 /* Only MMC2 supports a CLKIN */
191 if (mmc->slots[0].internal_clock) {
194 reg = omap_ctrl_readl(control_devconf1_offset);
195 reg |= OMAP2_MMCSDIO2ADPCLKISEL;
196 omap_ctrl_writel(reg, control_devconf1_offset);
201 static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
207 static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata;
209 void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
211 struct omap2_hsmmc_info *c;
212 int nr_hsmmc = ARRAY_SIZE(hsmmc_data);
216 if (!cpu_is_omap44xx()) {
217 if (cpu_is_omap2430()) {
218 control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
219 control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
221 control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
222 control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
225 control_pbias_offset =
226 OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
227 control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
228 reg = omap4_ctrl_pad_readl(control_mmc1);
229 reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
230 OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
231 reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
232 OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
233 reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK|
234 OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
235 OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
236 omap4_ctrl_pad_writel(reg, control_mmc1);
239 for (c = controllers; c->mmc; c++) {
240 struct hsmmc_controller *hc = hsmmc + c->mmc - 1;
241 struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];
243 if (!c->mmc || c->mmc > nr_hsmmc) {
244 pr_debug("MMC%d: no such controller\n", c->mmc);
248 pr_debug("MMC%d: already configured\n", c->mmc);
252 mmc = kzalloc(sizeof(struct omap_mmc_platform_data),
255 pr_err("Cannot allocate memory for mmc device!\n");
260 strncpy(hc->name, c->name, HSMMC_NAME_LEN);
262 snprintf(hc->name, ARRAY_SIZE(hc->name),
263 "mmc%islot%i", c->mmc, 1);
264 mmc->slots[0].name = hc->name;
266 mmc->slots[0].caps = c->caps;
267 mmc->slots[0].internal_clock = !c->ext_clock;
268 mmc->dma_mask = 0xffffffff;
269 if (cpu_is_omap44xx())
270 mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
274 mmc->get_context_loss_count = hsmmc_get_context_loss;
276 mmc->slots[0].switch_pin = c->gpio_cd;
277 mmc->slots[0].gpio_wp = c->gpio_wp;
279 mmc->slots[0].remux = c->remux;
280 mmc->slots[0].init_card = c->init_card;
283 mmc->slots[0].cover = 1;
286 mmc->slots[0].nonremovable = 1;
289 mmc->slots[0].power_saving = 1;
292 mmc->slots[0].no_off = 1;
294 if (c->vcc_aux_disable_is_sleep)
295 mmc->slots[0].vcc_aux_disable_is_sleep = 1;
297 /* NOTE: MMC slots should have a Vcc regulator set up.
298 * This may be from a TWL4030-family chip, another
299 * controllable regulator, or a fixed supply.
301 * temporary HACK: ocr_mask instead of fixed supply
303 mmc->slots[0].ocr_mask = c->ocr_mask;
305 if (cpu_is_omap3517() || cpu_is_omap3505())
306 mmc->slots[0].set_power = nop_mmc_set_power;
308 mmc->slots[0].features |= HSMMC_HAS_PBIAS;
310 if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
311 mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
315 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
316 /* on-chip level shifting via PBIAS0/PBIAS1 */
317 if (cpu_is_omap44xx()) {
318 mmc->slots[0].before_set_reg =
319 omap4_hsmmc1_before_set_reg;
320 mmc->slots[0].after_set_reg =
321 omap4_hsmmc1_after_set_reg;
323 mmc->slots[0].before_set_reg =
324 omap_hsmmc1_before_set_reg;
325 mmc->slots[0].after_set_reg =
326 omap_hsmmc1_after_set_reg;
330 /* Omap3630 HSMMC1 supports only 4-bit */
331 if (cpu_is_omap3630() &&
332 (c->caps & MMC_CAP_8_BIT_DATA)) {
333 c->caps &= ~MMC_CAP_8_BIT_DATA;
334 c->caps |= MMC_CAP_4_BIT_DATA;
335 mmc->slots[0].caps = c->caps;
341 if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
342 c->caps &= ~MMC_CAP_8_BIT_DATA;
343 c->caps |= MMC_CAP_4_BIT_DATA;
347 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
348 /* off-chip level shifting, or none */
349 mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
350 mmc->slots[0].after_set_reg = NULL;
354 pr_err("MMC%d configuration not supported!\n", c->mmc);
358 hsmmc_data[c->mmc - 1] = mmc;
361 omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC);
363 /* pass the device nodes back to board setup code */
364 for (c = controllers; c->mmc; c++) {
365 struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];
367 if (!c->mmc || c->mmc > nr_hsmmc)
373 for (i = 0; i < nr_hsmmc; i++)
374 kfree(hsmmc_data[i]);