arch/arm/mach-omap2/display.c

   1 /*
   2  * OMAP2plus display device setup / initialization.
   3  *
   4  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   5  *      Senthilvadivu Guruswamy
   6  *      Sumit Semwal
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  13  * kind, whether express or implied; without even the implied warranty
  14  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/string.h>
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/io.h>
  23 #include <linux/clk.h>
  24 #include <linux/err.h>
  25 #include <linux/delay.h>
  26
  27 #include <video/omapdss.h>
  28 #include <plat/omap_hwmod.h>
  29 #include <plat/omap_device.h>
  30 #include <plat/omap-pm.h>
  31 #include "common.h"
  32
  33 #include "mux.h"
  34 #include "control.h"
  35 #include "display.h"
  36
  37 #define DISPC_CONTROL           0x0040
  38 #define DISPC_CONTROL2          0x0238
  39 #define DISPC_IRQSTATUS         0x0018
  40
  41 #define DSS_SYSCONFIG           0x10
  42 #define DSS_SYSSTATUS           0x14
  43 #define DSS_CONTROL             0x40
  44 #define DSS_SDI_CONTROL         0x44
  45 #define DSS_PLL_CONTROL         0x48
  46
  47 #define LCD_EN_MASK             (0x1 << 0)
  48 #define DIGIT_EN_MASK           (0x1 << 1)
  49
  50 #define FRAMEDONE_IRQ_SHIFT     0
  51 #define EVSYNC_EVEN_IRQ_SHIFT   2
  52 #define EVSYNC_ODD_IRQ_SHIFT    3
  53 #define FRAMEDONE2_IRQ_SHIFT    22
  54 #define FRAMEDONETV_IRQ_SHIFT   24
  55
  56 /*
  57  * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
  58  *     reset before deciding that something has gone wrong
  59  */
  60 #define FRAMEDONE_IRQ_TIMEOUT           100
  61
  62 static struct platform_device omap_display_device = {
  63         .name          = "omapdss",
  64         .id            = -1,
  65         .dev            = {
  66                 .platform_data = NULL,
  67         },
  68 };
  69
  70 struct omap_dss_hwmod_data {
  71         const char *oh_name;
  72         const char *dev_name;
  73         const int id;
  74 };
  75
  76 static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initdata = {
  77         { "dss_core", "omapdss_dss", -1 },
  78         { "dss_dispc", "omapdss_dispc", -1 },
  79         { "dss_rfbi", "omapdss_rfbi", -1 },
  80         { "dss_venc", "omapdss_venc", -1 },
  81 };
  82
  83 static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = {
  84         { "dss_core", "omapdss_dss", -1 },
  85         { "dss_dispc", "omapdss_dispc", -1 },
  86         { "dss_rfbi", "omapdss_rfbi", -1 },
  87         { "dss_venc", "omapdss_venc", -1 },
  88         { "dss_dsi1", "omapdss_dsi", 0 },
  89 };
  90
  91 static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initdata = {
  92         { "dss_core", "omapdss_dss", -1 },
  93         { "dss_dispc", "omapdss_dispc", -1 },
  94         { "dss_rfbi", "omapdss_rfbi", -1 },
  95         { "dss_venc", "omapdss_venc", -1 },
  96         { "dss_dsi1", "omapdss_dsi", 0 },
  97         { "dss_dsi2", "omapdss_dsi", 1 },
  98         { "dss_hdmi", "omapdss_hdmi", -1 },
  99 };
 100
 101 static void omap4_hdmi_mux_pads(enum omap_hdmi_flags flags)
 102 {
 103         u32 reg;
 104         u16 control_i2c_1;
 105
 106         /* PAD0_HDMI_HPD_PAD1_HDMI_CEC */
 107         omap_mux_init_signal("hdmi_hpd",
 108                         OMAP_PIN_INPUT_PULLUP);
 109         omap_mux_init_signal("hdmi_cec",
 110                         OMAP_PIN_INPUT_PULLUP);
 111         /* PAD0_HDMI_DDC_SCL_PAD1_HDMI_DDC_SDA */
 112         omap_mux_init_signal("hdmi_ddc_scl",
 113                         OMAP_PIN_INPUT_PULLUP);
 114         omap_mux_init_signal("hdmi_ddc_sda",
 115                         OMAP_PIN_INPUT_PULLUP);
 116
 117         /*
 118          * CONTROL_I2C_1: HDMI_DDC_SDA_PULLUPRESX (bit 28) and
 119          * HDMI_DDC_SCL_PULLUPRESX (bit 24) are set to disable
 120          * internal pull up resistor.
 121          */
 122         if (flags & OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP) {
 123                 control_i2c_1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1;
 124                 reg = omap4_ctrl_pad_readl(control_i2c_1);
 125                 reg |= (OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK |
 126                         OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK);
 127                         omap4_ctrl_pad_writel(reg, control_i2c_1);
 128         }
 129 }
 130
 131 static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
 132 {
 133         u32 enable_mask, enable_shift;
 134         u32 pipd_mask, pipd_shift;
 135         u32 reg;
 136
 137         if (dsi_id == 0) {
 138                 enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
 139                 enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
 140                 pipd_mask = OMAP4_DSI1_PIPD_MASK;
 141                 pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
 142         } else if (dsi_id == 1) {
 143                 enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
 144                 enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
 145                 pipd_mask = OMAP4_DSI2_PIPD_MASK;
 146                 pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
 147         } else {
 148                 return -ENODEV;
 149         }
 150
 151         reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
 152
 153         reg &= ~enable_mask;
 154         reg &= ~pipd_mask;
 155
 156         reg |= (lanes << enable_shift) & enable_mask;
 157         reg |= (lanes << pipd_shift) & pipd_mask;
 158
 159         omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
 160
 161         return 0;
 162 }
 163
 164 int omap_hdmi_init(enum omap_hdmi_flags flags)
 165 {
 166         if (cpu_is_omap44xx())
 167                 omap4_hdmi_mux_pads(flags);
 168
 169         return 0;
 170 }
 171
 172 static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
 173 {
 174         if (cpu_is_omap44xx())
 175                 return omap4_dsi_mux_pads(dsi_id, lane_mask);
 176
 177         return 0;
 178 }
 179
 180 static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
 181 {
 182         if (cpu_is_omap44xx())
 183                 omap4_dsi_mux_pads(dsi_id, 0);
 184 }
 185
 186 int __init omap_display_init(struct omap_dss_board_info *board_data)
 187 {
 188         int r = 0;
 189         struct omap_hwmod *oh;
 190         struct platform_device *pdev;
 191         int i, oh_count;
 192         struct omap_display_platform_data pdata;
 193         const struct omap_dss_hwmod_data *curr_dss_hwmod;
 194
 195         memset(&pdata, 0, sizeof(pdata));
 196
 197         if (cpu_is_omap24xx()) {
 198                 curr_dss_hwmod = omap2_dss_hwmod_data;
 199                 oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
 200         } else if (cpu_is_omap34xx()) {
 201                 curr_dss_hwmod = omap3_dss_hwmod_data;
 202                 oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
 203         } else {
 204                 curr_dss_hwmod = omap4_dss_hwmod_data;
 205                 oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
 206         }
 207
 208         if (board_data->dsi_enable_pads == NULL)
 209                 board_data->dsi_enable_pads = omap_dsi_enable_pads;
 210         if (board_data->dsi_disable_pads == NULL)
 211                 board_data->dsi_disable_pads = omap_dsi_disable_pads;
 212
 213         pdata.board_data = board_data;
 214         pdata.board_data->get_context_loss_count =
 215                 omap_pm_get_dev_context_loss_count;
 216
 217         for (i = 0; i < oh_count; i++) {
 218                 oh = omap_hwmod_lookup(curr_dss_hwmod[i].oh_name);
 219                 if (!oh) {
 220                         pr_err("Could not look up %s\n",
 221                                 curr_dss_hwmod[i].oh_name);
 222                         return -ENODEV;
 223                 }
 224
 225                 pdev = omap_device_build(curr_dss_hwmod[i].dev_name,
 226                                 curr_dss_hwmod[i].id, oh, &pdata,
 227                                 sizeof(struct omap_display_platform_data),
 228                                 NULL, 0, 0);
 229
 230                 if (WARN((IS_ERR(pdev)), "Could not build omap_device for %s\n",
 231                                 curr_dss_hwmod[i].oh_name))
 232                         return -ENODEV;
 233         }
 234         omap_display_device.dev.platform_data = board_data;
 235
 236         r = platform_device_register(&omap_display_device);
 237         if (r < 0)
 238                 printk(KERN_ERR "Unable to register OMAP-Display device\n");
 239
 240         return r;
 241 }
 242
 243 static void dispc_disable_outputs(void)
 244 {
 245         u32 v, irq_mask = 0;
 246         bool lcd_en, digit_en, lcd2_en = false;
 247         int i;
 248         struct omap_dss_dispc_dev_attr *da;
 249         struct omap_hwmod *oh;
 250
 251         oh = omap_hwmod_lookup("dss_dispc");
 252         if (!oh) {
 253                 WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
 254                 return;
 255         }
 256
 257         if (!oh->dev_attr) {
 258                 pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
 259                 return;
 260         }
 261
 262         da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
 263
 264         /* store value of LCDENABLE and DIGITENABLE bits */
 265         v = omap_hwmod_read(oh, DISPC_CONTROL);
 266         lcd_en = v & LCD_EN_MASK;
 267         digit_en = v & DIGIT_EN_MASK;
 268
 269         /* store value of LCDENABLE for LCD2 */
 270         if (da->manager_count > 2) {
 271                 v = omap_hwmod_read(oh, DISPC_CONTROL2);
 272                 lcd2_en = v & LCD_EN_MASK;
 273         }
 274
 275         if (!(lcd_en | digit_en | lcd2_en))
 276                 return; /* no managers currently enabled */
 277
 278         /*
 279          * If any manager was enabled, we need to disable it before
 280          * DSS clocks are disabled or DISPC module is reset
 281          */
 282         if (lcd_en)
 283                 irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;
 284
 285         if (digit_en) {
 286                 if (da->has_framedonetv_irq) {
 287                         irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
 288                 } else {
 289                         irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
 290                                 1 << EVSYNC_ODD_IRQ_SHIFT;
 291                 }
 292         }
 293
 294         if (lcd2_en)
 295                 irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
 296
 297         /*
 298          * clear any previous FRAMEDONE, FRAMEDONETV,
 299          * EVSYNC_EVEN/ODD or FRAMEDONE2 interrupts
 300          */
 301         omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
 302
 303         /* disable LCD and TV managers */
 304         v = omap_hwmod_read(oh, DISPC_CONTROL);
 305         v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
 306         omap_hwmod_write(v, oh, DISPC_CONTROL);
 307
 308         /* disable LCD2 manager */
 309         if (da->manager_count > 2) {
 310                 v = omap_hwmod_read(oh, DISPC_CONTROL2);
 311                 v &= ~LCD_EN_MASK;
 312                 omap_hwmod_write(v, oh, DISPC_CONTROL2);
 313         }
 314
 315         i = 0;
 316         while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
 317                irq_mask) {
 318                 i++;
 319                 if (i > FRAMEDONE_IRQ_TIMEOUT) {
 320                         pr_err("didn't get FRAMEDONE1/2 or TV interrupt\n");
 321                         break;
 322                 }
 323                 mdelay(1);
 324         }
 325 }
 326
 327 #define MAX_MODULE_SOFTRESET_WAIT       10000
 328 int omap_dss_reset(struct omap_hwmod *oh)
 329 {
 330         struct omap_hwmod_opt_clk *oc;
 331         int c = 0;
 332         int i, r;
 333
 334         if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
 335                 pr_err("dss_core: hwmod data doesn't contain reset data\n");
 336                 return -EINVAL;
 337         }
 338
 339         for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
 340                 if (oc->_clk)
 341                         clk_enable(oc->_clk);
 342
 343         dispc_disable_outputs();
 344
 345         /* clear SDI registers */
 346         if (cpu_is_omap3430()) {
 347                 omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
 348                 omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
 349         }
 350
 351         /*
 352          * clear DSS_CONTROL register to switch DSS clock sources to
 353          * PRCM clock, if any
 354          */
 355         omap_hwmod_write(0x0, oh, DSS_CONTROL);
 356
 357         omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
 358                                 & SYSS_RESETDONE_MASK),
 359                         MAX_MODULE_SOFTRESET_WAIT, c);
 360
 361         if (c == MAX_MODULE_SOFTRESET_WAIT)
 362                 pr_warning("dss_core: waiting for reset to finish failed\n");
 363         else
 364                 pr_debug("dss_core: softreset done\n");
 365
 366         for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
 367                 if (oc->_clk)
 368                         clk_disable(oc->_clk);
 369
 370         r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
 371
 372         return r;
 373 }