arch/arm/mach-omap1/clock_data.c

   1 /*
   2  *  linux/arch/arm/mach-omap1/clock_data.c
   3  *
   4  *  Copyright (C) 2004 - 2005, 2009 Nokia corporation
   5  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
   6  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/clk.h>
  15 #include <linux/io.h>
  16
  17 #include <asm/mach-types.h>  /* for machine_is_* */
  18
  19 #include <plat/clock.h>
  20 #include <plat/cpu.h>
  21 #include <plat/clkdev_omap.h>
  22 #include <plat/usb.h>   /* for OTG_BASE */
  23
  24 #include "clock.h"
  25
  26 /*------------------------------------------------------------------------
  27  * Omap1 clocks
  28  *-------------------------------------------------------------------------*/
  29
  30 /* XXX is this necessary? */
  31 static struct clk dummy_ck = {
  32         .name   = "dummy",
  33         .ops    = &clkops_dummy,
  34         .flags  = RATE_FIXED,
  35 };
  36
  37 static struct clk ck_ref = {
  38         .name           = "ck_ref",
  39         .ops            = &clkops_null,
  40         .rate           = 12000000,
  41 };
  42
  43 static struct clk ck_dpll1 = {
  44         .name           = "ck_dpll1",
  45         .ops            = &clkops_null,
  46         .parent         = &ck_ref,
  47 };
  48
  49 /*
  50  * FIXME: This clock seems to be necessary but no-one has asked for its
  51  * activation.  [ FIX: SoSSI, SSR ]
  52  */
  53 static struct arm_idlect1_clk ck_dpll1out = {
  54         .clk = {
  55                 .name           = "ck_dpll1out",
  56                 .ops            = &clkops_generic,
  57                 .parent         = &ck_dpll1,
  58                 .flags          = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT |
  59                                   ENABLE_ON_INIT,
  60                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
  61                 .enable_bit     = EN_CKOUT_ARM,
  62                 .recalc         = &followparent_recalc,
  63         },
  64         .idlect_shift   = 12,
  65 };
  66
  67 static struct clk sossi_ck = {
  68         .name           = "ck_sossi",
  69         .ops            = &clkops_generic,
  70         .parent         = &ck_dpll1out.clk,
  71         .flags          = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
  72         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
  73         .enable_bit     = 16,
  74         .recalc         = &omap1_sossi_recalc,
  75         .set_rate       = &omap1_set_sossi_rate,
  76 };
  77
  78 static struct clk arm_ck = {
  79         .name           = "arm_ck",
  80         .ops            = &clkops_null,
  81         .parent         = &ck_dpll1,
  82         .rate_offset    = CKCTL_ARMDIV_OFFSET,
  83         .recalc         = &omap1_ckctl_recalc,
  84         .round_rate     = omap1_clk_round_rate_ckctl_arm,
  85         .set_rate       = omap1_clk_set_rate_ckctl_arm,
  86 };
  87
  88 static struct arm_idlect1_clk armper_ck = {
  89         .clk = {
  90                 .name           = "armper_ck",
  91                 .ops            = &clkops_generic,
  92                 .parent         = &ck_dpll1,
  93                 .flags          = CLOCK_IDLE_CONTROL,
  94                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
  95                 .enable_bit     = EN_PERCK,
  96                 .rate_offset    = CKCTL_PERDIV_OFFSET,
  97                 .recalc         = &omap1_ckctl_recalc,
  98                 .round_rate     = omap1_clk_round_rate_ckctl_arm,
  99                 .set_rate       = omap1_clk_set_rate_ckctl_arm,
 100         },
 101         .idlect_shift   = 2,
 102 };
 103
 104 /*
 105  * FIXME: This clock seems to be necessary but no-one has asked for its
 106  * activation.  [ GPIO code for 1510 ]
 107  */
 108 static struct clk arm_gpio_ck = {
 109         .name           = "arm_gpio_ck",
 110         .ops            = &clkops_generic,
 111         .parent         = &ck_dpll1,
 112         .flags          = ENABLE_ON_INIT,
 113         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 114         .enable_bit     = EN_GPIOCK,
 115         .recalc         = &followparent_recalc,
 116 };
 117
 118 static struct arm_idlect1_clk armxor_ck = {
 119         .clk = {
 120                 .name           = "armxor_ck",
 121                 .ops            = &clkops_generic,
 122                 .parent         = &ck_ref,
 123                 .flags          = CLOCK_IDLE_CONTROL,
 124                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 125                 .enable_bit     = EN_XORPCK,
 126                 .recalc         = &followparent_recalc,
 127         },
 128         .idlect_shift   = 1,
 129 };
 130
 131 static struct arm_idlect1_clk armtim_ck = {
 132         .clk = {
 133                 .name           = "armtim_ck",
 134                 .ops            = &clkops_generic,
 135                 .parent         = &ck_ref,
 136                 .flags          = CLOCK_IDLE_CONTROL,
 137                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 138                 .enable_bit     = EN_TIMCK,
 139                 .recalc         = &followparent_recalc,
 140         },
 141         .idlect_shift   = 9,
 142 };
 143
 144 static struct arm_idlect1_clk armwdt_ck = {
 145         .clk = {
 146                 .name           = "armwdt_ck",
 147                 .ops            = &clkops_generic,
 148                 .parent         = &ck_ref,
 149                 .flags          = CLOCK_IDLE_CONTROL,
 150                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 151                 .enable_bit     = EN_WDTCK,
 152                 .fixed_div      = 14,
 153                 .recalc         = &omap_fixed_divisor_recalc,
 154         },
 155         .idlect_shift   = 0,
 156 };
 157
 158 static struct clk arminth_ck16xx = {
 159         .name           = "arminth_ck",
 160         .ops            = &clkops_null,
 161         .parent         = &arm_ck,
 162         .recalc         = &followparent_recalc,
 163         /* Note: On 16xx the frequency can be divided by 2 by programming
 164          * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
 165          *
 166          * 1510 version is in TC clocks.
 167          */
 168 };
 169
 170 static struct clk dsp_ck = {
 171         .name           = "dsp_ck",
 172         .ops            = &clkops_generic,
 173         .parent         = &ck_dpll1,
 174         .enable_reg     = OMAP1_IO_ADDRESS(ARM_CKCTL),
 175         .enable_bit     = EN_DSPCK,
 176         .rate_offset    = CKCTL_DSPDIV_OFFSET,
 177         .recalc         = &omap1_ckctl_recalc,
 178         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 179         .set_rate       = omap1_clk_set_rate_ckctl_arm,
 180 };
 181
 182 static struct clk dspmmu_ck = {
 183         .name           = "dspmmu_ck",
 184         .ops            = &clkops_null,
 185         .parent         = &ck_dpll1,
 186         .rate_offset    = CKCTL_DSPMMUDIV_OFFSET,
 187         .recalc         = &omap1_ckctl_recalc,
 188         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 189         .set_rate       = omap1_clk_set_rate_ckctl_arm,
 190 };
 191
 192 static struct clk dspper_ck = {
 193         .name           = "dspper_ck",
 194         .ops            = &clkops_dspck,
 195         .parent         = &ck_dpll1,
 196         .enable_reg     = DSP_IDLECT2,
 197         .enable_bit     = EN_PERCK,
 198         .rate_offset    = CKCTL_PERDIV_OFFSET,
 199         .recalc         = &omap1_ckctl_recalc_dsp_domain,
 200         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 201         .set_rate       = &omap1_clk_set_rate_dsp_domain,
 202 };
 203
 204 static struct clk dspxor_ck = {
 205         .name           = "dspxor_ck",
 206         .ops            = &clkops_dspck,
 207         .parent         = &ck_ref,
 208         .enable_reg     = DSP_IDLECT2,
 209         .enable_bit     = EN_XORPCK,
 210         .recalc         = &followparent_recalc,
 211 };
 212
 213 static struct clk dsptim_ck = {
 214         .name           = "dsptim_ck",
 215         .ops            = &clkops_dspck,
 216         .parent         = &ck_ref,
 217         .enable_reg     = DSP_IDLECT2,
 218         .enable_bit     = EN_DSPTIMCK,
 219         .recalc         = &followparent_recalc,
 220 };
 221
 222 /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */
 223 static struct arm_idlect1_clk tc_ck = {
 224         .clk = {
 225                 .name           = "tc_ck",
 226                 .ops            = &clkops_null,
 227                 .parent         = &ck_dpll1,
 228                 .flags          = CLOCK_IDLE_CONTROL,
 229                 .rate_offset    = CKCTL_TCDIV_OFFSET,
 230                 .recalc         = &omap1_ckctl_recalc,
 231                 .round_rate     = omap1_clk_round_rate_ckctl_arm,
 232                 .set_rate       = omap1_clk_set_rate_ckctl_arm,
 233         },
 234         .idlect_shift   = 6,
 235 };
 236
 237 static struct clk arminth_ck1510 = {
 238         .name           = "arminth_ck",
 239         .ops            = &clkops_null,
 240         .parent         = &tc_ck.clk,
 241         .recalc         = &followparent_recalc,
 242         /* Note: On 1510 the frequency follows TC_CK
 243          *
 244          * 16xx version is in MPU clocks.
 245          */
 246 };
 247
 248 static struct clk tipb_ck = {
 249         /* No-idle controlled by "tc_ck" */
 250         .name           = "tipb_ck",
 251         .ops            = &clkops_null,
 252         .parent         = &tc_ck.clk,
 253         .recalc         = &followparent_recalc,
 254 };
 255
 256 static struct clk l3_ocpi_ck = {
 257         /* No-idle controlled by "tc_ck" */
 258         .name           = "l3_ocpi_ck",
 259         .ops            = &clkops_generic,
 260         .parent         = &tc_ck.clk,
 261         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
 262         .enable_bit     = EN_OCPI_CK,
 263         .recalc         = &followparent_recalc,
 264 };
 265
 266 static struct clk tc1_ck = {
 267         .name           = "tc1_ck",
 268         .ops            = &clkops_generic,
 269         .parent         = &tc_ck.clk,
 270         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
 271         .enable_bit     = EN_TC1_CK,
 272         .recalc         = &followparent_recalc,
 273 };
 274
 275 /*
 276  * FIXME: This clock seems to be necessary but no-one has asked for its
 277  * activation.  [ pm.c (SRAM), CCP, Camera ]
 278  */
 279 static struct clk tc2_ck = {
 280         .name           = "tc2_ck",
 281         .ops            = &clkops_generic,
 282         .parent         = &tc_ck.clk,
 283         .flags          = ENABLE_ON_INIT,
 284         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
 285         .enable_bit     = EN_TC2_CK,
 286         .recalc         = &followparent_recalc,
 287 };
 288
 289 static struct clk dma_ck = {
 290         /* No-idle controlled by "tc_ck" */
 291         .name           = "dma_ck",
 292         .ops            = &clkops_null,
 293         .parent         = &tc_ck.clk,
 294         .recalc         = &followparent_recalc,
 295 };
 296
 297 static struct clk dma_lcdfree_ck = {
 298         .name           = "dma_lcdfree_ck",
 299         .ops            = &clkops_null,
 300         .parent         = &tc_ck.clk,
 301         .recalc         = &followparent_recalc,
 302 };
 303
 304 static struct arm_idlect1_clk api_ck = {
 305         .clk = {
 306                 .name           = "api_ck",
 307                 .ops            = &clkops_generic,
 308                 .parent         = &tc_ck.clk,
 309                 .flags          = CLOCK_IDLE_CONTROL,
 310                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 311                 .enable_bit     = EN_APICK,
 312                 .recalc         = &followparent_recalc,
 313         },
 314         .idlect_shift   = 8,
 315 };
 316
 317 static struct arm_idlect1_clk lb_ck = {
 318         .clk = {
 319                 .name           = "lb_ck",
 320                 .ops            = &clkops_generic,
 321                 .parent         = &tc_ck.clk,
 322                 .flags          = CLOCK_IDLE_CONTROL,
 323                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 324                 .enable_bit     = EN_LBCK,
 325                 .recalc         = &followparent_recalc,
 326         },
 327         .idlect_shift   = 4,
 328 };
 329
 330 static struct clk rhea1_ck = {
 331         .name           = "rhea1_ck",
 332         .ops            = &clkops_null,
 333         .parent         = &tc_ck.clk,
 334         .recalc         = &followparent_recalc,
 335 };
 336
 337 static struct clk rhea2_ck = {
 338         .name           = "rhea2_ck",
 339         .ops            = &clkops_null,
 340         .parent         = &tc_ck.clk,
 341         .recalc         = &followparent_recalc,
 342 };
 343
 344 static struct clk lcd_ck_16xx = {
 345         .name           = "lcd_ck",
 346         .ops            = &clkops_generic,
 347         .parent         = &ck_dpll1,
 348         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 349         .enable_bit     = EN_LCDCK,
 350         .rate_offset    = CKCTL_LCDDIV_OFFSET,
 351         .recalc         = &omap1_ckctl_recalc,
 352         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 353         .set_rate       = omap1_clk_set_rate_ckctl_arm,
 354 };
 355
 356 static struct arm_idlect1_clk lcd_ck_1510 = {
 357         .clk = {
 358                 .name           = "lcd_ck",
 359                 .ops            = &clkops_generic,
 360                 .parent         = &ck_dpll1,
 361                 .flags          = CLOCK_IDLE_CONTROL,
 362                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 363                 .enable_bit     = EN_LCDCK,
 364                 .rate_offset    = CKCTL_LCDDIV_OFFSET,
 365                 .recalc         = &omap1_ckctl_recalc,
 366                 .round_rate     = omap1_clk_round_rate_ckctl_arm,
 367                 .set_rate       = omap1_clk_set_rate_ckctl_arm,
 368         },
 369         .idlect_shift   = 3,
 370 };
 371
 372 static struct clk uart1_1510 = {
 373         .name           = "uart1_ck",
 374         .ops            = &clkops_null,
 375         /* Direct from ULPD, no real parent */
 376         .parent         = &armper_ck.clk,
 377         .rate           = 12000000,
 378         .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 379         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 380         .enable_bit     = 29,   /* Chooses between 12MHz and 48MHz */
 381         .set_rate       = &omap1_set_uart_rate,
 382         .recalc         = &omap1_uart_recalc,
 383 };
 384
 385 static struct uart_clk uart1_16xx = {
 386         .clk    = {
 387                 .name           = "uart1_ck",
 388                 .ops            = &clkops_uart,
 389                 /* Direct from ULPD, no real parent */
 390                 .parent         = &armper_ck.clk,
 391                 .rate           = 48000000,
 392                 .flags          = RATE_FIXED | ENABLE_REG_32BIT |
 393                                   CLOCK_NO_IDLE_PARENT,
 394                 .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 395                 .enable_bit     = 29,
 396         },
 397         .sysc_addr      = 0xfffb0054,
 398 };
 399
 400 static struct clk uart2_ck = {
 401         .name           = "uart2_ck",
 402         .ops            = &clkops_null,
 403         /* Direct from ULPD, no real parent */
 404         .parent         = &armper_ck.clk,
 405         .rate           = 12000000,
 406         .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 407         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 408         .enable_bit     = 30,   /* Chooses between 12MHz and 48MHz */
 409         .set_rate       = &omap1_set_uart_rate,
 410         .recalc         = &omap1_uart_recalc,
 411 };
 412
 413 static struct clk uart3_1510 = {
 414         .name           = "uart3_ck",
 415         .ops            = &clkops_null,
 416         /* Direct from ULPD, no real parent */
 417         .parent         = &armper_ck.clk,
 418         .rate           = 12000000,
 419         .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 420         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 421         .enable_bit     = 31,   /* Chooses between 12MHz and 48MHz */
 422         .set_rate       = &omap1_set_uart_rate,
 423         .recalc         = &omap1_uart_recalc,
 424 };
 425
 426 static struct uart_clk uart3_16xx = {
 427         .clk    = {
 428                 .name           = "uart3_ck",
 429                 .ops            = &clkops_uart,
 430                 /* Direct from ULPD, no real parent */
 431                 .parent         = &armper_ck.clk,
 432                 .rate           = 48000000,
 433                 .flags          = RATE_FIXED | ENABLE_REG_32BIT |
 434                                   CLOCK_NO_IDLE_PARENT,
 435                 .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 436                 .enable_bit     = 31,
 437         },
 438         .sysc_addr      = 0xfffb9854,
 439 };
 440
 441 static struct clk usb_clko = {  /* 6 MHz output on W4_USB_CLKO */
 442         .name           = "usb_clko",
 443         .ops            = &clkops_generic,
 444         /* Direct from ULPD, no parent */
 445         .rate           = 6000000,
 446         .flags          = RATE_FIXED | ENABLE_REG_32BIT,
 447         .enable_reg     = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
 448         .enable_bit     = USB_MCLK_EN_BIT,
 449 };
 450
 451 static struct clk usb_hhc_ck1510 = {
 452         .name           = "usb_hhc_ck",
 453         .ops            = &clkops_generic,
 454         /* Direct from ULPD, no parent */
 455         .rate           = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
 456         .flags          = RATE_FIXED | ENABLE_REG_32BIT,
 457         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 458         .enable_bit     = USB_HOST_HHC_UHOST_EN,
 459 };
 460
 461 static struct clk usb_hhc_ck16xx = {
 462         .name           = "usb_hhc_ck",
 463         .ops            = &clkops_generic,
 464         /* Direct from ULPD, no parent */
 465         .rate           = 48000000,
 466         /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
 467         .flags          = RATE_FIXED | ENABLE_REG_32BIT,
 468         .enable_reg     = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
 469         .enable_bit     = 8 /* UHOST_EN */,
 470 };
 471
 472 static struct clk usb_dc_ck = {
 473         .name           = "usb_dc_ck",
 474         .ops            = &clkops_generic,
 475         /* Direct from ULPD, no parent */
 476         .rate           = 48000000,
 477         .flags          = RATE_FIXED,
 478         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 479         .enable_bit     = 4,
 480 };
 481
 482 static struct clk usb_dc_ck7xx = {
 483         .name           = "usb_dc_ck",
 484         .ops            = &clkops_generic,
 485         /* Direct from ULPD, no parent */
 486         .rate           = 48000000,
 487         .flags          = RATE_FIXED,
 488         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 489         .enable_bit     = 8,
 490 };
 491
 492 static struct clk mclk_1510 = {
 493         .name           = "mclk",
 494         .ops            = &clkops_generic,
 495         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 496         .rate           = 12000000,
 497         .flags          = RATE_FIXED,
 498         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 499         .enable_bit     = 6,
 500 };
 501
 502 static struct clk mclk_16xx = {
 503         .name           = "mclk",
 504         .ops            = &clkops_generic,
 505         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 506         .enable_reg     = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
 507         .enable_bit     = COM_ULPD_PLL_CLK_REQ,
 508         .set_rate       = &omap1_set_ext_clk_rate,
 509         .round_rate     = &omap1_round_ext_clk_rate,
 510         .init           = &omap1_init_ext_clk,
 511 };
 512
 513 static struct clk bclk_1510 = {
 514         .name           = "bclk",
 515         .ops            = &clkops_generic,
 516         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 517         .rate           = 12000000,
 518         .flags          = RATE_FIXED,
 519 };
 520
 521 static struct clk bclk_16xx = {
 522         .name           = "bclk",
 523         .ops            = &clkops_generic,
 524         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 525         .enable_reg     = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
 526         .enable_bit     = SWD_ULPD_PLL_CLK_REQ,
 527         .set_rate       = &omap1_set_ext_clk_rate,
 528         .round_rate     = &omap1_round_ext_clk_rate,
 529         .init           = &omap1_init_ext_clk,
 530 };
 531
 532 static struct clk mmc1_ck = {
 533         .name           = "mmc_ck",
 534         .ops            = &clkops_generic,
 535         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 536         .parent         = &armper_ck.clk,
 537         .rate           = 48000000,
 538         .flags          = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 539         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 540         .enable_bit     = 23,
 541 };
 542
 543 static struct clk mmc2_ck = {
 544         .name           = "mmc_ck",
 545         .id             = 1,
 546         .ops            = &clkops_generic,
 547         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 548         .parent         = &armper_ck.clk,
 549         .rate           = 48000000,
 550         .flags          = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 551         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 552         .enable_bit     = 20,
 553 };
 554
 555 static struct clk mmc3_ck = {
 556         .name           = "mmc_ck",
 557         .id             = 2,
 558         .ops            = &clkops_generic,
 559         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 560         .parent         = &armper_ck.clk,
 561         .rate           = 48000000,
 562         .flags          = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 563         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 564         .enable_bit     = 12,
 565 };
 566
 567 static struct clk virtual_ck_mpu = {
 568         .name           = "mpu",
 569         .ops            = &clkops_null,
 570         .parent         = &arm_ck, /* Is smarter alias for */
 571         .recalc         = &followparent_recalc,
 572         .set_rate       = &omap1_select_table_rate,
 573         .round_rate     = &omap1_round_to_table_rate,
 574 };
 575
 576 /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
 577 remains active during MPU idle whenever this is enabled */
 578 static struct clk i2c_fck = {
 579         .name           = "i2c_fck",
 580         .id             = 1,
 581         .ops            = &clkops_null,
 582         .flags          = CLOCK_NO_IDLE_PARENT,
 583         .parent         = &armxor_ck.clk,
 584         .recalc         = &followparent_recalc,
 585 };
 586
 587 static struct clk i2c_ick = {
 588         .name           = "i2c_ick",
 589         .id             = 1,
 590         .ops            = &clkops_null,
 591         .flags          = CLOCK_NO_IDLE_PARENT,
 592         .parent         = &armper_ck.clk,
 593         .recalc         = &followparent_recalc,
 594 };
 595
 596 /*
 597  * clkdev integration
 598  */
 599
 600 static struct omap_clk omap_clks[] = {
 601         /* non-ULPD clocks */
 602         CLK(NULL,       "ck_ref",       &ck_ref,        CK_16XX | CK_1510 | CK_310 | CK_7XX),
 603         CLK(NULL,       "ck_dpll1",     &ck_dpll1,      CK_16XX | CK_1510 | CK_310 | CK_7XX),
 604         /* CK_GEN1 clocks */
 605         CLK(NULL,       "ck_dpll1out",  &ck_dpll1out.clk, CK_16XX),
 606         CLK(NULL,       "ck_sossi",     &sossi_ck,      CK_16XX),
 607         CLK(NULL,       "arm_ck",       &arm_ck,        CK_16XX | CK_1510 | CK_310),
 608         CLK(NULL,       "armper_ck",    &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
 609         CLK(NULL,       "arm_gpio_ck",  &arm_gpio_ck,   CK_1510 | CK_310),
 610         CLK(NULL,       "armxor_ck",    &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
 611         CLK(NULL,       "armtim_ck",    &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
 612         CLK("omap_wdt", "fck",          &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
 613         CLK("omap_wdt", "ick",          &armper_ck.clk, CK_16XX),
 614         CLK("omap_wdt", "ick",          &dummy_ck,      CK_1510 | CK_310),
 615         CLK(NULL,       "arminth_ck",   &arminth_ck1510, CK_1510 | CK_310),
 616         CLK(NULL,       "arminth_ck",   &arminth_ck16xx, CK_16XX),
 617         /* CK_GEN2 clocks */
 618         CLK(NULL,       "dsp_ck",       &dsp_ck,        CK_16XX | CK_1510 | CK_310),
 619         CLK(NULL,       "dspmmu_ck",    &dspmmu_ck,     CK_16XX | CK_1510 | CK_310),
 620         CLK(NULL,       "dspper_ck",    &dspper_ck,     CK_16XX | CK_1510 | CK_310),
 621         CLK(NULL,       "dspxor_ck",    &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
 622         CLK(NULL,       "dsptim_ck",    &dsptim_ck,     CK_16XX | CK_1510 | CK_310),
 623         /* CK_GEN3 clocks */
 624         CLK(NULL,       "tc_ck",        &tc_ck.clk,     CK_16XX | CK_1510 | CK_310 | CK_7XX),
 625         CLK(NULL,       "tipb_ck",      &tipb_ck,       CK_1510 | CK_310),
 626         CLK(NULL,       "l3_ocpi_ck",   &l3_ocpi_ck,    CK_16XX | CK_7XX),
 627         CLK(NULL,       "tc1_ck",       &tc1_ck,        CK_16XX),
 628         CLK(NULL,       "tc2_ck",       &tc2_ck,        CK_16XX),
 629         CLK(NULL,       "dma_ck",       &dma_ck,        CK_16XX | CK_1510 | CK_310),
 630         CLK(NULL,       "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
 631         CLK(NULL,       "api_ck",       &api_ck.clk,    CK_16XX | CK_1510 | CK_310 | CK_7XX),
 632         CLK(NULL,       "lb_ck",        &lb_ck.clk,     CK_1510 | CK_310),
 633         CLK(NULL,       "rhea1_ck",     &rhea1_ck,      CK_16XX),
 634         CLK(NULL,       "rhea2_ck",     &rhea2_ck,      CK_16XX),
 635         CLK(NULL,       "lcd_ck",       &lcd_ck_16xx,   CK_16XX | CK_7XX),
 636         CLK(NULL,       "lcd_ck",       &lcd_ck_1510.clk, CK_1510 | CK_310),
 637         /* ULPD clocks */
 638         CLK(NULL,       "uart1_ck",     &uart1_1510,    CK_1510 | CK_310),
 639         CLK(NULL,       "uart1_ck",     &uart1_16xx.clk, CK_16XX),
 640         CLK(NULL,       "uart2_ck",     &uart2_ck,      CK_16XX | CK_1510 | CK_310),
 641         CLK(NULL,       "uart3_ck",     &uart3_1510,    CK_1510 | CK_310),
 642         CLK(NULL,       "uart3_ck",     &uart3_16xx.clk, CK_16XX),
 643         CLK(NULL,       "usb_clko",     &usb_clko,      CK_16XX | CK_1510 | CK_310),
 644         CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck1510, CK_1510 | CK_310),
 645         CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck16xx, CK_16XX),
 646         CLK(NULL,       "usb_dc_ck",    &usb_dc_ck,     CK_16XX),
 647         CLK(NULL,       "usb_dc_ck",    &usb_dc_ck7xx,  CK_7XX),
 648         CLK(NULL,       "mclk",         &mclk_1510,     CK_1510 | CK_310),
 649         CLK(NULL,       "mclk",         &mclk_16xx,     CK_16XX),
 650         CLK(NULL,       "bclk",         &bclk_1510,     CK_1510 | CK_310),
 651         CLK(NULL,       "bclk",         &bclk_16xx,     CK_16XX),
 652         CLK("mmci-omap.0", "fck",       &mmc1_ck,       CK_16XX | CK_1510 | CK_310),
 653         CLK("mmci-omap.0", "fck",       &mmc3_ck,       CK_7XX),
 654         CLK("mmci-omap.0", "ick",       &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
 655         CLK("mmci-omap.1", "fck",       &mmc2_ck,       CK_16XX),
 656         CLK("mmci-omap.1", "ick",       &armper_ck.clk, CK_16XX),
 657         /* Virtual clocks */
 658         CLK(NULL,       "mpu",          &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
 659         CLK("i2c_omap.1", "fck",        &i2c_fck,       CK_16XX | CK_1510 | CK_310 | CK_7XX),
 660         CLK("i2c_omap.1", "ick",        &i2c_ick,       CK_16XX),
 661         CLK("i2c_omap.1", "ick",        &dummy_ck,      CK_1510 | CK_310 | CK_7XX),
 662         CLK("omap1_spi100k.1", "fck",   &dummy_ck,      CK_7XX),
 663         CLK("omap1_spi100k.1", "ick",   &dummy_ck,      CK_7XX),
 664         CLK("omap1_spi100k.2", "fck",   &dummy_ck,      CK_7XX),
 665         CLK("omap1_spi100k.2", "ick",   &dummy_ck,      CK_7XX),
 666         CLK("omap_uwire", "fck",        &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
 667         CLK("omap-mcbsp.1", "ick",      &dspper_ck,     CK_16XX),
 668         CLK("omap-mcbsp.1", "ick",      &dummy_ck,      CK_1510 | CK_310),
 669         CLK("omap-mcbsp.2", "ick",      &armper_ck.clk, CK_16XX),
 670         CLK("omap-mcbsp.2", "ick",      &dummy_ck,      CK_1510 | CK_310),
 671         CLK("omap-mcbsp.3", "ick",      &dspper_ck,     CK_16XX),
 672         CLK("omap-mcbsp.3", "ick",      &dummy_ck,      CK_1510 | CK_310),
 673         CLK("omap-mcbsp.1", "fck",      &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
 674         CLK("omap-mcbsp.2", "fck",      &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
 675         CLK("omap-mcbsp.3", "fck",      &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
 676 };
 677
 678 /*
 679  * init
 680  */
 681
 682 static struct clk_functions omap1_clk_functions = {
 683         .clk_enable             = omap1_clk_enable,
 684         .clk_disable            = omap1_clk_disable,
 685         .clk_round_rate         = omap1_clk_round_rate,
 686         .clk_set_rate           = omap1_clk_set_rate,
 687         .clk_disable_unused     = omap1_clk_disable_unused,
 688 };
 689
 690 int __init omap1_clk_init(void)
 691 {
 692         struct omap_clk *c;
 693         const struct omap_clock_config *info;
 694         int crystal_type = 0; /* Default 12 MHz */
 695         u32 reg, cpu_mask;
 696
 697 #ifdef CONFIG_DEBUG_LL
 698         /*
 699          * Resets some clocks that may be left on from bootloader,
 700          * but leaves serial clocks on.
 701          */
 702         omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
 703 #endif
 704
 705         /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
 706         reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
 707         omap_writew(reg, SOFT_REQ_REG);
 708         if (!cpu_is_omap15xx())
 709                 omap_writew(0, SOFT_REQ_REG2);
 710
 711         clk_init(&omap1_clk_functions);
 712
 713         /* By default all idlect1 clocks are allowed to idle */
 714         arm_idlect1_mask = ~0;
 715
 716         for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
 717                 clk_preinit(c->lk.clk);
 718
 719         cpu_mask = 0;
 720         if (cpu_is_omap16xx())
 721                 cpu_mask |= CK_16XX;
 722         if (cpu_is_omap1510())
 723                 cpu_mask |= CK_1510;
 724         if (cpu_is_omap7xx())
 725                 cpu_mask |= CK_7XX;
 726         if (cpu_is_omap310())
 727                 cpu_mask |= CK_310;
 728
 729         for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
 730                 if (c->cpu & cpu_mask) {
 731                         clkdev_add(&c->lk);
 732                         clk_register(c->lk.clk);
 733                 }
 734
 735         /* Pointers to these clocks are needed by code in clock.c */
 736         api_ck_p = clk_get(NULL, "api_ck");
 737         ck_dpll1_p = clk_get(NULL, "ck_dpll1");
 738         ck_ref_p = clk_get(NULL, "ck_ref");
 739
 740         info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
 741         if (info != NULL) {
 742                 if (!cpu_is_omap15xx())
 743                         crystal_type = info->system_clock_type;
 744         }
 745
 746 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
 747         ck_ref.rate = 13000000;
 748 #elif defined(CONFIG_ARCH_OMAP16XX)
 749         if (crystal_type == 2)
 750                 ck_ref.rate = 19200000;
 751 #endif
 752
 753         pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: "
 754                 "0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
 755                 omap_readw(ARM_CKCTL));
 756
 757         /* We want to be in syncronous scalable mode */
 758         omap_writew(0x1000, ARM_SYSST);
 759
 760 #ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
 761         /* Use values set by bootloader. Determine PLL rate and recalculate
 762          * dependent clocks as if kernel had changed PLL or divisors.
 763          */
 764         {
 765                 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
 766
 767                 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
 768                 if (pll_ctl_val & 0x10) {
 769                         /* PLL enabled, apply multiplier and divisor */
 770                         if (pll_ctl_val & 0xf80)
 771                                 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
 772                         ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
 773                 } else {
 774                         /* PLL disabled, apply bypass divisor */
 775                         switch (pll_ctl_val & 0xc) {
 776                         case 0:
 777                                 break;
 778                         case 0x4:
 779                                 ck_dpll1.rate /= 2;
 780                                 break;
 781                         default:
 782                                 ck_dpll1.rate /= 4;
 783                                 break;
 784                         }
 785                 }
 786         }
 787 #else
 788         /* Find the highest supported frequency and enable it */
 789         if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
 790                 printk(KERN_ERR "System frequencies not set. Check your config.\n");
 791                 /* Guess sane values (60MHz) */
 792                 omap_writew(0x2290, DPLL_CTL);
 793                 omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL);
 794                 ck_dpll1.rate = 60000000;
 795         }
 796 #endif
 797         propagate_rate(&ck_dpll1);
 798         /* Cache rates for clocks connected to ck_ref (not dpll1) */
 799         propagate_rate(&ck_ref);
 800         printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
 801                 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
 802                ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
 803                ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
 804                arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
 805
 806 #if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
 807         /* Select slicer output as OMAP input clock */
 808         omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, OMAP7XX_PCC_UPLD_CTRL);
 809 #endif
 810
 811         /* Amstrad Delta wants BCLK high when inactive */
 812         if (machine_is_ams_delta())
 813                 omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
 814                                 (1 << SDW_MCLK_INV_BIT),
 815                                 ULPD_CLOCK_CTRL);
 816
 817         /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
 818         /* (on 730, bit 13 must not be cleared) */
 819         if (cpu_is_omap7xx())
 820                 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
 821         else
 822                 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
 823
 824         /* Put DSP/MPUI into reset until needed */
 825         omap_writew(0, ARM_RSTCT1);
 826         omap_writew(1, ARM_RSTCT2);
 827         omap_writew(0x400, ARM_IDLECT1);
 828
 829         /*
 830          * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
 831          * of the ARM_IDLECT2 register must be set to zero. The power-on
 832          * default value of this bit is one.
 833          */
 834         omap_writew(0x0000, ARM_IDLECT2);       /* Turn LCD clock off also */
 835
 836         /*
 837          * Only enable those clocks we will need, let the drivers
 838          * enable other clocks as necessary
 839          */
 840         clk_enable(&armper_ck.clk);
 841         clk_enable(&armxor_ck.clk);
 842         clk_enable(&armtim_ck.clk); /* This should be done by timer code */
 843
 844         if (cpu_is_omap15xx())
 845                 clk_enable(&arm_gpio_ck);
 846
 847         return 0;
 848 }