2 * linux/arch/arm/mach-omap1/clock.h
4 * Copyright (C) 2004 - 2005 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H
14 #define __ARCH_ARM_MACH_OMAP1_CLOCK_H
16 static void omap1_ckctl_recalc(struct clk * clk);
17 static void omap1_watchdog_recalc(struct clk * clk);
18 static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
19 static void omap1_sossi_recalc(struct clk *clk);
20 static void omap1_ckctl_recalc_dsp_domain(struct clk * clk);
21 static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate);
22 static int omap1_set_uart_rate(struct clk * clk, unsigned long rate);
23 static void omap1_uart_recalc(struct clk * clk);
24 static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate);
25 static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate);
26 static void omap1_init_ext_clk(struct clk * clk);
27 static int omap1_select_table_rate(struct clk * clk, unsigned long rate);
28 static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate);
30 static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate);
31 static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate);
36 unsigned long pll_rate;
43 unsigned long sysc_addr;
46 /* Provide a method for preventing idling some ARM IDLECT clocks */
47 struct arm_idlect1_clk {
49 unsigned long no_idle_count;
53 /* ARM_CKCTL bit shifts */
54 #define CKCTL_PERDIV_OFFSET 0
55 #define CKCTL_LCDDIV_OFFSET 2
56 #define CKCTL_ARMDIV_OFFSET 4
57 #define CKCTL_DSPDIV_OFFSET 6
58 #define CKCTL_TCDIV_OFFSET 8
59 #define CKCTL_DSPMMUDIV_OFFSET 10
60 /*#define ARM_TIMXO 12*/
62 /*#define ARM_INTHCK_SEL 14*/ /* Divide-by-2 for mpu inth_ck */
63 /* DSP_CKCTL bit shifts */
64 #define CKCTL_DSPPERDIV_OFFSET 0
66 /* ARM_IDLECT2 bit shifts */
71 #define EN_LBCK 4 /* Not on 1610/1710 */
72 /*#define EN_HSABCK 5*/
76 #define EN_GPIOCK 9 /* Not on 1610/1710 */
77 /*#define EN_LBFREECK 10*/
78 #define EN_CKOUT_ARM 11
80 /* ARM_IDLECT3 bit shifts */
85 /* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */
88 /* Various register defines for clock controls scattered around OMAP chip */
89 #define SDW_MCLK_INV_BIT 2 /* In ULPD_CLKC_CTRL */
90 #define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */
91 #define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */
92 #define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */
93 #define COM_ULPD_PLL_CLK_REQ 1 /* In COM_CLK_DIV_CTRL_SEL */
94 #define SWD_CLK_DIV_CTRL_SEL 0xfffe0874
95 #define COM_CLK_DIV_CTRL_SEL 0xfffe0878
96 #define SOFT_REQ_REG 0xfffe0834
97 #define SOFT_REQ_REG2 0xfffe0880
99 /*-------------------------------------------------------------------------
100 * Omap1 MPU rate table
101 *-------------------------------------------------------------------------*/
102 static struct mpu_rate rate_table[] = {
103 /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
104 * NOTE: Comment order here is different from bits in CKCTL value:
105 * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
107 #if defined(CONFIG_OMAP_ARM_216MHZ)
108 { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
110 #if defined(CONFIG_OMAP_ARM_195MHZ)
111 { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
113 #if defined(CONFIG_OMAP_ARM_192MHZ)
114 { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
115 { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
116 { 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
117 { 48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */
118 { 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
120 #if defined(CONFIG_OMAP_ARM_182MHZ)
121 { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
123 #if defined(CONFIG_OMAP_ARM_168MHZ)
124 { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
126 #if defined(CONFIG_OMAP_ARM_150MHZ)
127 { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
129 #if defined(CONFIG_OMAP_ARM_120MHZ)
130 { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
132 #if defined(CONFIG_OMAP_ARM_96MHZ)
133 { 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
135 #if defined(CONFIG_OMAP_ARM_60MHZ)
136 { 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
138 #if defined(CONFIG_OMAP_ARM_30MHZ)
139 { 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
144 /*-------------------------------------------------------------------------
146 *-------------------------------------------------------------------------*/
148 static struct clk ck_ref = {
154 static struct clk ck_dpll1 = {
158 .flags = RATE_PROPAGATES,
161 static struct arm_idlect1_clk ck_dpll1out = {
163 .name = "ck_dpll1out",
164 .ops = &clkops_generic,
166 .flags = CLOCK_IDLE_CONTROL |
167 ENABLE_REG_32BIT | RATE_PROPAGATES,
168 .enable_reg = (void __iomem *)ARM_IDLECT2,
169 .enable_bit = EN_CKOUT_ARM,
170 .recalc = &followparent_recalc,
175 static struct clk sossi_ck = {
177 .ops = &clkops_generic,
178 .parent = &ck_dpll1out.clk,
179 .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
180 .enable_reg = (void __iomem *)MOD_CONF_CTRL_1,
182 .recalc = &omap1_sossi_recalc,
183 .set_rate = &omap1_set_sossi_rate,
186 static struct clk arm_ck = {
190 .flags = RATE_PROPAGATES,
191 .rate_offset = CKCTL_ARMDIV_OFFSET,
192 .recalc = &omap1_ckctl_recalc,
193 .round_rate = omap1_clk_round_rate_ckctl_arm,
194 .set_rate = omap1_clk_set_rate_ckctl_arm,
197 static struct arm_idlect1_clk armper_ck = {
200 .ops = &clkops_generic,
202 .flags = CLOCK_IDLE_CONTROL,
203 .enable_reg = (void __iomem *)ARM_IDLECT2,
204 .enable_bit = EN_PERCK,
205 .rate_offset = CKCTL_PERDIV_OFFSET,
206 .recalc = &omap1_ckctl_recalc,
207 .round_rate = omap1_clk_round_rate_ckctl_arm,
208 .set_rate = omap1_clk_set_rate_ckctl_arm,
213 static struct clk arm_gpio_ck = {
214 .name = "arm_gpio_ck",
215 .ops = &clkops_generic,
217 .enable_reg = (void __iomem *)ARM_IDLECT2,
218 .enable_bit = EN_GPIOCK,
219 .recalc = &followparent_recalc,
222 static struct arm_idlect1_clk armxor_ck = {
225 .ops = &clkops_generic,
227 .flags = CLOCK_IDLE_CONTROL,
228 .enable_reg = (void __iomem *)ARM_IDLECT2,
229 .enable_bit = EN_XORPCK,
230 .recalc = &followparent_recalc,
235 static struct arm_idlect1_clk armtim_ck = {
238 .ops = &clkops_generic,
240 .flags = CLOCK_IDLE_CONTROL,
241 .enable_reg = (void __iomem *)ARM_IDLECT2,
242 .enable_bit = EN_TIMCK,
243 .recalc = &followparent_recalc,
248 static struct arm_idlect1_clk armwdt_ck = {
251 .ops = &clkops_generic,
253 .flags = CLOCK_IDLE_CONTROL,
254 .enable_reg = (void __iomem *)ARM_IDLECT2,
255 .enable_bit = EN_WDTCK,
256 .recalc = &omap1_watchdog_recalc,
261 static struct clk arminth_ck16xx = {
262 .name = "arminth_ck",
265 .recalc = &followparent_recalc,
266 /* Note: On 16xx the frequency can be divided by 2 by programming
267 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
269 * 1510 version is in TC clocks.
273 static struct clk dsp_ck = {
275 .ops = &clkops_generic,
277 .enable_reg = (void __iomem *)ARM_CKCTL,
278 .enable_bit = EN_DSPCK,
279 .rate_offset = CKCTL_DSPDIV_OFFSET,
280 .recalc = &omap1_ckctl_recalc,
281 .round_rate = omap1_clk_round_rate_ckctl_arm,
282 .set_rate = omap1_clk_set_rate_ckctl_arm,
285 static struct clk dspmmu_ck = {
289 .rate_offset = CKCTL_DSPMMUDIV_OFFSET,
290 .recalc = &omap1_ckctl_recalc,
291 .round_rate = omap1_clk_round_rate_ckctl_arm,
292 .set_rate = omap1_clk_set_rate_ckctl_arm,
295 static struct clk dspper_ck = {
297 .ops = &clkops_dspck,
299 .flags = VIRTUAL_IO_ADDRESS,
300 .enable_reg = DSP_IDLECT2,
301 .enable_bit = EN_PERCK,
302 .rate_offset = CKCTL_PERDIV_OFFSET,
303 .recalc = &omap1_ckctl_recalc_dsp_domain,
304 .round_rate = omap1_clk_round_rate_ckctl_arm,
305 .set_rate = &omap1_clk_set_rate_dsp_domain,
308 static struct clk dspxor_ck = {
310 .ops = &clkops_dspck,
312 .flags = VIRTUAL_IO_ADDRESS,
313 .enable_reg = DSP_IDLECT2,
314 .enable_bit = EN_XORPCK,
315 .recalc = &followparent_recalc,
318 static struct clk dsptim_ck = {
320 .ops = &clkops_dspck,
322 .flags = VIRTUAL_IO_ADDRESS,
323 .enable_reg = DSP_IDLECT2,
324 .enable_bit = EN_DSPTIMCK,
325 .recalc = &followparent_recalc,
328 /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */
329 static struct arm_idlect1_clk tc_ck = {
334 .flags = RATE_PROPAGATES | CLOCK_IDLE_CONTROL,
335 .rate_offset = CKCTL_TCDIV_OFFSET,
336 .recalc = &omap1_ckctl_recalc,
337 .round_rate = omap1_clk_round_rate_ckctl_arm,
338 .set_rate = omap1_clk_set_rate_ckctl_arm,
343 static struct clk arminth_ck1510 = {
344 .name = "arminth_ck",
346 .parent = &tc_ck.clk,
347 .recalc = &followparent_recalc,
348 /* Note: On 1510 the frequency follows TC_CK
350 * 16xx version is in MPU clocks.
354 static struct clk tipb_ck = {
355 /* No-idle controlled by "tc_ck" */
358 .parent = &tc_ck.clk,
359 .recalc = &followparent_recalc,
362 static struct clk l3_ocpi_ck = {
363 /* No-idle controlled by "tc_ck" */
364 .name = "l3_ocpi_ck",
365 .ops = &clkops_generic,
366 .parent = &tc_ck.clk,
367 .enable_reg = (void __iomem *)ARM_IDLECT3,
368 .enable_bit = EN_OCPI_CK,
369 .recalc = &followparent_recalc,
372 static struct clk tc1_ck = {
374 .ops = &clkops_generic,
375 .parent = &tc_ck.clk,
376 .enable_reg = (void __iomem *)ARM_IDLECT3,
377 .enable_bit = EN_TC1_CK,
378 .recalc = &followparent_recalc,
381 static struct clk tc2_ck = {
383 .ops = &clkops_generic,
384 .parent = &tc_ck.clk,
385 .enable_reg = (void __iomem *)ARM_IDLECT3,
386 .enable_bit = EN_TC2_CK,
387 .recalc = &followparent_recalc,
390 static struct clk dma_ck = {
391 /* No-idle controlled by "tc_ck" */
394 .parent = &tc_ck.clk,
395 .recalc = &followparent_recalc,
398 static struct clk dma_lcdfree_ck = {
399 .name = "dma_lcdfree_ck",
401 .parent = &tc_ck.clk,
402 .recalc = &followparent_recalc,
405 static struct arm_idlect1_clk api_ck = {
408 .ops = &clkops_generic,
409 .parent = &tc_ck.clk,
410 .flags = CLOCK_IDLE_CONTROL,
411 .enable_reg = (void __iomem *)ARM_IDLECT2,
412 .enable_bit = EN_APICK,
413 .recalc = &followparent_recalc,
418 static struct arm_idlect1_clk lb_ck = {
421 .ops = &clkops_generic,
422 .parent = &tc_ck.clk,
423 .flags = CLOCK_IDLE_CONTROL,
424 .enable_reg = (void __iomem *)ARM_IDLECT2,
425 .enable_bit = EN_LBCK,
426 .recalc = &followparent_recalc,
431 static struct clk rhea1_ck = {
434 .parent = &tc_ck.clk,
435 .recalc = &followparent_recalc,
438 static struct clk rhea2_ck = {
441 .parent = &tc_ck.clk,
442 .recalc = &followparent_recalc,
445 static struct clk lcd_ck_16xx = {
447 .ops = &clkops_generic,
449 .enable_reg = (void __iomem *)ARM_IDLECT2,
450 .enable_bit = EN_LCDCK,
451 .rate_offset = CKCTL_LCDDIV_OFFSET,
452 .recalc = &omap1_ckctl_recalc,
453 .round_rate = omap1_clk_round_rate_ckctl_arm,
454 .set_rate = omap1_clk_set_rate_ckctl_arm,
457 static struct arm_idlect1_clk lcd_ck_1510 = {
460 .ops = &clkops_generic,
462 .flags = CLOCK_IDLE_CONTROL,
463 .enable_reg = (void __iomem *)ARM_IDLECT2,
464 .enable_bit = EN_LCDCK,
465 .rate_offset = CKCTL_LCDDIV_OFFSET,
466 .recalc = &omap1_ckctl_recalc,
467 .round_rate = omap1_clk_round_rate_ckctl_arm,
468 .set_rate = omap1_clk_set_rate_ckctl_arm,
473 static struct clk uart1_1510 = {
476 /* Direct from ULPD, no real parent */
477 .parent = &armper_ck.clk,
479 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
480 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
481 .enable_bit = 29, /* Chooses between 12MHz and 48MHz */
482 .set_rate = &omap1_set_uart_rate,
483 .recalc = &omap1_uart_recalc,
486 static struct uart_clk uart1_16xx = {
490 /* Direct from ULPD, no real parent */
491 .parent = &armper_ck.clk,
493 .flags = RATE_FIXED | ENABLE_REG_32BIT |
494 CLOCK_NO_IDLE_PARENT,
495 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
498 .sysc_addr = 0xfffb0054,
501 static struct clk uart2_ck = {
504 /* Direct from ULPD, no real parent */
505 .parent = &armper_ck.clk,
507 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
508 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
509 .enable_bit = 30, /* Chooses between 12MHz and 48MHz */
510 .set_rate = &omap1_set_uart_rate,
511 .recalc = &omap1_uart_recalc,
514 static struct clk uart3_1510 = {
517 /* Direct from ULPD, no real parent */
518 .parent = &armper_ck.clk,
520 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
521 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
522 .enable_bit = 31, /* Chooses between 12MHz and 48MHz */
523 .set_rate = &omap1_set_uart_rate,
524 .recalc = &omap1_uart_recalc,
527 static struct uart_clk uart3_16xx = {
531 /* Direct from ULPD, no real parent */
532 .parent = &armper_ck.clk,
534 .flags = RATE_FIXED | ENABLE_REG_32BIT |
535 CLOCK_NO_IDLE_PARENT,
536 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
539 .sysc_addr = 0xfffb9854,
542 static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
544 .ops = &clkops_generic,
545 /* Direct from ULPD, no parent */
547 .flags = RATE_FIXED | ENABLE_REG_32BIT,
548 .enable_reg = (void __iomem *)ULPD_CLOCK_CTRL,
549 .enable_bit = USB_MCLK_EN_BIT,
552 static struct clk usb_hhc_ck1510 = {
553 .name = "usb_hhc_ck",
554 .ops = &clkops_generic,
555 /* Direct from ULPD, no parent */
556 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
557 .flags = RATE_FIXED | ENABLE_REG_32BIT,
558 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
559 .enable_bit = USB_HOST_HHC_UHOST_EN,
562 static struct clk usb_hhc_ck16xx = {
563 .name = "usb_hhc_ck",
564 .ops = &clkops_generic,
565 /* Direct from ULPD, no parent */
567 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
568 .flags = RATE_FIXED | ENABLE_REG_32BIT,
569 .enable_reg = (void __iomem *)OTG_BASE + 0x08 /* OTG_SYSCON_2 */,
570 .enable_bit = 8 /* UHOST_EN */,
573 static struct clk usb_dc_ck = {
575 .ops = &clkops_generic,
576 /* Direct from ULPD, no parent */
579 .enable_reg = (void __iomem *)SOFT_REQ_REG,
583 static struct clk mclk_1510 = {
585 .ops = &clkops_generic,
586 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
589 .enable_reg = (void __iomem *)SOFT_REQ_REG,
593 static struct clk mclk_16xx = {
595 .ops = &clkops_generic,
596 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
597 .enable_reg = (void __iomem *)COM_CLK_DIV_CTRL_SEL,
598 .enable_bit = COM_ULPD_PLL_CLK_REQ,
599 .set_rate = &omap1_set_ext_clk_rate,
600 .round_rate = &omap1_round_ext_clk_rate,
601 .init = &omap1_init_ext_clk,
604 static struct clk bclk_1510 = {
606 .ops = &clkops_generic,
607 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
612 static struct clk bclk_16xx = {
614 .ops = &clkops_generic,
615 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
616 .enable_reg = (void __iomem *)SWD_CLK_DIV_CTRL_SEL,
617 .enable_bit = SWD_ULPD_PLL_CLK_REQ,
618 .set_rate = &omap1_set_ext_clk_rate,
619 .round_rate = &omap1_round_ext_clk_rate,
620 .init = &omap1_init_ext_clk,
623 static struct clk mmc1_ck = {
625 .ops = &clkops_generic,
626 /* Functional clock is direct from ULPD, interface clock is ARMPER */
627 .parent = &armper_ck.clk,
629 .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
630 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
634 static struct clk mmc2_ck = {
637 .ops = &clkops_generic,
638 /* Functional clock is direct from ULPD, interface clock is ARMPER */
639 .parent = &armper_ck.clk,
641 .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
642 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
646 static struct clk virtual_ck_mpu = {
649 .parent = &arm_ck, /* Is smarter alias for */
650 .recalc = &followparent_recalc,
651 .set_rate = &omap1_select_table_rate,
652 .round_rate = &omap1_round_to_table_rate,
655 /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
656 remains active during MPU idle whenever this is enabled */
657 static struct clk i2c_fck = {
661 .flags = CLOCK_NO_IDLE_PARENT,
662 .parent = &armxor_ck.clk,
663 .recalc = &followparent_recalc,
666 static struct clk i2c_ick = {
670 .flags = CLOCK_NO_IDLE_PARENT,
671 .parent = &armper_ck.clk,
672 .recalc = &followparent_recalc,