1 /* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/list.h>
26 #include <linux/spinlock.h>
27 #include <linux/slab.h>
28 #include <linux/iommu.h>
30 #include <asm/cacheflush.h>
31 #include <asm/sizes.h>
33 #include <mach/iommu_hw-8xxx.h>
34 #include <mach/iommu.h>
36 DEFINE_SPINLOCK(msm_iommu_lock);
39 unsigned long *pgtable;
40 struct list_head list_attached;
43 static void __flush_iotlb(struct iommu_domain *domain)
45 struct msm_priv *priv = domain->priv;
46 struct msm_iommu_drvdata *iommu_drvdata;
47 struct msm_iommu_ctx_drvdata *ctx_drvdata;
49 #ifndef CONFIG_IOMMU_PGTABLES_L2
50 unsigned long *fl_table = priv->pgtable;
53 if (!list_empty(&priv->list_attached)) {
54 dmac_flush_range(fl_table, fl_table + SZ_16K);
56 for (i = 0; i < NUM_FL_PTE; i++)
57 if ((fl_table[i] & 0x03) == FL_TYPE_TABLE) {
58 void *sl_table = __va(fl_table[i] &
60 dmac_flush_range(sl_table, sl_table + SZ_4K);
65 list_for_each_entry(ctx_drvdata, &priv->list_attached, attached_elm) {
66 if (!ctx_drvdata->pdev || !ctx_drvdata->pdev->dev.parent)
69 iommu_drvdata = dev_get_drvdata(ctx_drvdata->pdev->dev.parent);
70 SET_CTX_TLBIALL(iommu_drvdata->base, ctx_drvdata->num, 0);
74 static void __reset_context(void __iomem *base, int ctx)
76 SET_BPRCOSH(base, ctx, 0);
77 SET_BPRCISH(base, ctx, 0);
78 SET_BPRCNSH(base, ctx, 0);
79 SET_BPSHCFG(base, ctx, 0);
80 SET_BPMTCFG(base, ctx, 0);
81 SET_ACTLR(base, ctx, 0);
82 SET_SCTLR(base, ctx, 0);
83 SET_FSRRESTORE(base, ctx, 0);
84 SET_TTBR0(base, ctx, 0);
85 SET_TTBR1(base, ctx, 0);
86 SET_TTBCR(base, ctx, 0);
87 SET_BFBCR(base, ctx, 0);
88 SET_PAR(base, ctx, 0);
89 SET_FAR(base, ctx, 0);
90 SET_CTX_TLBIALL(base, ctx, 0);
91 SET_TLBFLPTER(base, ctx, 0);
92 SET_TLBSLPTER(base, ctx, 0);
93 SET_TLBLKCR(base, ctx, 0);
94 SET_PRRR(base, ctx, 0);
95 SET_NMRR(base, ctx, 0);
96 SET_CONTEXTIDR(base, ctx, 0);
99 static void __program_context(void __iomem *base, int ctx, phys_addr_t pgtable)
101 __reset_context(base, ctx);
103 /* Set up HTW mode */
104 /* TLB miss configuration: perform HTW on miss */
105 SET_TLBMCFG(base, ctx, 0x3);
107 /* V2P configuration: HTW for access */
108 SET_V2PCFG(base, ctx, 0x3);
110 SET_TTBCR(base, ctx, 0);
111 SET_TTBR0_PA(base, ctx, (pgtable >> 14));
113 /* Invalidate the TLB for this context */
114 SET_CTX_TLBIALL(base, ctx, 0);
116 /* Set interrupt number to "secure" interrupt */
117 SET_IRPTNDX(base, ctx, 0);
119 /* Enable context fault interrupt */
120 SET_CFEIE(base, ctx, 1);
122 /* Stall access on a context fault and let the handler deal with it */
123 SET_CFCFG(base, ctx, 1);
125 /* Redirect all cacheable requests to L2 slave port. */
126 SET_RCISH(base, ctx, 1);
127 SET_RCOSH(base, ctx, 1);
128 SET_RCNSH(base, ctx, 1);
130 /* Turn on TEX Remap */
131 SET_TRE(base, ctx, 1);
133 /* Do not configure PRRR / NMRR on the IOMMU for now. We will assume
134 * TEX class 0 for everything until attributes are properly worked out
136 SET_PRRR(base, ctx, 0);
137 SET_NMRR(base, ctx, 0);
139 /* Turn on BFB prefetch */
140 SET_BFBDFE(base, ctx, 1);
142 #ifdef CONFIG_IOMMU_PGTABLES_L2
143 /* Configure page tables as inner-cacheable and shareable to reduce
144 * the TLB miss penalty.
146 SET_TTBR0_SH(base, ctx, 1);
147 SET_TTBR1_SH(base, ctx, 1);
149 SET_TTBR0_NOS(base, ctx, 1);
150 SET_TTBR1_NOS(base, ctx, 1);
152 SET_TTBR0_IRGNH(base, ctx, 0); /* WB, WA */
153 SET_TTBR0_IRGNL(base, ctx, 1);
155 SET_TTBR1_IRGNH(base, ctx, 0); /* WB, WA */
156 SET_TTBR1_IRGNL(base, ctx, 1);
158 SET_TTBR0_ORGN(base, ctx, 1); /* WB, WA */
159 SET_TTBR1_ORGN(base, ctx, 1); /* WB, WA */
166 static int msm_iommu_domain_init(struct iommu_domain *domain)
168 struct msm_priv *priv = kzalloc(sizeof(*priv), GFP_KERNEL);
173 INIT_LIST_HEAD(&priv->list_attached);
174 priv->pgtable = (unsigned long *)__get_free_pages(GFP_KERNEL,
180 memset(priv->pgtable, 0, SZ_16K);
189 static void msm_iommu_domain_destroy(struct iommu_domain *domain)
191 struct msm_priv *priv;
193 unsigned long *fl_table;
196 spin_lock_irqsave(&msm_iommu_lock, flags);
201 fl_table = priv->pgtable;
203 for (i = 0; i < NUM_FL_PTE; i++)
204 if ((fl_table[i] & 0x03) == FL_TYPE_TABLE)
205 free_page((unsigned long) __va(((fl_table[i]) &
208 free_pages((unsigned long)priv->pgtable, get_order(SZ_16K));
209 priv->pgtable = NULL;
213 spin_unlock_irqrestore(&msm_iommu_lock, flags);
216 static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
218 struct msm_priv *priv;
219 struct msm_iommu_ctx_dev *ctx_dev;
220 struct msm_iommu_drvdata *iommu_drvdata;
221 struct msm_iommu_ctx_drvdata *ctx_drvdata;
222 struct msm_iommu_ctx_drvdata *tmp_drvdata;
226 spin_lock_irqsave(&msm_iommu_lock, flags);
235 iommu_drvdata = dev_get_drvdata(dev->parent);
236 ctx_drvdata = dev_get_drvdata(dev);
237 ctx_dev = dev->platform_data;
239 if (!iommu_drvdata || !ctx_drvdata || !ctx_dev) {
244 list_for_each_entry(tmp_drvdata, &priv->list_attached, attached_elm)
245 if (tmp_drvdata == ctx_drvdata) {
250 __program_context(iommu_drvdata->base, ctx_dev->num,
251 __pa(priv->pgtable));
253 list_add(&(ctx_drvdata->attached_elm), &priv->list_attached);
254 __flush_iotlb(domain);
257 spin_unlock_irqrestore(&msm_iommu_lock, flags);
261 static void msm_iommu_detach_dev(struct iommu_domain *domain,
264 struct msm_priv *priv;
265 struct msm_iommu_ctx_dev *ctx_dev;
266 struct msm_iommu_drvdata *iommu_drvdata;
267 struct msm_iommu_ctx_drvdata *ctx_drvdata;
270 spin_lock_irqsave(&msm_iommu_lock, flags);
276 iommu_drvdata = dev_get_drvdata(dev->parent);
277 ctx_drvdata = dev_get_drvdata(dev);
278 ctx_dev = dev->platform_data;
280 if (!iommu_drvdata || !ctx_drvdata || !ctx_dev)
283 __flush_iotlb(domain);
284 __reset_context(iommu_drvdata->base, ctx_dev->num);
285 list_del_init(&ctx_drvdata->attached_elm);
288 spin_unlock_irqrestore(&msm_iommu_lock, flags);
291 static int msm_iommu_map(struct iommu_domain *domain, unsigned long va,
292 phys_addr_t pa, int order, int prot)
294 struct msm_priv *priv;
296 unsigned long *fl_table;
297 unsigned long *fl_pte;
298 unsigned long fl_offset;
299 unsigned long *sl_table;
300 unsigned long *sl_pte;
301 unsigned long sl_offset;
302 size_t len = 0x1000UL << order;
305 spin_lock_irqsave(&msm_iommu_lock, flags);
313 fl_table = priv->pgtable;
315 if (len != SZ_16M && len != SZ_1M &&
316 len != SZ_64K && len != SZ_4K) {
317 pr_debug("Bad size: %d\n", len);
323 pr_debug("Null page table\n");
328 fl_offset = FL_OFFSET(va); /* Upper 12 bits */
329 fl_pte = fl_table + fl_offset; /* int pointers, 4 bytes */
333 for (i = 0; i < 16; i++)
334 *(fl_pte+i) = (pa & 0xFF000000) | FL_SUPERSECTION |
335 FL_AP_READ | FL_AP_WRITE | FL_TYPE_SECT |
340 *fl_pte = (pa & 0xFFF00000) | FL_AP_READ | FL_AP_WRITE |
341 FL_TYPE_SECT | FL_SHARED;
343 /* Need a 2nd level table */
344 if ((len == SZ_4K || len == SZ_64K) && (*fl_pte) == 0) {
346 sl = (unsigned long *) __get_free_pages(GFP_KERNEL,
350 pr_debug("Could not allocate second level table\n");
355 memset(sl, 0, SZ_4K);
356 *fl_pte = ((((int)__pa(sl)) & FL_BASE_MASK) | FL_TYPE_TABLE);
359 sl_table = (unsigned long *) __va(((*fl_pte) & FL_BASE_MASK));
360 sl_offset = SL_OFFSET(va);
361 sl_pte = sl_table + sl_offset;
365 *sl_pte = (pa & SL_BASE_MASK_SMALL) | SL_AP0 | SL_AP1 |
366 SL_SHARED | SL_TYPE_SMALL;
371 for (i = 0; i < 16; i++)
372 *(sl_pte+i) = (pa & SL_BASE_MASK_LARGE) | SL_AP0 |
373 SL_AP1 | SL_SHARED | SL_TYPE_LARGE;
376 __flush_iotlb(domain);
378 spin_unlock_irqrestore(&msm_iommu_lock, flags);
382 static int msm_iommu_unmap(struct iommu_domain *domain, unsigned long va,
385 struct msm_priv *priv;
387 unsigned long *fl_table;
388 unsigned long *fl_pte;
389 unsigned long fl_offset;
390 unsigned long *sl_table;
391 unsigned long *sl_pte;
392 unsigned long sl_offset;
393 size_t len = 0x1000UL << order;
396 spin_lock_irqsave(&msm_iommu_lock, flags);
405 fl_table = priv->pgtable;
407 if (len != SZ_16M && len != SZ_1M &&
408 len != SZ_64K && len != SZ_4K) {
409 pr_debug("Bad length: %d\n", len);
415 pr_debug("Null page table\n");
420 fl_offset = FL_OFFSET(va); /* Upper 12 bits */
421 fl_pte = fl_table + fl_offset; /* int pointers, 4 bytes */
424 pr_debug("First level PTE is 0\n");
429 /* Unmap supersection */
431 for (i = 0; i < 16; i++)
437 sl_table = (unsigned long *) __va(((*fl_pte) & FL_BASE_MASK));
438 sl_offset = SL_OFFSET(va);
439 sl_pte = sl_table + sl_offset;
442 for (i = 0; i < 16; i++)
449 if (len == SZ_4K || len == SZ_64K) {
452 for (i = 0; i < NUM_SL_PTE; i++)
456 free_page((unsigned long)sl_table);
461 __flush_iotlb(domain);
463 spin_unlock_irqrestore(&msm_iommu_lock, flags);
467 static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain,
470 struct msm_priv *priv;
471 struct msm_iommu_drvdata *iommu_drvdata;
472 struct msm_iommu_ctx_drvdata *ctx_drvdata;
479 spin_lock_irqsave(&msm_iommu_lock, flags);
482 if (list_empty(&priv->list_attached))
485 ctx_drvdata = list_entry(priv->list_attached.next,
486 struct msm_iommu_ctx_drvdata, attached_elm);
487 iommu_drvdata = dev_get_drvdata(ctx_drvdata->pdev->dev.parent);
489 base = iommu_drvdata->base;
490 ctx = ctx_drvdata->num;
492 /* Invalidate context TLB */
493 SET_CTX_TLBIALL(base, ctx, 0);
494 SET_V2PPR_VA(base, ctx, va >> V2Pxx_VA_SHIFT);
496 if (GET_FAULT(base, ctx))
499 par = GET_PAR(base, ctx);
501 /* We are dealing with a supersection */
502 if (GET_NOFAULT_SS(base, ctx))
503 ret = (par & 0xFF000000) | (va & 0x00FFFFFF);
504 else /* Upper 20 bits from PAR, lower 12 from VA */
505 ret = (par & 0xFFFFF000) | (va & 0x00000FFF);
508 spin_unlock_irqrestore(&msm_iommu_lock, flags);
512 static int msm_iommu_domain_has_cap(struct iommu_domain *domain,
518 static void print_ctx_regs(void __iomem *base, int ctx)
520 unsigned int fsr = GET_FSR(base, ctx);
521 pr_err("FAR = %08x PAR = %08x\n",
522 GET_FAR(base, ctx), GET_PAR(base, ctx));
523 pr_err("FSR = %08x [%s%s%s%s%s%s%s%s%s%s]\n", fsr,
524 (fsr & 0x02) ? "TF " : "",
525 (fsr & 0x04) ? "AFF " : "",
526 (fsr & 0x08) ? "APF " : "",
527 (fsr & 0x10) ? "TLBMF " : "",
528 (fsr & 0x20) ? "HTWDEEF " : "",
529 (fsr & 0x40) ? "HTWSEEF " : "",
530 (fsr & 0x80) ? "MHF " : "",
531 (fsr & 0x10000) ? "SL " : "",
532 (fsr & 0x40000000) ? "SS " : "",
533 (fsr & 0x80000000) ? "MULTI " : "");
535 pr_err("FSYNR0 = %08x FSYNR1 = %08x\n",
536 GET_FSYNR0(base, ctx), GET_FSYNR1(base, ctx));
537 pr_err("TTBR0 = %08x TTBR1 = %08x\n",
538 GET_TTBR0(base, ctx), GET_TTBR1(base, ctx));
539 pr_err("SCTLR = %08x ACTLR = %08x\n",
540 GET_SCTLR(base, ctx), GET_ACTLR(base, ctx));
541 pr_err("PRRR = %08x NMRR = %08x\n",
542 GET_PRRR(base, ctx), GET_NMRR(base, ctx));
545 irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id)
547 struct msm_iommu_drvdata *drvdata = dev_id;
549 unsigned int fsr = 0;
552 spin_lock(&msm_iommu_lock);
555 pr_err("Invalid device ID in context interrupt handler\n");
559 base = drvdata->base;
561 pr_err("===== WOAH! =====\n");
562 pr_err("Unexpected IOMMU page fault!\n");
563 pr_err("base = %08x\n", (unsigned int) base);
565 ncb = GET_NCB(base)+1;
566 for (i = 0; i < ncb; i++) {
567 fsr = GET_FSR(base, i);
569 pr_err("Fault occurred in context %d.\n", i);
570 pr_err("Interesting registers:\n");
571 print_ctx_regs(base, i);
572 SET_FSR(base, i, 0x4000000F);
576 spin_unlock(&msm_iommu_lock);
580 static struct iommu_ops msm_iommu_ops = {
581 .domain_init = msm_iommu_domain_init,
582 .domain_destroy = msm_iommu_domain_destroy,
583 .attach_dev = msm_iommu_attach_dev,
584 .detach_dev = msm_iommu_detach_dev,
585 .map = msm_iommu_map,
586 .unmap = msm_iommu_unmap,
587 .iova_to_phys = msm_iommu_iova_to_phys,
588 .domain_has_cap = msm_iommu_domain_has_cap
591 static int __init msm_iommu_init(void)
593 register_iommu(&msm_iommu_ops);
597 subsys_initcall(msm_iommu_init);
599 MODULE_LICENSE("GPL v2");
600 MODULE_AUTHOR("Stepan Moskovchenko <stepanm@codeaurora.org>");