1 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
21 #include <linux/interrupt.h>
22 #include <linux/clk.h>
24 /* Sharability attributes of MSM IOMMU mappings */
25 #define MSM_IOMMU_ATTR_NON_SH 0x0
26 #define MSM_IOMMU_ATTR_SH 0x4
28 /* Cacheability attributes of MSM IOMMU mappings */
29 #define MSM_IOMMU_ATTR_NONCACHED 0x0
30 #define MSM_IOMMU_ATTR_CACHED_WB_WA 0x1
31 #define MSM_IOMMU_ATTR_CACHED_WB_NWA 0x2
32 #define MSM_IOMMU_ATTR_CACHED_WT 0x3
34 /* Mask for the cache policy attribute */
35 #define MSM_IOMMU_CP_MASK 0x03
37 /* Maximum number of Machine IDs that we are allowing to be mapped to the same
38 * context bank. The number of MIDs mapped to the same CB does not affect
39 * performance, but there is a practical limit on how many distinct MIDs may
40 * be present. These mappings are typically determined at design time and are
41 * not expected to change at run time.
43 #define MAX_NUM_MIDS 32
46 * struct msm_iommu_dev - a single IOMMU hardware instance
47 * name Human-readable name given to this IOMMU HW instance
48 * clk_rate Rate to set for this IOMMU's clock, if applicable to this
49 * particular IOMMU. 0 means don't set a rate.
50 * -1 means it is an AXI clock with no valid rate
53 struct msm_iommu_dev {
59 * struct msm_iommu_ctx_dev - an IOMMU context bank instance
60 * name Human-readable name given to this context bank
61 * num Index of this context bank within the hardware
62 * mids List of Machine IDs that are to be mapped into this context
63 * bank, terminated by -1. The MID is a set of signals on the
64 * AXI bus that identifies the function associated with a specific
65 * memory request. (See ARM spec).
67 struct msm_iommu_ctx_dev {
70 int mids[MAX_NUM_MIDS];
75 * struct msm_iommu_drvdata - A single IOMMU hardware instance
76 * @base: IOMMU config port base address (VA)
77 * @irq: Interrupt number
78 * @clk: The bus clock for this IOMMU hardware instance
79 * @pclk: The clock for the IOMMU bus interconnect
81 * A msm_iommu_drvdata holds the global driver data about a single piece
82 * of an IOMMU hardware instance.
84 struct msm_iommu_drvdata {
92 * struct msm_iommu_ctx_drvdata - an IOMMU context bank instance
93 * @num: Hardware context number of this context
94 * @pdev: Platform device associated wit this HW instance
95 * @attached_elm: List element for domains to track which devices are
98 * A msm_iommu_ctx_drvdata holds the driver data for a single context bank
99 * within each IOMMU hardware instance
101 struct msm_iommu_ctx_drvdata {
103 struct platform_device *pdev;
104 struct list_head attached_elm;
108 * Look up an IOMMU context device by its context name. NULL if none found.
109 * Useful for testing and drivers that do not yet fully have IOMMU stuff in
110 * their platform devices.
112 struct device *msm_iommu_get_ctx(const char *ctx_name);
115 * Interrupt handler for the IOMMU context fault interrupt. Hooking the
116 * interrupt is not supported in the API yet, but this will print an error
117 * message and dump useful IOMMU registers.
119 irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id);