arch/arm/mach-mediatek/mt8516/init.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2018 MediaTek Inc.
   4  * Copyright (C) 2019 BayLibre, SAS
   5  * Author: Fabien Parent <fparent@baylibre.com>
   6  */
   7
   8 #include <clk.h>
   9 #include <common.h>
  10 #include <cpu_func.h>
  11 #include <dm.h>
  12 #include <fdtdec.h>
  13 #include <ram.h>
  14 #include <asm/arch/misc.h>
  15 #include <asm/armv8/mmu.h>
  16 #include <asm/cache.h>
  17 #include <asm/sections.h>
  18 #include <dm/uclass.h>
  19 #include <dt-bindings/clock/mt8516-clk.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 int dram_init(void)
  24 {
  25         int ret;
  26
  27         ret = fdtdec_setup_memory_banksize();
  28         if (ret)
  29                 return ret;
  30
  31         return fdtdec_setup_mem_size_base();
  32 }
  33
  34 int dram_init_banksize(void)
  35 {
  36         gd->bd->bi_dram[0].start = gd->ram_base;
  37         gd->bd->bi_dram[0].size = gd->ram_size;
  38
  39         return 0;
  40 }
  41
  42 int mtk_pll_early_init(void)
  43 {
  44         unsigned long pll_rates[] = {
  45                 [CLK_APMIXED_ARMPLL] =   1300000000,
  46                 [CLK_APMIXED_MAINPLL] =  1501000000,
  47                 [CLK_APMIXED_UNIVPLL] =  1248000000,
  48                 [CLK_APMIXED_MMPLL] =     380000000,
  49         };
  50         struct udevice *dev;
  51         int ret, i;
  52
  53         ret = uclass_get_device_by_driver(UCLASS_CLK,
  54                         DM_GET_DRIVER(mtk_clk_apmixedsys), &dev);
  55         if (ret)
  56                 return ret;
  57
  58         /* configure default rate then enable apmixedsys */
  59         for (i = 0; i < ARRAY_SIZE(pll_rates); i++) {
  60                 struct clk clk = { .id = i, .dev = dev };
  61
  62                 ret = clk_set_rate(&clk, pll_rates[i]);
  63                 if (ret)
  64                         return ret;
  65
  66                 ret = clk_enable(&clk);
  67                 if (ret)
  68                         return ret;
  69         }
  70
  71         return 0;
  72 }
  73
  74 int mtk_soc_early_init(void)
  75 {
  76         int ret;
  77
  78         /* initialize early clocks */
  79         ret = mtk_pll_early_init();
  80         if (ret)
  81                 return ret;
  82
  83         return 0;
  84 }
  85
  86 void reset_cpu(ulong addr)
  87 {
  88         psci_system_reset();
  89 }
  90
  91 int print_cpuinfo(void)
  92 {
  93         printf("CPU:   MediaTek MT8516\n");
  94         return 0;
  95 }
  96
  97 static struct mm_region mt8516_mem_map[] = {
  98         {
  99                 /* DDR */
 100                 .virt = 0x40000000UL,
 101                 .phys = 0x40000000UL,
 102                 .size = 0x20000000UL,
 103                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
 104         }, {
 105                 .virt = 0x00000000UL,
 106                 .phys = 0x00000000UL,
 107                 .size = 0x20000000UL,
 108                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 109                          PTE_BLOCK_NON_SHARE |
 110                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 111         }, {
 112                 0,
 113         }
 114 };
 115 struct mm_region *mem_map = mt8516_mem_map;