1 // SPDX-License-Identifier: GPL-2.0+
3 * Keystone2: Architecture initialization
5 * (C) Copyright 2012-2014
6 * Texas Instruments Incorporated, <www.ti.com>
12 #include <asm/cache.h>
14 #include <asm/arch/msmc.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/hardware.h>
17 #include <asm/arch/psc_defs.h>
19 #define MAX_PCI_PORTS 2
26 #define DEVCFG_MODE_MASK (BIT(2) | BIT(1))
27 #define DEVCFG_MODE_SHIFT 1
29 void chip_configuration_unlock(void)
31 __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
32 __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
41 u32 base = KS2_OSR_CFG_BASE;
42 u32 ecc_ctrl[KS2_OSR_NUM_RAM_BANKS];
44 /* Enable the OSR clock domain */
45 psc_enable_module(KS2_LPSC_OSR);
47 /* Disable OSR ECC check for all the ram banks */
48 for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++) {
49 val = i | KS2_OSR_ECC_VEC_TRIG_RD |
50 (KS2_OSR_ECC_CTRL << KS2_OSR_ECC_VEC_RD_ADDR_SH);
52 writel(val , base + KS2_OSR_ECC_VEC);
55 * wait till read is done.
56 * Print should be added after earlyprintk support is added.
58 for (j = 0; j < 10000; j++) {
59 val = readl(base + KS2_OSR_ECC_VEC);
60 if (val & KS2_OSR_ECC_VEC_RD_DONE)
64 ecc_ctrl[i] = readl(base + KS2_OSR_ECC_CTRL) ^
67 writel(ecc_ctrl[i], KS2_MSMC_DATA_BASE + i * 4);
68 writel(ecc_ctrl[i], base + KS2_OSR_ECC_CTRL);
71 /* Reset OSR memory to all zeros */
72 for (i = 0; i < KS2_OSR_SIZE; i += 4)
73 writel(0, KS2_OSR_DATA_BASE + i);
75 /* Enable OSR ECC check for all the ram banks */
76 for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++)
78 KS2_OSR_ECC_CTRL_CHK, base + KS2_OSR_ECC_CTRL);
82 /* Function to set up PCIe mode */
83 static void config_pcie_mode(int pcie_port, enum pci_mode mode)
85 u32 val = __raw_readl(KS2_DEVCFG);
87 if (pcie_port >= MAX_PCI_PORTS)
91 * each pci port has two bits for mode and it starts at
92 * bit 1. So use port number to get the right bit position.
95 val &= ~(DEVCFG_MODE_MASK << pcie_port);
96 val |= ((mode << DEVCFG_MODE_SHIFT) << pcie_port);
97 __raw_writel(val, KS2_DEVCFG);
100 static void msmc_k2hkle_common_setup(void)
102 msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_0);
103 msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_ARM);
104 msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_NETCP);
105 msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_QM_PDSP);
106 msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_PCIE0);
107 msmc_share_all_segments(KS2_MSMC_SEGMENT_DEBUG);
110 static void msmc_k2hk_setup(void)
112 msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_1);
113 msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_2);
114 msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_3);
115 msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_4);
116 msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_5);
117 msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_6);
118 msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_7);
119 msmc_share_all_segments(K2HKE_MSMC_SEGMENT_HYPERLINK);
122 static inline void msmc_k2l_setup(void)
124 msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_1);
125 msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_2);
126 msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_3);
127 msmc_share_all_segments(K2L_MSMC_SEGMENT_PCIE1);
130 static inline void msmc_k2e_setup(void)
132 msmc_share_all_segments(K2E_MSMC_SEGMENT_PCIE1);
133 msmc_share_all_segments(K2HKE_MSMC_SEGMENT_HYPERLINK);
134 msmc_share_all_segments(K2E_MSMC_SEGMENT_TSIP);
137 static void msmc_k2g_setup(void)
139 msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_0);
140 msmc_share_all_segments(K2G_MSMC_SEGMENT_ARM);
141 msmc_share_all_segments(K2G_MSMC_SEGMENT_ICSS0);
142 msmc_share_all_segments(K2G_MSMC_SEGMENT_ICSS1);
143 msmc_share_all_segments(K2G_MSMC_SEGMENT_NSS);
144 msmc_share_all_segments(K2G_MSMC_SEGMENT_PCIE);
145 msmc_share_all_segments(K2G_MSMC_SEGMENT_USB);
146 msmc_share_all_segments(K2G_MSMC_SEGMENT_MLB);
147 msmc_share_all_segments(K2G_MSMC_SEGMENT_PMMC);
148 msmc_share_all_segments(K2G_MSMC_SEGMENT_DSS);
149 msmc_share_all_segments(K2G_MSMC_SEGMENT_MMC);
150 msmc_share_all_segments(KS2_MSMC_SEGMENT_DEBUG);
153 int arch_cpu_init(void)
155 chip_configuration_unlock();
161 msmc_k2hkle_common_setup();
164 else if (cpu_is_k2l())
170 /* Initialize the PCIe-0 to work as Root Complex */
171 config_pcie_mode(0, ROOTCOMPLEX);
172 #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
173 /* Initialize the PCIe-1 to work as Root Complex */
174 config_pcie_mode(1, ROOTCOMPLEX);
176 #ifdef CONFIG_SOC_K2L
181 * just initialise the COM2 port so that TI specific
182 * UART register PWREMU_MGMT is initialized. Linux UART
183 * driver doesn't handle this.
185 #ifndef CONFIG_DM_SERIAL
186 NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM2),
187 CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
193 void reset_cpu(ulong addr)
195 volatile u32 *rstctrl = (volatile u32 *)(KS2_RSTCTRL);
198 tmp = *rstctrl & KS2_RSTCTRL_MASK;
199 *rstctrl = tmp | KS2_RSTCTRL_KEY;
201 *rstctrl &= KS2_RSTCTRL_SWRST;
207 void enable_caches(void)
209 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
210 /* Enable D-cache. I-cache is already enabled in start.S */
215 #if defined(CONFIG_DISPLAY_CPUINFO)
216 int print_cpuinfo(void)
218 u16 cpu = get_part_number();
219 u8 rev = cpu_revision();
234 #ifdef CONFIG_SOC_K2G
236 int speed = get_max_arm_speed(speeds);
237 if (speed == SPD1000)
239 else if (speed == SPD600)