1 // SPDX-License-Identifier: GPL-2.0+
3 * J721E: SoC specific initialization
5 * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
6 * Lokesh Vutla <lokeshvutla@ti.com>
12 #include <asm/armv7_mpu.h>
13 #include <asm/arch/hardware.h>
14 #include <asm/arch/sysfw-loader.h>
16 #include <asm/arch/sys_proto.h>
17 #include <linux/soc/ti/ti_sci_protocol.h>
19 #include <dm/uclass-internal.h>
20 #include <dm/pinctrl.h>
22 #include <remoteproc.h>
24 #ifdef CONFIG_SPL_BUILD
25 #ifdef CONFIG_K3_LOAD_SYSFW
26 #ifdef CONFIG_TI_SECURE_DEVICE
27 struct fwl_data cbass_hc_cfg0_fwls[] = {
28 { "PCIE0_CFG", 2560, 8 },
29 { "PCIE1_CFG", 2561, 8 },
30 { "USB3SS0_CORE", 2568, 4 },
31 { "USB3SS1_CORE", 2570, 4 },
32 { "EMMC8SS0_CFG", 2576, 4 },
33 { "UFS_HCI0_CFG", 2580, 4 },
34 { "SERDES0", 2584, 1 },
35 { "SERDES1", 2585, 1 },
36 }, cbass_hc0_fwls[] = {
37 { "PCIE0_HP", 2528, 24 },
38 { "PCIE0_LP", 2529, 24 },
39 { "PCIE1_HP", 2530, 24 },
40 { "PCIE1_LP", 2531, 24 },
41 }, cbass_rc_cfg0_fwls[] = {
42 { "EMMCSD4SS0_CFG", 2380, 4 },
43 }, cbass_rc0_fwls[] = {
45 }, infra_cbass0_fwls[] = {
46 { "PLL_MMR0", 8, 26 },
47 { "CTRL_MMR0", 9, 16 },
48 }, mcu_cbass0_fwls[] = {
49 { "MCU_R5FSS0_CORE0", 1024, 4 },
50 { "MCU_R5FSS0_CORE0_CFG", 1025, 2 },
51 { "MCU_R5FSS0_CORE1", 1028, 4 },
52 { "MCU_FSS0_CFG", 1032, 12 },
53 { "MCU_FSS0_S1", 1033, 8 },
54 { "MCU_FSS0_S0", 1036, 8 },
55 { "MCU_PSROM49152X32", 1048, 1 },
56 { "MCU_MSRAM128KX64", 1050, 8 },
57 { "MCU_CTRL_MMR0", 1200, 8 },
58 { "MCU_PLL_MMR0", 1201, 3 },
59 { "MCU_CPSW0", 1220, 2 },
60 }, wkup_cbass0_fwls[] = {
61 { "WKUP_CTRL_MMR0", 131, 16 },
66 static void mmr_unlock(u32 base, u32 partition)
68 /* Translate the base address */
69 phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
71 /* Unlock the requested partition if locked using two-step sequence */
72 writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
73 writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
76 static void ctrl_mmr_unlock(void)
78 /* Unlock all WKUP_CTRL_MMR0 module registers */
79 mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
80 mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
81 mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
82 mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
83 mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
84 mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
85 mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
87 /* Unlock all MCU_CTRL_MMR0 module registers */
88 mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
89 mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
90 mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
91 mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
92 mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
94 /* Unlock all CTRL_MMR0 module registers */
95 mmr_unlock(CTRL_MMR0_BASE, 0);
96 mmr_unlock(CTRL_MMR0_BASE, 1);
97 mmr_unlock(CTRL_MMR0_BASE, 2);
98 mmr_unlock(CTRL_MMR0_BASE, 3);
99 mmr_unlock(CTRL_MMR0_BASE, 4);
100 mmr_unlock(CTRL_MMR0_BASE, 5);
101 mmr_unlock(CTRL_MMR0_BASE, 6);
102 mmr_unlock(CTRL_MMR0_BASE, 7);
105 #if defined(CONFIG_K3_LOAD_SYSFW)
106 void k3_mmc_stop_clock(void)
108 if (spl_boot_device() == BOOT_DEVICE_MMC1) {
109 struct mmc *mmc = find_mmc_device(0);
114 mmc->saved_clock = mmc->clock;
115 mmc_set_clock(mmc, 0, true);
119 void k3_mmc_restart_clock(void)
121 if (spl_boot_device() == BOOT_DEVICE_MMC1) {
122 struct mmc *mmc = find_mmc_device(0);
127 mmc_set_clock(mmc, mmc->saved_clock, false);
133 * This uninitialized global variable would normal end up in the .bss section,
134 * but the .bss is cleared between writing and reading this variable, so move
135 * it to the .data section.
137 u32 bootindex __attribute__((section(".data")));
139 static void store_boot_index_from_rom(void)
141 bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
144 void board_init_f(ulong dummy)
146 #if defined(CONFIG_K3_J721E_DDRSS) || defined(CONFIG_K3_LOAD_SYSFW)
151 * Cannot delay this further as there is a chance that
152 * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
154 store_boot_index_from_rom();
156 /* Make all control module registers accessible */
159 #ifdef CONFIG_CPU_V7R
160 disable_linefill_optimization();
161 setup_k3_mpu_regions();
167 #ifdef CONFIG_K3_LOAD_SYSFW
169 * Process pinctrl for the serial0 a.k.a. MCU_UART0 module and continue
170 * regardless of the result of pinctrl. Do this without probing the
171 * device, but instead by searching the device that would request the
172 * given sequence number if probed. The UART will be used by the system
173 * firmware (SYSFW) image for various purposes and SYSFW depends on us
174 * to initialize its pin settings.
176 ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, true, &dev);
178 pinctrl_select_state(dev, "default");
181 * Load, start up, and configure system controller firmware. Provide
182 * the U-Boot console init function to the SYSFW post-PM configuration
183 * callback hook, effectively switching on (or over) the console
186 k3_sysfw_loader(k3_mmc_stop_clock, k3_mmc_restart_clock);
188 /* Prepare console output */
189 preloader_console_init();
191 /* Disable ROM configured firewalls right after loading sysfw */
192 #ifdef CONFIG_TI_SECURE_DEVICE
193 remove_fwl_configs(cbass_hc_cfg0_fwls, ARRAY_SIZE(cbass_hc_cfg0_fwls));
194 remove_fwl_configs(cbass_hc0_fwls, ARRAY_SIZE(cbass_hc0_fwls));
195 remove_fwl_configs(cbass_rc_cfg0_fwls, ARRAY_SIZE(cbass_rc_cfg0_fwls));
196 remove_fwl_configs(cbass_rc0_fwls, ARRAY_SIZE(cbass_rc0_fwls));
197 remove_fwl_configs(infra_cbass0_fwls, ARRAY_SIZE(infra_cbass0_fwls));
198 remove_fwl_configs(mcu_cbass0_fwls, ARRAY_SIZE(mcu_cbass0_fwls));
199 remove_fwl_configs(wkup_cbass0_fwls, ARRAY_SIZE(wkup_cbass0_fwls));
202 /* Prepare console output */
203 preloader_console_init();
206 /* Output System Firmware version info */
207 k3_sysfw_print_ver();
209 /* Perform EEPROM-based board detection */
212 #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
213 ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(k3_avs),
216 printf("AVS init failed: %d\n", ret);
219 #if defined(CONFIG_K3_J721E_DDRSS)
220 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
222 panic("DRAM init failed: %d\n", ret);
226 u32 spl_mmc_boot_mode(const u32 boot_device)
228 switch (boot_device) {
229 case BOOT_DEVICE_MMC1:
230 return MMCSD_MODE_EMMCBOOT;
231 case BOOT_DEVICE_MMC2:
232 return MMCSD_MODE_FS;
234 return MMCSD_MODE_RAW;
238 static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat)
241 u32 bootmode = (wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
242 WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
244 bootmode |= (main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) <<
247 if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
248 bootmode = BOOT_DEVICE_SPI;
250 if (bootmode == BOOT_DEVICE_MMC2) {
251 u32 port = (main_devstat &
252 MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK) >>
253 MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT;
255 bootmode = BOOT_DEVICE_MMC1;
261 u32 spl_boot_device(void)
263 u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
266 if (wkup_devstat & WKUP_DEVSTAT_MCU_OMLY_MASK) {
267 printf("ERROR: MCU only boot is not yet supported\n");
268 return BOOT_DEVICE_RAM;
271 /* MAIN CTRL MMR can only be read if MCU ONLY is 0 */
272 main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
274 /* ToDo: Add support for backup boot media */
275 return __get_primary_bootmedia(main_devstat, wkup_devstat);
279 #ifdef CONFIG_SYS_K3_SPL_ATF
281 #define J721E_DEV_MCU_RTI0 262
282 #define J721E_DEV_MCU_RTI1 263
283 #define J721E_DEV_MCU_ARMSS0_CPU0 250
284 #define J721E_DEV_MCU_ARMSS0_CPU1 251
286 void release_resources_for_core_shutdown(void)
288 struct ti_sci_handle *ti_sci;
289 struct ti_sci_dev_ops *dev_ops;
290 struct ti_sci_proc_ops *proc_ops;
294 const u32 put_device_ids[] = {
299 ti_sci = get_ti_sci_handle();
300 dev_ops = &ti_sci->ops.dev_ops;
301 proc_ops = &ti_sci->ops.proc_ops;
303 /* Iterate through list of devices to put (shutdown) */
304 for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
305 u32 id = put_device_ids[i];
307 ret = dev_ops->put_device(ti_sci, id);
309 panic("Failed to put device %u (%d)\n", id, ret);
312 const u32 put_core_ids[] = {
313 J721E_DEV_MCU_ARMSS0_CPU1,
314 J721E_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */
317 /* Iterate through list of cores to put (shutdown) */
318 for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
319 u32 id = put_core_ids[i];
322 * Queue up the core shutdown request. Note that this call
323 * needs to be followed up by an actual invocation of an WFE
324 * or WFI CPU instruction.
326 ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
328 panic("Failed sending core %u shutdown message (%d)\n",
334 #ifdef CONFIG_SYS_K3_SPL_ATF
335 void start_non_linux_remote_cores(void)
340 size = load_firmware("name_mainr5f0_0fw", "addr_mainr5f0_0load",
345 /* assuming remoteproc 2 is aliased for the needed remotecore */
346 ret = rproc_load(2, loadaddr, size);
348 printf("Firmware failed to start on rproc (%d)\n", ret);
352 ret = rproc_start(2);
354 printf("Firmware init failed on rproc (%d)\n", ret);
358 printf("Remoteproc 2 started successfully\n");