arch/arm/mach-exynos4/cpu.c

   1 /* linux/arch/arm/mach-exynos4/cpu.c
   2  *
   3  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9 */
  10
  11 #include <linux/sched.h>
  12 #include <linux/sysdev.h>
  13
  14 #include <asm/mach/map.h>
  15 #include <asm/mach/irq.h>
  16
  17 #include <asm/proc-fns.h>
  18 #include <asm/hardware/cache-l2x0.h>
  19
  20 #include <plat/cpu.h>
  21 #include <plat/clock.h>
  22 #include <plat/exynos4.h>
  23 #include <plat/sdhci.h>
  24 #include <plat/devs.h>
  25 #include <plat/fimc-core.h>
  26 #include <plat/iic-core.h>
  27
  28 #include <mach/regs-irq.h>
  29
  30 extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
  31                          unsigned int irq_start);
  32 extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
  33
  34 /* Initial IO mappings */
  35 static struct map_desc exynos4_iodesc[] __initdata = {
  36         {
  37                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
  38                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
  39                 .length         = SZ_4K,
  40                 .type           = MT_DEVICE,
  41         }, {
  42                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
  43                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM),
  44                 .length         = SZ_4K,
  45                 .type           = MT_DEVICE,
  46         }, {
  47                 .virtual        = (unsigned long)S5P_VA_CMU,
  48                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
  49                 .length         = SZ_128K,
  50                 .type           = MT_DEVICE,
  51         }, {
  52                 .virtual        = (unsigned long)S5P_VA_PMU,
  53                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
  54                 .length         = SZ_64K,
  55                 .type           = MT_DEVICE,
  56         }, {
  57                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
  58                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
  59                 .length         = SZ_4K,
  60                 .type           = MT_DEVICE,
  61         }, {
  62                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
  63                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
  64                 .length         = SZ_8K,
  65                 .type           = MT_DEVICE,
  66         }, {
  67                 .virtual        = (unsigned long)S5P_VA_L2CC,
  68                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
  69                 .length         = SZ_4K,
  70                 .type           = MT_DEVICE,
  71         }, {
  72                 .virtual        = (unsigned long)S5P_VA_GPIO1,
  73                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO1),
  74                 .length         = SZ_4K,
  75                 .type           = MT_DEVICE,
  76         }, {
  77                 .virtual        = (unsigned long)S5P_VA_GPIO2,
  78                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO2),
  79                 .length         = SZ_4K,
  80                 .type           = MT_DEVICE,
  81         }, {
  82                 .virtual        = (unsigned long)S5P_VA_GPIO3,
  83                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO3),
  84                 .length         = SZ_256,
  85                 .type           = MT_DEVICE,
  86         }, {
  87                 .virtual        = (unsigned long)S5P_VA_DMC0,
  88                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
  89                 .length         = SZ_4K,
  90                 .type           = MT_DEVICE,
  91         }, {
  92                 .virtual        = (unsigned long)S3C_VA_UART,
  93                 .pfn            = __phys_to_pfn(S3C_PA_UART),
  94                 .length         = SZ_512K,
  95                 .type           = MT_DEVICE,
  96         }, {
  97                 .virtual        = (unsigned long)S5P_VA_SROMC,
  98                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
  99                 .length         = SZ_4K,
 100                 .type           = MT_DEVICE,
 101         }, {
 102                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 103                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
 104                 .length         = SZ_4K,
 105                 .type           = MT_DEVICE,
 106         }, {
 107                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
 108                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
 109                 .length         = SZ_64K,
 110                 .type           = MT_DEVICE,
 111         }, {
 112                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
 113                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
 114                 .length         = SZ_64K,
 115                 .type           = MT_DEVICE,
 116         },
 117 };
 118
 119 static void exynos4_idle(void)
 120 {
 121         if (!need_resched())
 122                 cpu_do_idle();
 123
 124         local_irq_enable();
 125 }
 126
 127 /*
 128  * exynos4_map_io
 129  *
 130  * register the standard cpu IO areas
 131  */
 132 void __init exynos4_map_io(void)
 133 {
 134         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 135
 136         /* initialize device information early */
 137         exynos4_default_sdhci0();
 138         exynos4_default_sdhci1();
 139         exynos4_default_sdhci2();
 140         exynos4_default_sdhci3();
 141
 142         s3c_fimc_setname(0, "exynos4-fimc");
 143         s3c_fimc_setname(1, "exynos4-fimc");
 144         s3c_fimc_setname(2, "exynos4-fimc");
 145         s3c_fimc_setname(3, "exynos4-fimc");
 146
 147         /* The I2C bus controllers are directly compatible with s3c2440 */
 148         s3c_i2c0_setname("s3c2440-i2c");
 149         s3c_i2c1_setname("s3c2440-i2c");
 150         s3c_i2c2_setname("s3c2440-i2c");
 151 }
 152
 153 void __init exynos4_init_clocks(int xtal)
 154 {
 155         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 156
 157         s3c24xx_register_baseclocks(xtal);
 158         s5p_register_clocks(xtal);
 159         exynos4_register_clocks();
 160         exynos4_setup_clocks();
 161 }
 162
 163 void __init exynos4_init_irq(void)
 164 {
 165         int irq;
 166
 167         gic_init(0, IRQ_LOCALTIMER, S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
 168
 169         for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
 170
 171                 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
 172                                 COMBINER_IRQ(irq, 0));
 173                 combiner_cascade_irq(irq, IRQ_SPI(irq));
 174         }
 175
 176         /* The parameters of s5p_init_irq() are for VIC init.
 177          * Theses parameters should be NULL and 0 because EXYNOS4
 178          * uses GIC instead of VIC.
 179          */
 180         s5p_init_irq(NULL, 0);
 181 }
 182
 183 struct sysdev_class exynos4_sysclass = {
 184         .name   = "exynos4-core",
 185 };
 186
 187 static struct sys_device exynos4_sysdev = {
 188         .cls    = &exynos4_sysclass,
 189 };
 190
 191 static int __init exynos4_core_init(void)
 192 {
 193         return sysdev_class_register(&exynos4_sysclass);
 194 }
 195
 196 core_initcall(exynos4_core_init);
 197
 198 #ifdef CONFIG_CACHE_L2X0
 199 static int __init exynos4_l2x0_cache_init(void)
 200 {
 201         /* TAG, Data Latency Control: 2cycle */
 202         __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 203         __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 204
 205         /* L2X0 Prefetch Control */
 206         __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
 207
 208         /* L2X0 Power Control */
 209         __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
 210                      S5P_VA_L2CC + L2X0_POWER_CTRL);
 211
 212         l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
 213
 214         return 0;
 215 }
 216
 217 early_initcall(exynos4_l2x0_cache_init);
 218 #endif
 219
 220 int __init exynos4_init(void)
 221 {
 222         printk(KERN_INFO "EXYNOS4: Initializing architecture\n");
 223
 224         /* set idle function */
 225         pm_idle = exynos4_idle;
 226
 227         return sysdev_register(&exynos4_sysdev);
 228 }