2 * Texas Instruments TNETV107X SoC devices
4 * Copyright (C) 2010 Texas Instruments
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/platform_device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/clk.h>
20 #include <linux/slab.h>
22 #include <mach/common.h>
23 #include <mach/irqs.h>
24 #include <mach/edma.h>
25 #include <mach/tnetv107x.h>
29 /* Base addresses for on-chip devices */
30 #define TNETV107X_TPCC_BASE 0x01c00000
31 #define TNETV107X_TPTC0_BASE 0x01c10000
32 #define TNETV107X_TPTC1_BASE 0x01c10400
33 #define TNETV107X_WDOG_BASE 0x08086700
34 #define TNETV107X_SDIO0_BASE 0x08088700
35 #define TNETV107X_SDIO1_BASE 0x08088800
36 #define TNETV107X_ASYNC_EMIF_CNTRL_BASE 0x08200000
37 #define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE 0x30000000
38 #define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE 0x40000000
39 #define TNETV107X_ASYNC_EMIF_DATA_CE2_BASE 0x44000000
40 #define TNETV107X_ASYNC_EMIF_DATA_CE3_BASE 0x48000000
42 /* TNETV107X specific EDMA3 information */
43 #define EDMA_TNETV107X_NUM_DMACH 64
44 #define EDMA_TNETV107X_NUM_TCC 64
45 #define EDMA_TNETV107X_NUM_PARAMENTRY 128
46 #define EDMA_TNETV107X_NUM_EVQUE 2
47 #define EDMA_TNETV107X_NUM_TC 2
48 #define EDMA_TNETV107X_CHMAP_EXIST 0
49 #define EDMA_TNETV107X_NUM_REGIONS 4
50 #define TNETV107X_DMACH2EVENT_MAP0 0x3C0CE000u
51 #define TNETV107X_DMACH2EVENT_MAP1 0x000FFFFFu
53 #define TNETV107X_DMACH_SDIO0_RX 26
54 #define TNETV107X_DMACH_SDIO0_TX 27
55 #define TNETV107X_DMACH_SDIO1_RX 28
56 #define TNETV107X_DMACH_SDIO1_TX 29
58 static const s8 edma_tc_mapping[][2] = {
59 /* event queue no TC no */
65 static const s8 edma_priority_mapping[][2] = {
66 /* event queue no Prio */
72 static struct edma_soc_info edma_cc0_info = {
73 .n_channel = EDMA_TNETV107X_NUM_DMACH,
74 .n_region = EDMA_TNETV107X_NUM_REGIONS,
75 .n_slot = EDMA_TNETV107X_NUM_PARAMENTRY,
76 .n_tc = EDMA_TNETV107X_NUM_TC,
78 .queue_tc_mapping = edma_tc_mapping,
79 .queue_priority_mapping = edma_priority_mapping,
82 static struct edma_soc_info *tnetv107x_edma_info[EDMA_MAX_CC] = {
86 static struct resource edma_resources[] = {
89 .start = TNETV107X_TPCC_BASE,
90 .end = TNETV107X_TPCC_BASE + SZ_32K - 1,
91 .flags = IORESOURCE_MEM,
95 .start = TNETV107X_TPTC0_BASE,
96 .end = TNETV107X_TPTC0_BASE + SZ_1K - 1,
97 .flags = IORESOURCE_MEM,
101 .start = TNETV107X_TPTC1_BASE,
102 .end = TNETV107X_TPTC1_BASE + SZ_1K - 1,
103 .flags = IORESOURCE_MEM,
107 .start = IRQ_TNETV107X_TPCC,
108 .flags = IORESOURCE_IRQ,
112 .start = IRQ_TNETV107X_TPCC_ERR,
113 .flags = IORESOURCE_IRQ,
117 static struct platform_device edma_device = {
120 .num_resources = ARRAY_SIZE(edma_resources),
121 .resource = edma_resources,
122 .dev.platform_data = tnetv107x_edma_info,
125 static struct plat_serial8250_port serial_data[] = {
127 .mapbase = TNETV107X_UART0_BASE,
128 .irq = IRQ_TNETV107X_UART0,
129 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
130 UPF_FIXED_TYPE | UPF_IOREMAP,
132 .iotype = UPIO_MEM32,
136 .mapbase = TNETV107X_UART1_BASE,
137 .irq = IRQ_TNETV107X_UART1,
138 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
139 UPF_FIXED_TYPE | UPF_IOREMAP,
141 .iotype = UPIO_MEM32,
145 .mapbase = TNETV107X_UART2_BASE,
146 .irq = IRQ_TNETV107X_UART2,
147 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
148 UPF_FIXED_TYPE | UPF_IOREMAP,
150 .iotype = UPIO_MEM32,
158 struct platform_device tnetv107x_serial_device = {
159 .name = "serial8250",
160 .id = PLAT8250_DEV_PLATFORM,
161 .dev.platform_data = serial_data,
164 static struct resource mmc0_resources[] = {
165 { /* Memory mapped registers */
166 .start = TNETV107X_SDIO0_BASE,
167 .end = TNETV107X_SDIO0_BASE + 0x0ff,
168 .flags = IORESOURCE_MEM
170 { /* MMC interrupt */
171 .start = IRQ_TNETV107X_MMC0,
172 .flags = IORESOURCE_IRQ
174 { /* SDIO interrupt */
175 .start = IRQ_TNETV107X_SDIO0,
176 .flags = IORESOURCE_IRQ
179 .start = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO0_RX),
180 .flags = IORESOURCE_DMA
183 .start = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO0_TX),
184 .flags = IORESOURCE_DMA
188 static struct resource mmc1_resources[] = {
189 { /* Memory mapped registers */
190 .start = TNETV107X_SDIO1_BASE,
191 .end = TNETV107X_SDIO1_BASE + 0x0ff,
192 .flags = IORESOURCE_MEM
194 { /* MMC interrupt */
195 .start = IRQ_TNETV107X_MMC1,
196 .flags = IORESOURCE_IRQ
198 { /* SDIO interrupt */
199 .start = IRQ_TNETV107X_SDIO1,
200 .flags = IORESOURCE_IRQ
203 .start = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO1_RX),
204 .flags = IORESOURCE_DMA
207 .start = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO1_TX),
208 .flags = IORESOURCE_DMA
212 static u64 mmc0_dma_mask = DMA_BIT_MASK(32);
213 static u64 mmc1_dma_mask = DMA_BIT_MASK(32);
215 static struct platform_device mmc_devices[2] = {
217 .name = "davinci_mmc",
220 .dma_mask = &mmc0_dma_mask,
221 .coherent_dma_mask = DMA_BIT_MASK(32),
223 .num_resources = ARRAY_SIZE(mmc0_resources),
224 .resource = mmc0_resources
227 .name = "davinci_mmc",
230 .dma_mask = &mmc1_dma_mask,
231 .coherent_dma_mask = DMA_BIT_MASK(32),
233 .num_resources = ARRAY_SIZE(mmc1_resources),
234 .resource = mmc1_resources
238 static const u32 emif_windows[] = {
239 TNETV107X_ASYNC_EMIF_DATA_CE0_BASE, TNETV107X_ASYNC_EMIF_DATA_CE1_BASE,
240 TNETV107X_ASYNC_EMIF_DATA_CE2_BASE, TNETV107X_ASYNC_EMIF_DATA_CE3_BASE,
243 static const u32 emif_window_sizes[] = { SZ_256M, SZ_64M, SZ_64M, SZ_64M };
245 static struct resource wdt_resources[] = {
247 .start = TNETV107X_WDOG_BASE,
248 .end = TNETV107X_WDOG_BASE + SZ_4K - 1,
249 .flags = IORESOURCE_MEM,
253 struct platform_device tnetv107x_wdt_device = {
254 .name = "tnetv107x_wdt",
256 .num_resources = ARRAY_SIZE(wdt_resources),
257 .resource = wdt_resources,
260 static int __init nand_init(int chipsel, struct davinci_nand_pdata *data)
262 struct resource res[2];
263 struct platform_device *pdev;
267 /* Figure out the resource range from the ale/cle masks */
268 range = max(data->mask_cle, data->mask_ale);
269 range = PAGE_ALIGN(range + 4) - 1;
271 if (range >= emif_window_sizes[chipsel])
274 pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
278 pdev->name = "davinci_nand";
280 pdev->dev.platform_data = data;
282 memset(res, 0, sizeof(res));
284 res[0].start = emif_windows[chipsel];
285 res[0].end = res[0].start + range;
286 res[0].flags = IORESOURCE_MEM;
288 res[1].start = TNETV107X_ASYNC_EMIF_CNTRL_BASE;
289 res[1].end = res[1].start + SZ_4K - 1;
290 res[1].flags = IORESOURCE_MEM;
292 ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
298 return platform_device_register(pdev);
301 void __init tnetv107x_devices_init(struct tnetv107x_device_info *info)
305 platform_device_register(&edma_device);
306 platform_device_register(&tnetv107x_wdt_device);
308 if (info->serial_config)
309 davinci_serial_init(info->serial_config);
311 for (i = 0; i < 2; i++)
312 if (info->mmc_config[i]) {
313 mmc_devices[i].dev.platform_data = info->mmc_config[i];
314 platform_device_register(&mmc_devices[i]);
317 for (i = 0; i < 4; i++)
318 if (info->nand_config[i])
319 nand_init(i, info->nand_config[i]);