2 * linux/arch/arm/kernel/entry-armv.S
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Low-level vector interface routines
14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction
15 * that causes it to save wrong values... Be aware!
18 #include <asm/memory.h>
19 #include <asm/glue-df.h>
20 #include <asm/glue-pf.h>
21 #include <asm/vfpmacros.h>
22 #include <mach/entry-macro.S>
23 #include <asm/thread_notify.h>
24 #include <asm/unwind.h>
25 #include <asm/unistd.h>
28 #include "entry-header.S"
29 #include <asm/entry-macro-multi.S>
32 * Interrupt handling. Preserves r7, r8, r9
35 #ifdef CONFIG_MULTI_IRQ_HANDLER
36 ldr r5, =handle_arch_irq
43 arch_irq_handler_default
48 mov r0, r2 @ pass address of aborted instruction.
52 ldr pc, [r4, #PROCESSOR_PABT_FUNC]
61 @ Call the processor-specific abort handler:
63 @ r2 - aborted context pc
64 @ r3 - aborted context cpsr
66 @ The abort handler must return the aborted address in r0, and
67 @ the fault status register in r1. r9 must be preserved.
72 ldr pc, [r4, #PROCESSOR_DABT_FUNC]
79 .section .kprobes.text,"ax",%progbits
85 * Invalid mode handlers
87 .macro inv_entry, reason
88 sub sp, sp, #S_FRAME_SIZE
89 ARM( stmib sp, {r1 - lr} )
90 THUMB( stmia sp, {r0 - r12} )
91 THUMB( str sp, [sp, #S_SP] )
92 THUMB( str lr, [sp, #S_LR] )
97 inv_entry BAD_PREFETCH
99 ENDPROC(__pabt_invalid)
104 ENDPROC(__dabt_invalid)
109 ENDPROC(__irq_invalid)
112 inv_entry BAD_UNDEFINSTR
115 @ XXX fall through to common_invalid
119 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
125 add r0, sp, #S_PC @ here for interlock avoidance
126 mov r7, #-1 @ "" "" "" ""
127 str r4, [sp] @ save preserved r0
128 stmia r0, {r5 - r7} @ lr_<exception>,
129 @ cpsr_<exception>, "old_r0"
133 ENDPROC(__und_invalid)
139 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
140 #define SPFIX(code...) code
142 #define SPFIX(code...)
145 .macro svc_entry, stack_hole=0
147 UNWIND(.save {r0 - pc} )
148 sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4)
149 #ifdef CONFIG_THUMB2_KERNEL
150 SPFIX( str r0, [sp] ) @ temporarily saved
152 SPFIX( tst r0, #4 ) @ test original stack alignment
153 SPFIX( ldr r0, [sp] ) @ restored
157 SPFIX( subeq sp, sp, #4 )
161 add r5, sp, #S_SP - 4 @ here for interlock avoidance
162 mov r4, #-1 @ "" "" "" ""
163 add r0, sp, #(S_FRAME_SIZE + \stack_hole - 4)
164 SPFIX( addeq r0, r0, #4 )
165 str r1, [sp, #-4]! @ save the "real" r0 copied
166 @ from the exception stack
171 @ We are now ready to fill in the remaining blanks on the stack:
175 @ r2 - lr_<exception>, already fixed up for correct return/restart
176 @ r3 - spsr_<exception>
177 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
187 @ get ready to re-enable interrupts if appropriate
191 biceq r9, r9, #PSR_I_BIT
196 @ set desired IRQ state, then call main handler
204 @ IRQs off again before pulling preserved data off the stack
209 @ restore SPSR and restart the instruction
212 svc_exit r2 @ return from exception
220 #ifdef CONFIG_TRACE_IRQFLAGS
221 bl trace_hardirqs_off
223 #ifdef CONFIG_PREEMPT
225 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
226 add r7, r8, #1 @ increment it
227 str r7, [tsk, #TI_PREEMPT]
231 #ifdef CONFIG_PREEMPT
232 str r8, [tsk, #TI_PREEMPT] @ restore preempt count
233 ldr r0, [tsk, #TI_FLAGS] @ get flags
234 teq r8, #0 @ if preempt count != 0
235 movne r0, #0 @ force flags to 0
236 tst r0, #_TIF_NEED_RESCHED
239 ldr r4, [sp, #S_PSR] @ irqs are already disabled
240 #ifdef CONFIG_TRACE_IRQFLAGS
242 bleq trace_hardirqs_on
244 svc_exit r4 @ return from exception
250 #ifdef CONFIG_PREEMPT
253 1: bl preempt_schedule_irq @ irq en/disable is done inside
254 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
255 tst r0, #_TIF_NEED_RESCHED
256 moveq pc, r8 @ go again
262 #ifdef CONFIG_KPROBES
263 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
264 @ it obviously needs free stack space which then will belong to
272 @ call emulation code, which returns using r9 if it has emulated
273 @ the instruction, or the more conventional lr if we are to treat
274 @ this as a real undefined instruction
278 #ifndef CONFIG_THUMB2_KERNEL
281 ldrh r0, [r2, #-2] @ Thumb instruction at LR - 2
283 cmp r9, #0xe800 @ 32-bit instruction if xx >= 0
284 ldrhhs r9, [r2] @ bottom 16 bits
285 orrhs r0, r9, r0, lsl #16
290 mov r0, sp @ struct pt_regs *regs
294 @ IRQs off again before pulling preserved data off the stack
296 1: disable_irq_notrace
299 @ restore SPSR and restart the instruction
301 ldr r2, [sp, #S_PSR] @ Get SVC cpsr
302 svc_exit r2 @ return from exception
311 @ re-enable interrupts if appropriate
315 biceq r9, r9, #PSR_I_BIT
319 msr cpsr_c, r9 @ Maybe enable interrupts
321 bl do_PrefetchAbort @ call abort handler
324 @ IRQs off again before pulling preserved data off the stack
329 @ restore SPSR and restart the instruction
332 svc_exit r2 @ return from exception
349 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
352 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
353 #error "sizeof(struct pt_regs) must be a multiple of 8"
358 UNWIND(.cantunwind ) @ don't unwind the user space
359 sub sp, sp, #S_FRAME_SIZE
360 ARM( stmib sp, {r1 - r12} )
361 THUMB( stmia sp, {r0 - r12} )
364 add r0, sp, #S_PC @ here for interlock avoidance
365 mov r4, #-1 @ "" "" "" ""
367 str r1, [sp] @ save the "real" r0 copied
368 @ from the exception stack
371 @ We are now ready to fill in the remaining blanks on the stack:
373 @ r2 - lr_<exception>, already fixed up for correct return/restart
374 @ r3 - spsr_<exception>
375 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
377 @ Also, separately save sp_usr and lr_usr
380 ARM( stmdb r0, {sp, lr}^ )
381 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
384 @ Enable the alignment trap while in kernel mode
389 @ Clear FP to mark the first stack frame
394 .macro kuser_cmpxchg_check
395 #if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
397 #warning "NPTL on non MMU needs fixing"
399 @ Make sure our user space atomic helper is restarted
400 @ if it was interrupted in a critical region. Here we
401 @ perform a quick test inline since it should be false
402 @ 99.9999% of the time. The rest is done out of line.
404 blhs kuser_cmpxchg_fixup
416 @ IRQs on, then call the main handler
421 adr lr, BSYM(ret_from_exception)
431 #ifdef CONFIG_IRQSOFF_TRACER
432 bl trace_hardirqs_off
436 #ifdef CONFIG_PREEMPT
437 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
438 add r7, r8, #1 @ increment it
439 str r7, [tsk, #TI_PREEMPT]
443 #ifdef CONFIG_PREEMPT
444 ldr r0, [tsk, #TI_PREEMPT]
445 str r8, [tsk, #TI_PREEMPT]
447 ARM( strne r0, [r0, -r0] )
448 THUMB( movne r0, #0 )
449 THUMB( strne r0, [r0] )
453 b ret_to_user_from_irq
464 @ fall through to the emulation code, which returns using r9 if
465 @ it has emulated the instruction, or the more conventional lr
466 @ if we are to treat this as a real undefined instruction
470 adr r9, BSYM(ret_from_exception)
471 adr lr, BSYM(__und_usr_unknown)
472 tst r3, #PSR_T_BIT @ Thumb mode?
473 itet eq @ explicit IT needed for the 1f label
474 subeq r4, r2, #4 @ ARM instr at LR - 4
475 subne r4, r2, #2 @ Thumb instr at LR - 2
477 #ifdef CONFIG_CPU_ENDIAN_BE8
478 reveq r0, r0 @ little endian instruction
482 #if __LINUX_ARM_ARCH__ >= 7
484 ARM( ldrht r5, [r4], #2 )
485 THUMB( ldrht r5, [r4] )
486 THUMB( add r4, r4, #2 )
487 and r0, r5, #0xf800 @ mask bits 111x x... .... ....
488 cmp r0, #0xe800 @ 32bit instruction if xx != 0
489 blo __und_usr_unknown
491 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
492 orr r0, r0, r5, lsl #16
500 @ fallthrough to call_fpe
504 * The out of line fixup for the ldrt above.
506 .pushsection .fixup, "ax"
509 .pushsection __ex_table,"a"
511 #if __LINUX_ARM_ARCH__ >= 7
518 * Check whether the instruction is a co-processor instruction.
519 * If yes, we need to call the relevant co-processor handler.
521 * Note that we don't do a full check here for the co-processor
522 * instructions; all instructions with bit 27 set are well
523 * defined. The only instructions that should fault are the
524 * co-processor instructions. However, we have to watch out
525 * for the ARM6/ARM7 SWI bug.
527 * NEON is a special case that has to be handled here. Not all
528 * NEON instructions are co-processor instructions, so we have
529 * to make a special case of checking for them. Plus, there's
530 * five groups of them, so we have a table of mask/opcode pairs
531 * to check against, and if any match then we branch off into the
534 * Emulators may wish to make use of the following registers:
535 * r0 = instruction opcode.
537 * r9 = normal "successful" return address
538 * r10 = this threads thread_info structure.
539 * lr = unrecognised instruction return address
542 @ Fall-through from Thumb-2 __und_usr
545 adr r6, .LCneon_thumb_opcodes
550 adr r6, .LCneon_arm_opcodes
552 ldr r7, [r6], #4 @ mask value
553 cmp r7, #0 @ end mask?
556 ldr r7, [r6], #4 @ opcode bits matching in mask
557 cmp r8, r7 @ NEON instruction?
561 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
562 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
563 b do_vfp @ let VFP handler handle this
566 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
567 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
568 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
569 and r8, r0, #0x0f000000 @ mask out op-code bits
570 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)?
573 get_thread_info r10 @ get current thread
574 and r8, r0, #0x00000f00 @ mask out CP number
575 THUMB( lsr r8, r8, #8 )
577 add r6, r10, #TI_USED_CP
578 ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[]
579 THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[]
581 @ Test if we need to give access to iWMMXt coprocessors
582 ldr r5, [r10, #TI_FLAGS]
583 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
584 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
585 bcs iwmmxt_task_enable
587 ARM( add pc, pc, r8, lsr #6 )
588 THUMB( lsl r8, r8, #2 )
593 W(b) do_fpe @ CP#1 (FPE)
594 W(b) do_fpe @ CP#2 (FPE)
597 b crunch_task_enable @ CP#4 (MaverickCrunch)
598 b crunch_task_enable @ CP#5 (MaverickCrunch)
599 b crunch_task_enable @ CP#6 (MaverickCrunch)
609 W(b) do_vfp @ CP#10 (VFP)
610 W(b) do_vfp @ CP#11 (VFP)
612 movw_pc lr @ CP#10 (VFP)
613 movw_pc lr @ CP#11 (VFP)
617 movw_pc lr @ CP#14 (Debug)
618 movw_pc lr @ CP#15 (Control)
624 .word 0xfe000000 @ mask
625 .word 0xf2000000 @ opcode
627 .word 0xff100000 @ mask
628 .word 0xf4000000 @ opcode
630 .word 0x00000000 @ mask
631 .word 0x00000000 @ opcode
633 .LCneon_thumb_opcodes:
634 .word 0xef000000 @ mask
635 .word 0xef000000 @ opcode
637 .word 0xff100000 @ mask
638 .word 0xf9000000 @ opcode
640 .word 0x00000000 @ mask
641 .word 0x00000000 @ opcode
647 add r10, r10, #TI_FPSTATE @ r10 = workspace
648 ldr pc, [r4] @ Call FP module USR entry point
651 * The FP module is called with these registers set:
654 * r9 = normal "successful" return address
656 * lr = unrecognised FP instruction return address
671 adr lr, BSYM(ret_from_exception)
673 ENDPROC(__und_usr_unknown)
680 enable_irq @ Enable interrupts
682 bl do_PrefetchAbort @ call abort handler
686 * This is the return code to user mode for abort handlers
688 ENTRY(ret_from_exception)
696 ENDPROC(ret_from_exception)
699 * Register switch for ARMv3 and ARMv4 processors
700 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
701 * previous and next are guaranteed not to be the same.
706 add ip, r1, #TI_CPU_SAVE
707 ldr r3, [r2, #TI_TP_VALUE]
708 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
709 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
710 THUMB( str sp, [ip], #4 )
711 THUMB( str lr, [ip], #4 )
712 #ifdef CONFIG_CPU_USE_DOMAINS
713 ldr r6, [r2, #TI_CPU_DOMAIN]
716 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
717 ldr r7, [r2, #TI_TASK]
718 ldr r8, =__stack_chk_guard
719 ldr r7, [r7, #TSK_STACK_CANARY]
721 #ifdef CONFIG_CPU_USE_DOMAINS
722 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
725 add r4, r2, #TI_CPU_SAVE
726 ldr r0, =thread_notify_head
727 mov r1, #THREAD_NOTIFY_SWITCH
728 bl atomic_notifier_call_chain
729 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
734 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
735 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously
736 THUMB( ldr sp, [ip], #4 )
737 THUMB( ldr pc, [ip] )
746 * These are segment of kernel provided user code reachable from user space
747 * at a fixed address in kernel memory. This is used to provide user space
748 * with some operations which require kernel help because of unimplemented
749 * native feature and/or instructions in many ARM CPUs. The idea is for
750 * this code to be executed directly in user mode for best efficiency but
751 * which is too intimate with the kernel counter part to be left to user
752 * libraries. In fact this code might even differ from one CPU to another
753 * depending on the available instruction set and restrictions like on
754 * SMP systems. In other words, the kernel reserves the right to change
755 * this code as needed without warning. Only the entry points and their
756 * results are guaranteed to be stable.
758 * Each segment is 32-byte aligned and will be moved to the top of the high
759 * vector page. New segments (if ever needed) must be added in front of
760 * existing ones. This mechanism should be used only for things that are
761 * really small and justified, and not be abused freely.
763 * User space is expected to implement those things inline when optimizing
764 * for a processor that has the necessary native support, but only if such
765 * resulting binaries are already to be incompatible with earlier ARM
766 * processors due to the use of unsupported instructions other than what
767 * is provided here. In other words don't make binaries unable to run on
768 * earlier processors just for the sake of not using these kernel helpers
769 * if your compiled code is not going to use the new instructions for other
775 #ifdef CONFIG_ARM_THUMB
783 .globl __kuser_helper_start
784 __kuser_helper_start:
787 * Reference prototype:
789 * void __kernel_memory_barrier(void)
793 * lr = return address
803 * Definition and user space usage example:
805 * typedef void (__kernel_dmb_t)(void);
806 * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0)
808 * Apply any needed memory barrier to preserve consistency with data modified
809 * manually and __kuser_cmpxchg usage.
811 * This could be used as follows:
813 * #define __kernel_dmb() \
814 * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \
815 * : : : "r0", "lr","cc" )
818 __kuser_memory_barrier: @ 0xffff0fa0
825 * Reference prototype:
827 * int __kernel_cmpxchg(int oldval, int newval, int *ptr)
834 * lr = return address
838 * r0 = returned value (zero or non-zero)
839 * C flag = set if r0 == 0, clear if r0 != 0
845 * Definition and user space usage example:
847 * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr);
848 * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0)
850 * Atomically store newval in *ptr if *ptr is equal to oldval for user space.
851 * Return zero if *ptr was changed or non-zero if no exchange happened.
852 * The C flag is also set if *ptr was changed to allow for assembly
853 * optimization in the calling code.
857 * - This routine already includes memory barriers as needed.
859 * For example, a user space atomic_add implementation could look like this:
861 * #define atomic_add(ptr, val) \
862 * ({ register unsigned int *__ptr asm("r2") = (ptr); \
863 * register unsigned int __result asm("r1"); \
865 * "1: @ atomic_add\n\t" \
866 * "ldr r0, [r2]\n\t" \
867 * "mov r3, #0xffff0fff\n\t" \
868 * "add lr, pc, #4\n\t" \
869 * "add r1, r0, %2\n\t" \
870 * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \
872 * : "=&r" (__result) \
873 * : "r" (__ptr), "rIL" (val) \
874 * : "r0","r3","ip","lr","cc","memory" ); \
878 __kuser_cmpxchg: @ 0xffff0fc0
880 #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
883 * Poor you. No fast solution possible...
884 * The kernel itself must perform the operation.
885 * A special ghost syscall is used for that (see traps.c).
888 ldr r7, 1f @ it's 20 bits
891 1: .word __ARM_NR_cmpxchg
893 #elif __LINUX_ARM_ARCH__ < 6
898 * The only thing that can break atomicity in this cmpxchg
899 * implementation is either an IRQ or a data abort exception
900 * causing another process/thread to be scheduled in the middle
901 * of the critical sequence. To prevent this, code is added to
902 * the IRQ and data abort exception handlers to set the pc back
903 * to the beginning of the critical section if it is found to be
904 * within that critical section (see kuser_cmpxchg_fixup).
906 1: ldr r3, [r2] @ load current val
907 subs r3, r3, r0 @ compare with oldval
908 2: streq r1, [r2] @ store newval if eq
909 rsbs r0, r3, #0 @ set return val and C flag
914 @ Called from kuser_cmpxchg_check macro.
915 @ r2 = address of interrupted insn (must be preserved).
916 @ sp = saved regs. r7 and r8 are clobbered.
917 @ 1b = first critical insn, 2b = last critical insn.
918 @ If r2 >= 1b and r2 <= 2b then saved pc_usr is set to 1b.
920 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
922 rsbcss r8, r8, #(2b - 1b)
923 strcs r7, [sp, #S_PC]
928 #warning "NPTL on non MMU needs fixing"
943 /* beware -- each __kuser slot must be 8 instructions max */
944 ALT_SMP(b __kuser_memory_barrier)
952 * Reference prototype:
954 * int __kernel_get_tls(void)
958 * lr = return address
968 * Definition and user space usage example:
970 * typedef int (__kernel_get_tls_t)(void);
971 * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0)
973 * Get the TLS value as previously set via the __ARM_NR_set_tls syscall.
975 * This could be used as follows:
977 * #define __kernel_get_tls() \
978 * ({ register unsigned int __val asm("r0"); \
979 * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \
980 * : "=r" (__val) : : "lr","cc" ); \
984 __kuser_get_tls: @ 0xffff0fe0
985 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
987 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code
989 .word 0 @ 0xffff0ff0 software TLS value, then
990 .endr @ pad up to __kuser_helper_version
993 * Reference declaration:
995 * extern unsigned int __kernel_helper_version;
997 * Definition and user space usage example:
999 * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc)
1001 * User space may read this to determine the curent number of helpers
1005 __kuser_helper_version: @ 0xffff0ffc
1006 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
1008 .globl __kuser_helper_end
1016 * This code is copied to 0xffff0200 so we can use branches in the
1017 * vectors, rather than ldr's. Note that this code must not
1018 * exceed 0x300 bytes.
1020 * Common stub entry macro:
1021 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1023 * SP points to a minimal amount of processor-private memory, the address
1024 * of which is copied into r0 for the mode specific abort handler.
1026 .macro vector_stub, name, mode, correction=0
1031 sub lr, lr, #\correction
1035 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
1038 stmia sp, {r0, lr} @ save r0, lr
1040 str lr, [sp, #8] @ save spsr
1043 @ Prepare for SVC32 mode. IRQs remain disabled.
1046 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
1050 @ the branch table must immediately follow this code
1054 THUMB( ldr lr, [r0, lr, lsl #2] )
1056 ARM( ldr lr, [pc, lr, lsl #2] )
1057 movs pc, lr @ branch to handler in SVC mode
1058 ENDPROC(vector_\name)
1061 @ handler addresses follow this label
1065 .globl __stubs_start
1068 * Interrupt dispatcher
1070 vector_stub irq, IRQ_MODE, 4
1072 .long __irq_usr @ 0 (USR_26 / USR_32)
1073 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
1074 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
1075 .long __irq_svc @ 3 (SVC_26 / SVC_32)
1076 .long __irq_invalid @ 4
1077 .long __irq_invalid @ 5
1078 .long __irq_invalid @ 6
1079 .long __irq_invalid @ 7
1080 .long __irq_invalid @ 8
1081 .long __irq_invalid @ 9
1082 .long __irq_invalid @ a
1083 .long __irq_invalid @ b
1084 .long __irq_invalid @ c
1085 .long __irq_invalid @ d
1086 .long __irq_invalid @ e
1087 .long __irq_invalid @ f
1090 * Data abort dispatcher
1091 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1093 vector_stub dabt, ABT_MODE, 8
1095 .long __dabt_usr @ 0 (USR_26 / USR_32)
1096 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
1097 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
1098 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
1099 .long __dabt_invalid @ 4
1100 .long __dabt_invalid @ 5
1101 .long __dabt_invalid @ 6
1102 .long __dabt_invalid @ 7
1103 .long __dabt_invalid @ 8
1104 .long __dabt_invalid @ 9
1105 .long __dabt_invalid @ a
1106 .long __dabt_invalid @ b
1107 .long __dabt_invalid @ c
1108 .long __dabt_invalid @ d
1109 .long __dabt_invalid @ e
1110 .long __dabt_invalid @ f
1113 * Prefetch abort dispatcher
1114 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1116 vector_stub pabt, ABT_MODE, 4
1118 .long __pabt_usr @ 0 (USR_26 / USR_32)
1119 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
1120 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
1121 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
1122 .long __pabt_invalid @ 4
1123 .long __pabt_invalid @ 5
1124 .long __pabt_invalid @ 6
1125 .long __pabt_invalid @ 7
1126 .long __pabt_invalid @ 8
1127 .long __pabt_invalid @ 9
1128 .long __pabt_invalid @ a
1129 .long __pabt_invalid @ b
1130 .long __pabt_invalid @ c
1131 .long __pabt_invalid @ d
1132 .long __pabt_invalid @ e
1133 .long __pabt_invalid @ f
1136 * Undef instr entry dispatcher
1137 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1139 vector_stub und, UND_MODE
1141 .long __und_usr @ 0 (USR_26 / USR_32)
1142 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
1143 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
1144 .long __und_svc @ 3 (SVC_26 / SVC_32)
1145 .long __und_invalid @ 4
1146 .long __und_invalid @ 5
1147 .long __und_invalid @ 6
1148 .long __und_invalid @ 7
1149 .long __und_invalid @ 8
1150 .long __und_invalid @ 9
1151 .long __und_invalid @ a
1152 .long __und_invalid @ b
1153 .long __und_invalid @ c
1154 .long __und_invalid @ d
1155 .long __und_invalid @ e
1156 .long __und_invalid @ f
1160 /*=============================================================================
1162 *-----------------------------------------------------------------------------
1163 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
1164 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
1165 * Basically to switch modes, we *HAVE* to clobber one register... brain
1166 * damage alert! I don't think that we can execute any code in here in any
1167 * other mode than FIQ... Ok you can switch to another mode, but you can't
1168 * get out of that mode without clobbering one register.
1174 /*=============================================================================
1175 * Address exception handler
1176 *-----------------------------------------------------------------------------
1177 * These aren't too critical.
1178 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1185 * We group all the following data together to optimise
1186 * for CPUs with separate I & D caches.
1196 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start
1198 .globl __vectors_start
1200 ARM( swi SYS_ERROR0 )
1203 W(b) vector_und + stubs_offset
1204 W(ldr) pc, .LCvswi + stubs_offset
1205 W(b) vector_pabt + stubs_offset
1206 W(b) vector_dabt + stubs_offset
1207 W(b) vector_addrexcptn + stubs_offset
1208 W(b) vector_irq + stubs_offset
1209 W(b) vector_fiq + stubs_offset
1211 .globl __vectors_end
1217 .globl cr_no_alignment
1223 #ifdef CONFIG_MULTI_IRQ_HANDLER
1224 .globl handle_arch_irq