arch/arm/dts/sam9x60.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * sam9x60.dtsi - Device Tree Include file for SAM9X60 SoC.
   4  *
   5  * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
   6  *
   7  * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
   8  */
   9
  10 #include "skeleton.dtsi"
  11 #include <dt-bindings/dma/at91.h>
  12 #include <dt-bindings/pinctrl/at91.h>
  13 #include <dt-bindings/interrupt-controller/irq.h>
  14 #include <dt-bindings/gpio/gpio.h>
  15 #include <dt-bindings/clk/at91.h>
  16
  17 /{
  18         model = "Microchip SAM9X60 SoC";
  19         compatible = "microchip,sam9x60";
  20
  21         aliases {
  22                 serial0 = &dbgu;
  23                 gpio0 = &pioA;
  24                 gpio1 = &pioB;
  25                 gpio3 = &pioD;
  26                 spi0 = &qspi;
  27         };
  28
  29         clocks {
  30                 slow_rc_osc: slow_rc_osc {
  31                         compatible = "fixed-clock";
  32                         #clock-cells = <0>;
  33                         clock-frequency = <18500>;
  34                 };
  35
  36                 main_rc: main_rc {
  37                         compatible = "fixed-clock";
  38                         #clock-cells = <0>;
  39                         clock-frequency = <12000000>;
  40                 };
  41
  42                 slow_xtal: slow_xtal {
  43                         compatible = "fixed-clock";
  44                         #clock-cells = <0>;
  45                 };
  46
  47                 main_xtal: main_xtal {
  48                         compatible = "fixed-clock";
  49                         #clock-cells = <0>;
  50                 };
  51         };
  52
  53         ahb {
  54                 compatible = "simple-bus";
  55                 #address-cells = <1>;
  56                 #size-cells = <1>;
  57                 ranges;
  58
  59                 sdhci0: sdhci-host@80000000 {
  60                         compatible = "microchip,sam9x60-sdhci";
  61                         reg = <0x80000000 0x300>;
  62                         clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>;
  63                         clock-names = "hclock", "multclk";
  64                         assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
  65                         assigned-clock-rates = <100000000>;
  66                         assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* ID_PLL_A_DIV */
  67                         bus-width = <4>;
  68                         pinctrl-names = "default";
  69                         pinctrl-0 = <&pinctrl_sdhci0>;
  70                 };
  71
  72                 apb {
  73                         compatible = "simple-bus";
  74                         #address-cells = <1>;
  75                         #size-cells = <1>;
  76                         ranges;
  77
  78                         qspi: spi@f0014000 {
  79                                 compatible = "microchip,sam9x60-qspi";
  80                                 reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
  81                                 reg-names = "qspi_base", "qspi_mmap";
  82                                 clocks =  <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_SYSTEM 18>; /* ID_QSPI */
  83                                 clock-names = "pclk", "qspick";
  84                                 #address-cells = <1>;
  85                                 #size-cells = <0>;
  86                                 status = "disabled";
  87                         };
  88
  89                         flx0: flexcom@f801c600 {
  90                                 compatible = "atmel,sama5d2-flexcom";
  91                                 reg = <0xf801c000 0x200>;
  92                                 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
  93                                 #address-cells = <1>;
  94                                 #size-cells = <1>;
  95                                 ranges = <0x0 0xf801c000 0x800>;
  96                                 status = "disabled";
  97                         };
  98
  99                         macb0: ethernet@f802c000 {
 100                                 compatible = "cdns,sam9x60-macb", "cdns,macb";
 101                                 reg = <0xf802c000 0x100>;
 102                                 pinctrl-names = "default";
 103                                 pinctrl-0 = <&pinctrl_macb0_rmii>;
 104                                 clock-names = "hclk", "pclk";
 105                                 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>;
 106                                 status = "disabled";
 107                         };
 108
 109                         dbgu: serial@fffff200 {
 110                                 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
 111                                 reg = <0xfffff200 0x200>;
 112                                 pinctrl-names = "default";
 113                                 pinctrl-0 = <&pinctrl_dbgu>;
 114                                 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
 115                                 clock-names = "usart";
 116                         };
 117
 118                         pinctrl {
 119                                 #address-cells = <1>;
 120                                 #size-cells = <1>;
 121                                 compatible = "microchip,sam9x60-pinctrl", "simple-bus";
 122                                 ranges = <0xfffff400 0xfffff400 0x800>;
 123                                 reg = <0xfffff400 0x200         /* pioA */
 124                                        0xfffff600 0x200         /* pioB */
 125                                        0xfffff800 0x200         /* pioC */
 126                                        0xfffffa00 0x200>;       /* pioD */
 127
 128                                 /* shared pinctrl settings */
 129                                 dbgu {
 130                                         pinctrl_dbgu: dbgu-0 {
 131                                                 atmel,pins =
 132                                                         <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
 133                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
 134                                         };
 135                                 };
 136
 137                                 macb0 {
 138                                         pinctrl_macb0_rmii: macb0_rmii-0 {
 139                                                 atmel,pins =
 140                                                         <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB0 periph A */
 141                                                          AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB1 periph A */
 142                                                          AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB2 periph A */
 143                                                          AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB3 periph A */
 144                                                          AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB4 periph A */
 145                                                          AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB5 periph A */
 146                                                          AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB6 periph A */
 147                                                          AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB7 periph A */
 148                                                          AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB9 periph A */
 149                                                          AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
 150                                         };
 151                                 };
 152
 153                                 sdhci0 {
 154                                         pinctrl_sdhci0: sdhci0 {
 155                                                 atmel,pins =
 156                                                         <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_DRIVE_STRENGTH_DEFAULT /* PA17 CK  periph A with pullup */
 157                                                          AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP                /* PA16 CMD periph A with pullup */
 158                                                          AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP                /* PA15 DAT0 periph A */
 159                                                          AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP                /* PA18 DAT1 periph A with pullup */
 160                                                          AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP                /* PA19 DAT2 periph A with pullup */
 161                                                          AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;              /* PA20 DAT3 periph A with pullup */
 162                                         };
 163                                 };
 164                         };
 165
 166                         pioA: gpio@fffff400 {
 167                                 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 168                                 reg = <0xfffff400 0x200>;
 169                                 #gpio-cells = <2>;
 170                                 gpio-controller;
 171                                 clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
 172                         };
 173
 174                         pioB: gpio@fffff600 {
 175                                 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 176                                 reg = <0xfffff600 0x200>;
 177                                 #gpio-cells = <2>;
 178                                 gpio-controller;
 179                                 clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
 180                         };
 181
 182                         pioD: gpio@fffffa00 {
 183                                 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 184                                 reg = <0xfffffa00 0x200>;
 185                                 #gpio-cells = <2>;
 186                                 gpio-controller;
 187                                 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
 188                         };
 189
 190                         pmc: pmc@fffffc00 {
 191                                 compatible = "microchip,sam9x60-pmc";
 192                                 reg = <0xfffffc00 0x200>;
 193                                 #clock-cells = <2>;
 194                                 clocks = <&clk32 1>, <&clk32 0>, <&main_xtal>, <&main_rc>;
 195                                 clock-names = "td_slck", "md_slck", "main_xtal", "main_rc";
 196                                 status = "okay";
 197                         };
 198
 199                         pit: timer@fffffe40 {
 200                                 compatible = "atmel,at91sam9260-pit";
 201                                 reg = <0xfffffe40 0x10>;
 202                                 clocks = <&pmc PMC_TYPE_CORE 11>; /* ID_MCK. */
 203                         };
 204
 205                         clk32: sckc@fffffe50 {
 206                                 compatible = "microchip,sam9x60-sckc";
 207                                 reg = <0xfffffe50 0x4>;
 208                                 clocks = <&slow_rc_osc>, <&slow_xtal>;
 209                                 #clock-cells = <1>;
 210                         };
 211                 };
 212         };
 213
 214         onewire_tm: onewire {
 215                 compatible = "w1-gpio";
 216                 status = "disabled";
 217         };
 218 };