arch/arm/dts/imxrt1050-evk-u-boot.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (C) 2019
   4  * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
   5  */
   6
   7 #include <dt-bindings/memory/imxrt-sdram.h>
   8 #include "imxrt1050-pinfunc.h"
   9
  10 / {
  11         aliases {
  12                 display0 = &lcdif;
  13                 usbphy0 = &usbphy1;
  14         };
  15
  16         chosen {
  17                 bootph-pre-ram;
  18                 tick-timer = &gpt;
  19         };
  20
  21         clocks {
  22                 bootph-pre-ram;
  23         };
  24
  25         soc {
  26                 bootph-pre-ram;
  27
  28                 usbphy1: usbphy@400d9000 {
  29                         compatible = "fsl,imxrt-usbphy";
  30                         reg = <0x400d9000 0x1000>;
  31                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
  32                 };
  33
  34                 usbmisc: usbmisc@402e0800 {
  35                         #index-cells = <1>;
  36                         compatible = "fsl,imxrt-usbmisc";
  37                         reg = <0x402e0800 0x200>;
  38                         clocks = <&clks IMXRT1050_CLK_USBOH3>;
  39                 };
  40
  41                 usbotg1: usb@402e0000 {
  42                         compatible = "fsl,imxrt-usb", "fsl,imx27-usb";
  43                         reg = <0x402e0000 0x200>;
  44                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
  45                         clocks = <&clks IMXRT1050_CLK_USBOH3>;
  46                         fsl,usbphy = <&usbphy1>;
  47                         fsl,usbmisc = <&usbmisc 0>;
  48                         ahb-burst-config = <0x0>;
  49                         tx-burst-size-dword = <0x10>;
  50                         rx-burst-size-dword = <0x10>;
  51                         status = "disabled";
  52                 };
  53
  54                 lcdif: lcdif@402b8000 {
  55                         compatible = "fsl,imxrt-lcdif";
  56                         reg = <0x402b8000 0x4000>;
  57                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
  58                         clocks = <&clks IMXRT1050_CLK_LCDIF_PIX>,
  59                                  <&clks IMXRT1050_CLK_LCDIF_APB>;
  60                         clock-names = "pix", "axi";
  61                         assigned-clocks = <&clks IMXRT1050_CLK_LCDIF_SEL>;
  62                         assigned-clock-parents = <&clks IMXRT1050_CLK_PLL5_VIDEO>;
  63                         status = "disabled";
  64                 };
  65
  66                 semc: semc@402f0000 {
  67                         compatible = "fsl,imxrt-semc";
  68                         reg = <0x402f0000 0x4000>;
  69                         clocks = <&clks IMXRT1050_CLK_SEMC>;
  70                         pinctrl-0 = <&pinctrl_semc>;
  71                         pinctrl-names = "default";
  72                         status = "okay";
  73                 };
  74         };
  75 };
  76
  77 &semc {
  78         bootph-pre-ram;
  79         /*
  80          * Memory configuration from sdram datasheet IS42S16160J-6BLI
  81          */
  82         fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8
  83                                 MUX_CSX0_SDRAM_CS1
  84                                 0
  85                                 0
  86                                 0
  87                                 0>;
  88         fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITS
  89                                         BL_8
  90                                         COL_9BITS
  91                                         CL_3>;
  92         fsl,sdram-timing = /bits/ 8 <0x2
  93                                      0x2
  94                                      0x9
  95                                      0x1
  96                                      0x5
  97                                      0x6
  98
  99                                      0x20
 100                                      0x09
 101                                      0x01
 102                                      0x00
 103
 104                                      0x04
 105                                      0x0A
 106                                      0x21
 107                                      0x50>;
 108
 109         bank1: bank@0 {
 110                 fsl,base-address = <0x80000000>;
 111                 fsl,memory-size = <MEM_SIZE_32M>;
 112                 bootph-pre-ram;
 113         };
 114 };
 115
 116 &osc {
 117         bootph-pre-ram;
 118 };
 119
 120 &anatop {
 121         bootph-pre-ram;
 122 };
 123
 124 &clks {
 125         bootph-pre-ram;
 126 };
 127
 128 &gpio1 {
 129         compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
 130         bootph-pre-ram;
 131 };
 132
 133 &gpio2 {
 134         compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
 135         bootph-pre-ram;
 136 };
 137
 138 &gpio3 {
 139         compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
 140         bootph-pre-ram;
 141 };
 142
 143 &gpio4 {
 144         compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
 145         bootph-pre-ram;
 146 };
 147
 148 &gpio5 {
 149         compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
 150         bootph-pre-ram;
 151 };
 152
 153 &gpt {
 154         clocks = <&osc>;
 155         compatible = "fsl,imxrt-gpt";
 156         status = "okay";
 157         bootph-pre-ram;
 158 };
 159
 160 &lpuart1 { /* console */
 161         compatible = "fsl,imxrt-lpuart";
 162         clock-names = "per";
 163         bootph-pre-ram;
 164 };
 165
 166 &iomuxc {
 167         bootph-pre-ram;
 168         compatible = "fsl,imxrt-iomuxc";
 169         pinctrl-0 = <&pinctrl_lpuart1>;
 170
 171         pinctrl_semc: semcgrp {
 172                 fsl,pins = <
 173                         MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00
 174                                 0xf1    /* SEMC_D0 */
 175                         MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01
 176                                 0xf1    /* SEMC_D1 */
 177                         MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02
 178                                 0xf1    /* SEMC_D2 */
 179                         MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03
 180                                 0xf1    /* SEMC_D3 */
 181                         MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04
 182                                 0xf1    /* SEMC_D4 */
 183                         MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05
 184                                 0xf1    /* SEMC_D5 */
 185                         MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06
 186                                 0xf1    /* SEMC_D6 */
 187                         MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07
 188                                 0xf1    /* SEMC_D7 */
 189                         MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00
 190                                 0xf1    /* SEMC_DM0 */
 191                         MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
 192                                 0xf1    /* SEMC_A0 */
 193                         MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01
 194                                 0xf1    /* SEMC_A1 */
 195                         MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02
 196                                 0xf1    /* SEMC_A2 */
 197                         MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03
 198                                 0xf1    /* SEMC_A3 */
 199                         MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04
 200                                 0xf1    /* SEMC_A4 */
 201                         MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05
 202                                 0xf1    /* SEMC_A5 */
 203                         MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06
 204                                 0xf1    /* SEMC_A6 */
 205                         MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07
 206                                 0xf1    /* SEMC_A7 */
 207                         MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08
 208                                 0xf1    /* SEMC_A8 */
 209                         MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09
 210                                 0xf1    /* SEMC_A9 */
 211                         MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11
 212                                 0xf1    /* SEMC_A11 */
 213                         MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12
 214                                 0xf1    /* SEMC_A12 */
 215                         MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0
 216                                 0xf1    /* SEMC_BA0 */
 217                         MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1
 218                                 0xf1    /* SEMC_BA1 */
 219                         MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10
 220                                 0xf1    /* SEMC_A10 */
 221                         MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS
 222                                 0xf1    /* SEMC_CAS */
 223                         MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS
 224                                 0xf1    /* SEMC_RAS */
 225                         MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK
 226                                 0xf1    /* SEMC_CLK */
 227                         MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE
 228                                 0xf1    /* SEMC_CKE */
 229                         MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE
 230                                 0xf1    /* SEMC_WE */
 231                         MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0
 232                                 0xf1    /* SEMC_CS0 */
 233                         MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08
 234                                 0xf1    /* SEMC_D8 */
 235                         MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09
 236                                 0xf1    /* SEMC_D9 */
 237                         MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10
 238                                 0xf1    /* SEMC_D10 */
 239                         MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11
 240                                 0xf1    /* SEMC_D11 */
 241                         MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12
 242                                 0xf1    /* SEMC_D12 */
 243                         MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13
 244                                 0xf1    /* SEMC_D13 */
 245                         MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14
 246                                 0xf1    /* SEMC_D14 */
 247                         MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15
 248                                 0xf1    /* SEMC_D15 */
 249                         MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01
 250                                 0xf1    /* SEMC_DM1 */
 251                         MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS
 252                                 (IMX_PAD_SION | 0xf1)   /* SEMC_DQS */
 253                 >;
 254                 bootph-pre-ram;
 255         };
 256
 257         pinctrl_lcdif: lcdifgrp {
 258                 fsl,pins = <
 259                         MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK              0x1b0b1
 260                         MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE           0x1b0b1
 261                         MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC            0x1b0b1
 262                         MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC            0x1b0b1
 263                         MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00           0x1b0b1
 264                         MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01           0x1b0b1
 265                         MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02           0x1b0b1
 266                         MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03           0x1b0b1
 267                         MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04           0x1b0b1
 268                         MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05           0x1b0b1
 269                         MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06           0x1b0b1
 270                         MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07           0x1b0b1
 271                         MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08           0x1b0b1
 272                         MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09           0x1b0b1
 273                         MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10           0x1b0b1
 274                         MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11           0x1b0b1
 275                         MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13           0x1b0b1
 276                         MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14           0x1b0b1
 277                         MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15           0x1b0b1
 278                         MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31           0x0b069
 279                         MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02        0x0b069
 280                 >;
 281         };
 282
 283         pinctrl_lpuart1: lpuart1grp {
 284                 bootph-pre-ram;
 285         };
 286
 287         pinctrl_usdhc0: usdhc0grp {
 288                 bootph-pre-ram;
 289         };
 290  };
 291
 292 &usdhc1 {
 293         compatible = "fsl,imxrt-usdhc";
 294         bootph-pre-ram;
 295 };
 296
 297 &lcdif {
 298         pinctrl-names = "default";
 299         pinctrl-0 = <&pinctrl_lcdif>;
 300         display = <&display0>;
 301         status = "okay";
 302
 303         display0: display0 {
 304                 bits-per-pixel = <16>;
 305                 bus-width = <16>;
 306
 307                 display-timings {
 308                         timing0: timing0 {
 309                                 clock-frequency = <9300000>;
 310                                 hactive = <480>;
 311                                 vactive = <272>;
 312                                 hback-porch = <4>;
 313                                 hfront-porch = <8>;
 314                                 vback-porch = <4>;
 315                                 vfront-porch = <8>;
 316                                 hsync-len = <41>;
 317                                 vsync-len = <10>;
 318                                 de-active = <1>;
 319                                 pixelclk-active = <0>;
 320                                 hsync-active = <0>;
 321                                 vsync-active = <0>;
 322                         };
 323                 };
 324         };
 325 };
 326
 327 &usbotg1 {
 328         dr_mode = "host";
 329         status = "okay";
 330 };