arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2 /*
   3  * Copyright 2022 Toradex
   4  */
   5
   6 #include "imx8mp-u-boot.dtsi"
   7
   8 / {
   9         wdt-reboot {
  10                 compatible = "wdt-reboot";
  11                 bootph-pre-ram;
  12                 wdt = <&wdog1>;
  13         };
  14 };
  15
  16 &{/aliases} {
  17         eeprom0 = &eeprom_module;
  18         eeprom1 = &eeprom_carrier_board;
  19         eeprom2 = &eeprom_display_adapter;
  20 };
  21
  22 &clk {
  23         bootph-all;
  24         bootph-pre-ram;
  25         /delete-property/ assigned-clocks;
  26         /delete-property/ assigned-clock-parents;
  27         /delete-property/ assigned-clock-rates;
  28
  29 };
  30
  31 &gpio1 {
  32         bootph-pre-ram;
  33 };
  34
  35 &gpio2 {
  36         bootph-pre-ram;
  37
  38         regulator-ethphy {
  39                 gpio-hog;
  40                 gpios = <20 GPIO_ACTIVE_HIGH>;
  41                 line-name = "reg_ethphy";
  42                 output-high;
  43                 pinctrl-names = "default";
  44                 pinctrl-0 = <&pinctrl_reg_eth>;
  45         };
  46 };
  47
  48 &gpio3 {
  49         bootph-pre-ram;
  50 };
  51
  52 &gpio4 {
  53         bootph-pre-ram;
  54
  55         ctrl-sleep-moci-hog {
  56                 bootph-pre-ram;
  57         };
  58 };
  59
  60 &gpio5 {
  61         bootph-pre-ram;
  62 };
  63
  64 &i2c1 {
  65         bootph-pre-ram;
  66
  67         eeprom_module: eeprom@50 {
  68                 compatible = "i2c-eeprom";
  69                 pagesize = <16>;
  70                 reg = <0x50>;
  71         };
  72 };
  73
  74 &i2c2 {
  75         bootph-pre-ram;
  76 };
  77
  78 &i2c3 {
  79         bootph-pre-ram;
  80 };
  81
  82 &i2c4 {
  83         /* EEPROM on display adapter (MIPI DSI Display Adapter) */
  84         eeprom_display_adapter: eeprom@50 {
  85                 compatible = "i2c-eeprom";
  86                 pagesize = <16>;
  87                 reg = <0x50>;
  88         };
  89
  90         /* EEPROM on carrier board */
  91         eeprom_carrier_board: eeprom@57 {
  92                 compatible = "i2c-eeprom";
  93                 pagesize = <16>;
  94                 reg = <0x57>;
  95         };
  96 };
  97
  98 &pca9450 {
  99         bootph-pre-ram;
 100 };
 101
 102 &pinctrl_ctrl_sleep_moci {
 103         bootph-pre-ram;
 104 };
 105
 106 &pinctrl_i2c1 {
 107         bootph-pre-ram;
 108 };
 109
 110 &pinctrl_usdhc2_pwr_en {
 111         bootph-pre-ram;
 112         u-boot,off-on-delay-us = <20000>;
 113 };
 114
 115 &pinctrl_uart3 {
 116         bootph-pre-ram;
 117 };
 118
 119 &pinctrl_usdhc2_cd {
 120         bootph-pre-ram;
 121 };
 122
 123 &pinctrl_usdhc2 {
 124         bootph-pre-ram;
 125 };
 126
 127 &pinctrl_usdhc3 {
 128         bootph-pre-ram;
 129 };
 130
 131 &pinctrl_wdog {
 132         bootph-pre-ram;
 133 };
 134
 135 &reg_usdhc2_vmmc {
 136         bootph-pre-ram;
 137 };
 138
 139 &uart3 {
 140         bootph-pre-ram;
 141 };
 142
 143 &usdhc1 {
 144         status = "disabled";
 145 };
 146
 147 &usdhc2 {
 148         assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
 149         assigned-clock-rates = <400000000>;
 150         assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
 151         sd-uhs-ddr50;
 152         sd-uhs-sdr104;
 153         bootph-pre-ram;
 154 };
 155
 156 &usdhc3 {
 157         assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
 158         assigned-clock-rates = <400000000>;
 159         assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
 160         mmc-hs400-1_8v;
 161         mmc-hs400-enhanced-strobe;
 162         bootph-pre-ram;
 163 };
 164
 165 &wdog1 {
 166         bootph-pre-ram;
 167 };