arch/arm/boot/dts/ste-dbx5x0.dtsi

   1 /*
   2  * Copyright 2012 Linaro Ltd
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include <dt-bindings/interrupt-controller/irq.h>
  13 #include <dt-bindings/mfd/dbx500-prcmu.h>
  14 #include <dt-bindings/arm/ux500_pm_domains.h>
  15 #include "skeleton.dtsi"
  16
  17 / {
  18         soc {
  19                 #address-cells = <1>;
  20                 #size-cells = <1>;
  21                 compatible = "stericsson,db8500";
  22                 interrupt-parent = <&intc>;
  23                 ranges;
  24
  25                 cpus {
  26                         #address-cells = <1>;
  27                         #size-cells = <0>;
  28
  29                         cpu-map {
  30                                 cluster0 {
  31                                         core0 {
  32                                                 cpu = <&CPU0>;
  33                                         };
  34                                         core1 {
  35                                                 cpu = <&CPU1>;
  36                                         };
  37                                 };
  38                         };
  39                         CPU0: cpu@0 {
  40                                 device_type = "cpu";
  41                                 compatible = "arm,cortex-a9";
  42                                 reg = <0>;
  43                         };
  44                         CPU1: cpu@1 {
  45                                 device_type = "cpu";
  46                                 compatible = "arm,cortex-a9";
  47                                 reg = <1>;
  48                         };
  49                 };
  50
  51                 ptm@801ae000 {
  52                         compatible = "arm,coresight-etm3x", "arm,primecell";
  53                         reg = <0x801ae000 0x1000>;
  54
  55                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
  56                         clock-names = "apb_pclk", "atclk";
  57                         cpu = <&CPU0>;
  58                         port {
  59                                 ptm0_out_port: endpoint {
  60                                         remote-endpoint = <&funnel_in_port0>;
  61                                 };
  62                         };
  63                 };
  64
  65                 ptm@801af000 {
  66                         compatible = "arm,coresight-etm3x", "arm,primecell";
  67                         reg = <0x801af000 0x1000>;
  68
  69                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
  70                         clock-names = "apb_pclk", "atclk";
  71                         cpu = <&CPU1>;
  72                         port {
  73                                 ptm1_out_port: endpoint {
  74                                         remote-endpoint = <&funnel_in_port1>;
  75                                 };
  76                         };
  77                 };
  78
  79                 funnel@801a6000 {
  80                         compatible = "arm,coresight-funnel", "arm,primecell";
  81                         reg = <0x801a6000 0x1000>;
  82
  83                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
  84                         clock-names = "apb_pclk", "atclk";
  85                         ports {
  86                                 #address-cells = <1>;
  87                                 #size-cells = <0>;
  88
  89                                 /* funnel output ports */
  90                                 port@0 {
  91                                         reg = <0>;
  92                                         funnel_out_port: endpoint {
  93                                                 remote-endpoint =
  94                                                         <&replicator_in_port0>;
  95                                         };
  96                                 };
  97
  98                                 /* funnel input ports */
  99                                 port@1 {
 100                                         reg = <0>;
 101                                         funnel_in_port0: endpoint {
 102                                                 slave-mode;
 103                                                 remote-endpoint = <&ptm0_out_port>;
 104                                         };
 105                                 };
 106
 107                                 port@2 {
 108                                         reg = <1>;
 109                                         funnel_in_port1: endpoint {
 110                                                 slave-mode;
 111                                                 remote-endpoint = <&ptm1_out_port>;
 112                                         };
 113                                 };
 114                         };
 115                 };
 116
 117                 replicator {
 118                         compatible = "arm,coresight-replicator";
 119                         clocks = <&prcmu_clk PRCMU_APEATCLK>;
 120                         clock-names = "atclk";
 121
 122                         ports {
 123                                 #address-cells = <1>;
 124                                 #size-cells = <0>;
 125
 126                                 /* replicator output ports */
 127                                 port@0 {
 128                                         reg = <0>;
 129                                         replicator_out_port0: endpoint {
 130                                                 remote-endpoint = <&tpiu_in_port>;
 131                                         };
 132                                 };
 133                                 port@1 {
 134                                         reg = <1>;
 135                                         replicator_out_port1: endpoint {
 136                                                 remote-endpoint = <&etb_in_port>;
 137                                         };
 138                                 };
 139
 140                                 /* replicator input port */
 141                                 port@2 {
 142                                         reg = <0>;
 143                                         replicator_in_port0: endpoint {
 144                                                 slave-mode;
 145                                                 remote-endpoint = <&funnel_out_port>;
 146                                         };
 147                                 };
 148                         };
 149                 };
 150
 151                 tpiu@80190000 {
 152                         compatible = "arm,coresight-tpiu", "arm,primecell";
 153                         reg = <0x80190000 0x1000>;
 154
 155                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
 156                         clock-names = "apb_pclk", "atclk";
 157                         port {
 158                                 tpiu_in_port: endpoint {
 159                                         slave-mode;
 160                                         remote-endpoint = <&replicator_out_port0>;
 161                                 };
 162                         };
 163                 };
 164
 165                 etb@801a4000 {
 166                         compatible = "arm,coresight-etb10", "arm,primecell";
 167                         reg = <0x801a4000 0x1000>;
 168
 169                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
 170                         clock-names = "apb_pclk", "atclk";
 171                         port {
 172                                 etb_in_port: endpoint {
 173                                         slave-mode;
 174                                         remote-endpoint = <&replicator_out_port1>;
 175                                 };
 176                         };
 177                 };
 178
 179                 intc: interrupt-controller@a0411000 {
 180                         compatible = "arm,cortex-a9-gic";
 181                         #interrupt-cells = <3>;
 182                         #address-cells = <1>;
 183                         interrupt-controller;
 184                         reg = <0xa0411000 0x1000>,
 185                               <0xa0410100 0x100>;
 186                 };
 187
 188                 scu@a04100000 {
 189                         compatible = "arm,cortex-a9-scu";
 190                         reg = <0xa0410000 0x100>;
 191                 };
 192
 193                 /*
 194                  * The backup RAM is used for retention during sleep
 195                  * and various things like spin tables
 196                  */
 197                 backupram@80150000 {
 198                         compatible = "ste,dbx500-backupram";
 199                         reg = <0x80150000 0x2000>;
 200                 };
 201
 202                 L2: l2-cache {
 203                         compatible = "arm,pl310-cache";
 204                         reg = <0xa0412000 0x1000>;
 205                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
 206                         cache-unified;
 207                         cache-level = <2>;
 208                 };
 209
 210                 pmu {
 211                         compatible = "arm,cortex-a9-pmu";
 212                         interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 213                 };
 214
 215                 pm_domains: pm_domains0 {
 216                         compatible = "stericsson,ux500-pm-domains";
 217                         #power-domain-cells = <1>;
 218                 };
 219
 220                 clocks {
 221                         compatible = "stericsson,u8500-clks";
 222                         /*
 223                          * Registers for the CLKRST block on peripheral
 224                          * groups 1, 2, 3, 5, 6,
 225                          */
 226                         reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
 227                             <0x8000f000 0x1000>, <0xa03ff000 0x1000>,
 228                             <0xa03cf000 0x1000>;
 229
 230                         prcmu_clk: prcmu-clock {
 231                                 #clock-cells = <1>;
 232                         };
 233
 234                         prcc_pclk: prcc-periph-clock {
 235                                 #clock-cells = <2>;
 236                         };
 237
 238                         prcc_kclk: prcc-kernel-clock {
 239                                 #clock-cells = <2>;
 240                         };
 241
 242                         rtc_clk: rtc32k-clock {
 243                                 #clock-cells = <0>;
 244                         };
 245
 246                         smp_twd_clk: smp-twd-clock {
 247                                 #clock-cells = <0>;
 248                         };
 249                 };
 250
 251                 mtu@a03c6000 {
 252                         /* Nomadik System Timer */
 253                         compatible = "st,nomadik-mtu";
 254                         reg = <0xa03c6000 0x1000>;
 255                         interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
 256
 257                         clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>;
 258                         clock-names = "timclk", "apb_pclk";
 259                 };
 260
 261                 timer@a0410600 {
 262                         compatible = "arm,cortex-a9-twd-timer";
 263                         reg = <0xa0410600 0x20>;
 264                         interrupts = <1 13 0x304>; /* IRQ level high per-CPU */
 265
 266                         clocks = <&smp_twd_clk>;
 267                 };
 268
 269                 watchdog@a0410620 {
 270                         compatible = "arm,cortex-a9-twd-wdt";
 271                         reg = <0xa0410620 0x20>;
 272                         interrupts = <1 14 0x304>;
 273                         clocks = <&smp_twd_clk>;
 274                 };
 275
 276                 rtc@80154000 {
 277                         compatible = "arm,rtc-pl031", "arm,primecell";
 278                         reg = <0x80154000 0x1000>;
 279                         interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
 280
 281                         clocks = <&rtc_clk>;
 282                         clock-names = "apb_pclk";
 283                 };
 284
 285                 gpio0: gpio@8012e000 {
 286                         compatible = "stericsson,db8500-gpio",
 287                                 "st,nomadik-gpio";
 288                         reg =  <0x8012e000 0x80>;
 289                         interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
 290                         interrupt-controller;
 291                         #interrupt-cells = <2>;
 292                         st,supports-sleepmode;
 293                         gpio-controller;
 294                         #gpio-cells = <2>;
 295                         gpio-bank = <0>;
 296
 297                         clocks = <&prcc_pclk 1 9>;
 298                 };
 299
 300                 gpio1: gpio@8012e080 {
 301                         compatible = "stericsson,db8500-gpio",
 302                                 "st,nomadik-gpio";
 303                         reg =  <0x8012e080 0x80>;
 304                         interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
 305                         interrupt-controller;
 306                         #interrupt-cells = <2>;
 307                         st,supports-sleepmode;
 308                         gpio-controller;
 309                         #gpio-cells = <2>;
 310                         gpio-bank = <1>;
 311
 312                         clocks = <&prcc_pclk 1 9>;
 313                 };
 314
 315                 gpio2: gpio@8000e000 {
 316                         compatible = "stericsson,db8500-gpio",
 317                                 "st,nomadik-gpio";
 318                         reg =  <0x8000e000 0x80>;
 319                         interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH>;
 320                         interrupt-controller;
 321                         #interrupt-cells = <2>;
 322                         st,supports-sleepmode;
 323                         gpio-controller;
 324                         #gpio-cells = <2>;
 325                         gpio-bank = <2>;
 326
 327                         clocks = <&prcc_pclk 3 8>;
 328                 };
 329
 330                 gpio3: gpio@8000e080 {
 331                         compatible = "stericsson,db8500-gpio",
 332                                 "st,nomadik-gpio";
 333                         reg =  <0x8000e080 0x80>;
 334                         interrupts = <0 122 IRQ_TYPE_LEVEL_HIGH>;
 335                         interrupt-controller;
 336                         #interrupt-cells = <2>;
 337                         st,supports-sleepmode;
 338                         gpio-controller;
 339                         #gpio-cells = <2>;
 340                         gpio-bank = <3>;
 341
 342                         clocks = <&prcc_pclk 3 8>;
 343                 };
 344
 345                 gpio4: gpio@8000e100 {
 346                         compatible = "stericsson,db8500-gpio",
 347                                 "st,nomadik-gpio";
 348                         reg =  <0x8000e100 0x80>;
 349                         interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
 350                         interrupt-controller;
 351                         #interrupt-cells = <2>;
 352                         st,supports-sleepmode;
 353                         gpio-controller;
 354                         #gpio-cells = <2>;
 355                         gpio-bank = <4>;
 356
 357                         clocks = <&prcc_pclk 3 8>;
 358                 };
 359
 360                 gpio5: gpio@8000e180 {
 361                         compatible = "stericsson,db8500-gpio",
 362                                 "st,nomadik-gpio";
 363                         reg =  <0x8000e180 0x80>;
 364                         interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
 365                         interrupt-controller;
 366                         #interrupt-cells = <2>;
 367                         st,supports-sleepmode;
 368                         gpio-controller;
 369                         #gpio-cells = <2>;
 370                         gpio-bank = <5>;
 371
 372                         clocks = <&prcc_pclk 3 8>;
 373                 };
 374
 375                 gpio6: gpio@8011e000 {
 376                         compatible = "stericsson,db8500-gpio",
 377                                 "st,nomadik-gpio";
 378                         reg =  <0x8011e000 0x80>;
 379                         interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
 380                         interrupt-controller;
 381                         #interrupt-cells = <2>;
 382                         st,supports-sleepmode;
 383                         gpio-controller;
 384                         #gpio-cells = <2>;
 385                         gpio-bank = <6>;
 386
 387                         clocks = <&prcc_pclk 2 11>;
 388                 };
 389
 390                 gpio7: gpio@8011e080 {
 391                         compatible = "stericsson,db8500-gpio",
 392                                 "st,nomadik-gpio";
 393                         reg =  <0x8011e080 0x80>;
 394                         interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
 395                         interrupt-controller;
 396                         #interrupt-cells = <2>;
 397                         st,supports-sleepmode;
 398                         gpio-controller;
 399                         #gpio-cells = <2>;
 400                         gpio-bank = <7>;
 401
 402                         clocks = <&prcc_pclk 2 11>;
 403                 };
 404
 405                 gpio8: gpio@a03fe000 {
 406                         compatible = "stericsson,db8500-gpio",
 407                                 "st,nomadik-gpio";
 408                         reg =  <0xa03fe000 0x80>;
 409                         interrupts = <0 127 IRQ_TYPE_LEVEL_HIGH>;
 410                         interrupt-controller;
 411                         #interrupt-cells = <2>;
 412                         st,supports-sleepmode;
 413                         gpio-controller;
 414                         #gpio-cells = <2>;
 415                         gpio-bank = <8>;
 416
 417                         clocks = <&prcc_pclk 5 1>;
 418                 };
 419
 420                 pinctrl {
 421                         compatible = "stericsson,db8500-pinctrl";
 422                         prcm = <&prcmu>;
 423                 };
 424
 425                 usb_per5@a03e0000 {
 426                         compatible = "stericsson,db8500-musb";
 427                         reg = <0xa03e0000 0x10000>;
 428                         interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 429                         interrupt-names = "mc";
 430
 431                         dr_mode = "otg";
 432
 433                         dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
 434                                <&dma 38 0 0x0>, /* Logical - MemToDev */
 435                                <&dma 37 0 0x2>, /* Logical - DevToMem */
 436                                <&dma 37 0 0x0>, /* Logical - MemToDev */
 437                                <&dma 36 0 0x2>, /* Logical - DevToMem */
 438                                <&dma 36 0 0x0>, /* Logical - MemToDev */
 439                                <&dma 19 0 0x2>, /* Logical - DevToMem */
 440                                <&dma 19 0 0x0>, /* Logical - MemToDev */
 441                                <&dma 18 0 0x2>, /* Logical - DevToMem */
 442                                <&dma 18 0 0x0>, /* Logical - MemToDev */
 443                                <&dma 17 0 0x2>, /* Logical - DevToMem */
 444                                <&dma 17 0 0x0>, /* Logical - MemToDev */
 445                                <&dma 16 0 0x2>, /* Logical - DevToMem */
 446                                <&dma 16 0 0x0>, /* Logical - MemToDev */
 447                                <&dma 39 0 0x2>, /* Logical - DevToMem */
 448                                <&dma 39 0 0x0>; /* Logical - MemToDev */
 449
 450                         dma-names = "iep_1_9",  "oep_1_9",
 451                                     "iep_2_10", "oep_2_10",
 452                                     "iep_3_11", "oep_3_11",
 453                                     "iep_4_12", "oep_4_12",
 454                                     "iep_5_13", "oep_5_13",
 455                                     "iep_6_14", "oep_6_14",
 456                                     "iep_7_15", "oep_7_15",
 457                                     "iep_8",    "oep_8";
 458
 459                         clocks = <&prcc_pclk 5 0>;
 460                 };
 461
 462                 dma: dma-controller@801C0000 {
 463                         compatible = "stericsson,db8500-dma40", "stericsson,dma40";
 464                         reg = <0x801C0000 0x1000 0x40010000 0x800>;
 465                         reg-names = "base", "lcpa";
 466                         interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 467
 468                         #dma-cells = <3>;
 469                         memcpy-channels = <56 57 58 59 60>;
 470
 471                         clocks = <&prcmu_clk PRCMU_DMACLK>;
 472                 };
 473
 474                 prcmu: prcmu@80157000 {
 475                         compatible = "stericsson,db8500-prcmu";
 476                         reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
 477                         reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
 478                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 479                         #address-cells = <1>;
 480                         #size-cells = <1>;
 481                         interrupt-controller;
 482                         #interrupt-cells = <2>;
 483                         ranges;
 484
 485                         prcmu-timer-4@80157450 {
 486                                 compatible = "stericsson,db8500-prcmu-timer-4";
 487                                 reg = <0x80157450 0xC>;
 488                         };
 489
 490                         cpufreq {
 491                                 compatible = "stericsson,cpufreq-ux500";
 492                                 clocks = <&prcmu_clk PRCMU_ARMSS>;
 493                                 clock-names = "armss";
 494                                 status = "disabled";
 495                         };
 496
 497                         thermal@801573c0 {
 498                                 compatible = "stericsson,db8500-thermal";
 499                                 reg = <0x801573c0 0x40>;
 500                                 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>,
 501                                              <22 IRQ_TYPE_LEVEL_HIGH>;
 502                                 interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
 503                                 status = "disabled";
 504                         };
 505
 506                         db8500-prcmu-regulators {
 507                                 compatible = "stericsson,db8500-prcmu-regulator";
 508
 509                                 // DB8500_REGULATOR_VAPE
 510                                 db8500_vape_reg: db8500_vape {
 511                                         regulator-compatible = "db8500_vape";
 512                                         regulator-always-on;
 513                                 };
 514
 515                                 // DB8500_REGULATOR_VARM
 516                                 db8500_varm_reg: db8500_varm {
 517                                         regulator-compatible = "db8500_varm";
 518                                 };
 519
 520                                 // DB8500_REGULATOR_VMODEM
 521                                 db8500_vmodem_reg: db8500_vmodem {
 522                                         regulator-compatible = "db8500_vmodem";
 523                                 };
 524
 525                                 // DB8500_REGULATOR_VPLL
 526                                 db8500_vpll_reg: db8500_vpll {
 527                                         regulator-compatible = "db8500_vpll";
 528                                 };
 529
 530                                 // DB8500_REGULATOR_VSMPS1
 531                                 db8500_vsmps1_reg: db8500_vsmps1 {
 532                                         regulator-compatible = "db8500_vsmps1";
 533                                 };
 534
 535                                 // DB8500_REGULATOR_VSMPS2
 536                                 db8500_vsmps2_reg: db8500_vsmps2 {
 537                                         regulator-compatible = "db8500_vsmps2";
 538                                 };
 539
 540                                 // DB8500_REGULATOR_VSMPS3
 541                                 db8500_vsmps3_reg: db8500_vsmps3 {
 542                                         regulator-compatible = "db8500_vsmps3";
 543                                 };
 544
 545                                 // DB8500_REGULATOR_VRF1
 546                                 db8500_vrf1_reg: db8500_vrf1 {
 547                                         regulator-compatible = "db8500_vrf1";
 548                                 };
 549
 550                                 // DB8500_REGULATOR_SWITCH_SVAMMDSP
 551                                 db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
 552                                         regulator-compatible = "db8500_sva_mmdsp";
 553                                 };
 554
 555                                 // DB8500_REGULATOR_SWITCH_SVAMMDSPRET
 556                                 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
 557                                         regulator-compatible = "db8500_sva_mmdsp_ret";
 558                                 };
 559
 560                                 // DB8500_REGULATOR_SWITCH_SVAPIPE
 561                                 db8500_sva_pipe_reg: db8500_sva_pipe {
 562                                         regulator-compatible = "db8500_sva_pipe";
 563                                 };
 564
 565                                 // DB8500_REGULATOR_SWITCH_SIAMMDSP
 566                                 db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
 567                                         regulator-compatible = "db8500_sia_mmdsp";
 568                                 };
 569
 570                                 // DB8500_REGULATOR_SWITCH_SIAMMDSPRET
 571                                 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
 572                                 };
 573
 574                                 // DB8500_REGULATOR_SWITCH_SIAPIPE
 575                                 db8500_sia_pipe_reg: db8500_sia_pipe {
 576                                         regulator-compatible = "db8500_sia_pipe";
 577                                 };
 578
 579                                 // DB8500_REGULATOR_SWITCH_SGA
 580                                 db8500_sga_reg: db8500_sga {
 581                                         regulator-compatible = "db8500_sga";
 582                                         vin-supply = <&db8500_vape_reg>;
 583                                 };
 584
 585                                 // DB8500_REGULATOR_SWITCH_B2R2_MCDE
 586                                 db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
 587                                         regulator-compatible = "db8500_b2r2_mcde";
 588                                         vin-supply = <&db8500_vape_reg>;
 589                                 };
 590
 591                                 // DB8500_REGULATOR_SWITCH_ESRAM12
 592                                 db8500_esram12_reg: db8500_esram12 {
 593                                         regulator-compatible = "db8500_esram12";
 594                                 };
 595
 596                                 // DB8500_REGULATOR_SWITCH_ESRAM12RET
 597                                 db8500_esram12_ret_reg: db8500_esram12_ret {
 598                                         regulator-compatible = "db8500_esram12_ret";
 599                                 };
 600
 601                                 // DB8500_REGULATOR_SWITCH_ESRAM34
 602                                 db8500_esram34_reg: db8500_esram34 {
 603                                         regulator-compatible = "db8500_esram34";
 604                                 };
 605
 606                                 // DB8500_REGULATOR_SWITCH_ESRAM34RET
 607                                 db8500_esram34_ret_reg: db8500_esram34_ret {
 608                                         regulator-compatible = "db8500_esram34_ret";
 609                                 };
 610                         };
 611
 612                         ab8500 {
 613                                 compatible = "stericsson,ab8500";
 614                                 interrupt-parent = <&intc>;
 615                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 616                                 interrupt-controller;
 617                                 #interrupt-cells = <2>;
 618
 619                                 ab8500_gpio: ab8500-gpio {
 620                                         gpio-controller;
 621                                         #gpio-cells = <2>;
 622                                 };
 623
 624                                 ab8500-rtc {
 625                                         compatible = "stericsson,ab8500-rtc";
 626                                         interrupts = <17 IRQ_TYPE_LEVEL_HIGH
 627                                                       18 IRQ_TYPE_LEVEL_HIGH>;
 628                                         interrupt-names = "60S", "ALARM";
 629                                 };
 630
 631                                 ab8500-gpadc {
 632                                         compatible = "stericsson,ab8500-gpadc";
 633                                         interrupts = <32 IRQ_TYPE_LEVEL_HIGH
 634                                                       39 IRQ_TYPE_LEVEL_HIGH>;
 635                                         interrupt-names = "HW_CONV_END", "SW_CONV_END";
 636                                         vddadc-supply = <&ab8500_ldo_tvout_reg>;
 637                                 };
 638
 639                                 ab8500_battery: ab8500_battery {
 640                                         stericsson,battery-type = "LIPO";
 641                                         thermistor-on-batctrl;
 642                                 };
 643
 644                                 ab8500_fg {
 645                                         compatible = "stericsson,ab8500-fg";
 646                                         battery    = <&ab8500_battery>;
 647                                 };
 648
 649                                 ab8500_btemp {
 650                                         compatible = "stericsson,ab8500-btemp";
 651                                         battery    = <&ab8500_battery>;
 652                                 };
 653
 654                                 ab8500_charger {
 655                                         compatible      = "stericsson,ab8500-charger";
 656                                         battery         = <&ab8500_battery>;
 657                                         vddadc-supply   = <&ab8500_ldo_tvout_reg>;
 658                                 };
 659
 660                                 ab8500_chargalg {
 661                                         compatible      = "stericsson,ab8500-chargalg";
 662                                         battery         = <&ab8500_battery>;
 663                                 };
 664
 665                                 ab8500_usb {
 666                                         compatible = "stericsson,ab8500-usb";
 667                                         interrupts = < 90 IRQ_TYPE_LEVEL_HIGH
 668                                                        96 IRQ_TYPE_LEVEL_HIGH
 669                                                        14 IRQ_TYPE_LEVEL_HIGH
 670                                                        15 IRQ_TYPE_LEVEL_HIGH
 671                                                        79 IRQ_TYPE_LEVEL_HIGH
 672                                                        74 IRQ_TYPE_LEVEL_HIGH
 673                                                        75 IRQ_TYPE_LEVEL_HIGH>;
 674                                         interrupt-names = "ID_WAKEUP_R",
 675                                                           "ID_WAKEUP_F",
 676                                                           "VBUS_DET_F",
 677                                                           "VBUS_DET_R",
 678                                                           "USB_LINK_STATUS",
 679                                                           "USB_ADP_PROBE_PLUG",
 680                                                           "USB_ADP_PROBE_UNPLUG";
 681                                         vddulpivio18-supply = <&ab8500_ldo_intcore_reg>;
 682                                         v-ape-supply = <&db8500_vape_reg>;
 683                                         musb_1v8-supply = <&db8500_vsmps2_reg>;
 684                                 };
 685
 686                                 ab8500-ponkey {
 687                                         compatible = "stericsson,ab8500-poweron-key";
 688                                         interrupts = <6 IRQ_TYPE_LEVEL_HIGH
 689                                                       7 IRQ_TYPE_LEVEL_HIGH>;
 690                                         interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
 691                                 };
 692
 693                                 ab8500-sysctrl {
 694                                         compatible = "stericsson,ab8500-sysctrl";
 695                                 };
 696
 697                                 ab8500-pwm {
 698                                         compatible = "stericsson,ab8500-pwm";
 699                                 };
 700
 701                                 ab8500-debugfs {
 702                                         compatible = "stericsson,ab8500-debug";
 703                                 };
 704
 705                                 codec: ab8500-codec {
 706                                         compatible = "stericsson,ab8500-codec";
 707
 708                                         V-AUD-supply = <&ab8500_ldo_audio_reg>;
 709                                         V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>;
 710                                         V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>;
 711                                         V-DMIC-supply = <&ab8500_ldo_dmic_reg>;
 712
 713                                         stericsson,earpeice-cmv = <950>; /* Units in mV. */
 714                                 };
 715
 716                                 ext_regulators: ab8500-ext-regulators {
 717                                         compatible = "stericsson,ab8500-ext-regulator";
 718
 719                                         ab8500_ext1_reg: ab8500_ext1 {
 720                                                 regulator-compatible = "ab8500_ext1";
 721                                                 regulator-min-microvolt = <1800000>;
 722                                                 regulator-max-microvolt = <1800000>;
 723                                                 regulator-boot-on;
 724                                                 regulator-always-on;
 725                                         };
 726
 727                                         ab8500_ext2_reg: ab8500_ext2 {
 728                                                 regulator-compatible = "ab8500_ext2";
 729                                                 regulator-min-microvolt = <1360000>;
 730                                                 regulator-max-microvolt = <1360000>;
 731                                                 regulator-boot-on;
 732                                                 regulator-always-on;
 733                                         };
 734
 735                                         ab8500_ext3_reg: ab8500_ext3 {
 736                                                 regulator-compatible = "ab8500_ext3";
 737                                                 regulator-min-microvolt = <3400000>;
 738                                                 regulator-max-microvolt = <3400000>;
 739                                                 regulator-boot-on;
 740                                         };
 741                                 };
 742
 743                                 ab8500-regulators {
 744                                         compatible = "stericsson,ab8500-regulator";
 745                                         vin-supply = <&ab8500_ext3_reg>;
 746
 747                                         // supplies to the display/camera
 748                                         ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
 749                                                 regulator-compatible = "ab8500_ldo_aux1";
 750                                                 regulator-min-microvolt = <2500000>;
 751                                                 regulator-max-microvolt = <2900000>;
 752                                                 regulator-boot-on;
 753                                                 /* BUG: If turned off MMC will be affected. */
 754                                                 regulator-always-on;
 755                                         };
 756
 757                                         // supplies to the on-board eMMC
 758                                         ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
 759                                                 regulator-compatible = "ab8500_ldo_aux2";
 760                                                 regulator-min-microvolt = <1100000>;
 761                                                 regulator-max-microvolt = <3300000>;
 762                                         };
 763
 764                                         // supply for VAUX3; SDcard slots
 765                                         ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
 766                                                 regulator-compatible = "ab8500_ldo_aux3";
 767                                                 regulator-min-microvolt = <1100000>;
 768                                                 regulator-max-microvolt = <3300000>;
 769                                         };
 770
 771                                         // supply for v-intcore12; VINTCORE12 LDO
 772                                         ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
 773                                                 regulator-compatible = "ab8500_ldo_intcore";
 774                                         };
 775
 776                                         // supply for tvout; gpadc; TVOUT LDO
 777                                         ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
 778                                                 regulator-compatible = "ab8500_ldo_tvout";
 779                                         };
 780
 781                                         // supply for ab8500-usb; USB LDO
 782                                         ab8500_ldo_usb_reg: ab8500_ldo_usb {
 783                                                 regulator-compatible = "ab8500_ldo_usb";
 784                                         };
 785
 786                                         // supply for ab8500-vaudio; VAUDIO LDO
 787                                         ab8500_ldo_audio_reg: ab8500_ldo_audio {
 788                                                 regulator-compatible = "ab8500_ldo_audio";
 789                                         };
 790
 791                                         // supply for v-anamic1 VAMIC1 LDO
 792                                         ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
 793                                                 regulator-compatible = "ab8500_ldo_anamic1";
 794                                         };
 795
 796                                         // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
 797                                         ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
 798                                                 regulator-compatible = "ab8500_ldo_anamic2";
 799                                         };
 800
 801                                         // supply for v-dmic; VDMIC LDO
 802                                         ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
 803                                                 regulator-compatible = "ab8500_ldo_dmic";
 804                                         };
 805
 806                                         // supply for U8500 CSI/DSI; VANA LDO
 807                                         ab8500_ldo_ana_reg: ab8500_ldo_ana {
 808                                                 regulator-compatible = "ab8500_ldo_ana";
 809                                         };
 810                                 };
 811                         };
 812                 };
 813
 814                 i2c@80004000 {
 815                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 816                         reg = <0x80004000 0x1000>;
 817                         interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
 818
 819                         #address-cells = <1>;
 820                         #size-cells = <0>;
 821                         v-i2c-supply = <&db8500_vape_reg>;
 822
 823                         clock-frequency = <400000>;
 824                         clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>;
 825                         clock-names = "i2cclk", "apb_pclk";
 826                         power-domains = <&pm_domains DOMAIN_VAPE>;
 827                 };
 828
 829                 i2c@80122000 {
 830                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 831                         reg = <0x80122000 0x1000>;
 832                         interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 833
 834                         #address-cells = <1>;
 835                         #size-cells = <0>;
 836                         v-i2c-supply = <&db8500_vape_reg>;
 837
 838                         clock-frequency = <400000>;
 839
 840                         clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>;
 841                         clock-names = "i2cclk", "apb_pclk";
 842                         power-domains = <&pm_domains DOMAIN_VAPE>;
 843                 };
 844
 845                 i2c@80128000 {
 846                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 847                         reg = <0x80128000 0x1000>;
 848                         interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 849
 850                         #address-cells = <1>;
 851                         #size-cells = <0>;
 852                         v-i2c-supply = <&db8500_vape_reg>;
 853
 854                         clock-frequency = <400000>;
 855
 856                         clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>;
 857                         clock-names = "i2cclk", "apb_pclk";
 858                         power-domains = <&pm_domains DOMAIN_VAPE>;
 859                 };
 860
 861                 i2c@80110000 {
 862                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 863                         reg = <0x80110000 0x1000>;
 864                         interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>;
 865
 866                         #address-cells = <1>;
 867                         #size-cells = <0>;
 868                         v-i2c-supply = <&db8500_vape_reg>;
 869
 870                         clock-frequency = <400000>;
 871
 872                         clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>;
 873                         clock-names = "i2cclk", "apb_pclk";
 874                         power-domains = <&pm_domains DOMAIN_VAPE>;
 875                 };
 876
 877                 i2c@8012a000 {
 878                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 879                         reg = <0x8012a000 0x1000>;
 880                         interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
 881
 882                         #address-cells = <1>;
 883                         #size-cells = <0>;
 884                         v-i2c-supply = <&db8500_vape_reg>;
 885
 886                         clock-frequency = <400000>;
 887
 888                         clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>;
 889                         clock-names = "i2cclk", "apb_pclk";
 890                         power-domains = <&pm_domains DOMAIN_VAPE>;
 891                 };
 892
 893                 ssp@80002000 {
 894                         compatible = "arm,pl022", "arm,primecell";
 895                         reg = <0x80002000 0x1000>;
 896                         interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 897                         #address-cells = <1>;
 898                         #size-cells = <0>;
 899                         clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>;
 900                         clock-names = "SSPCLK", "apb_pclk";
 901                         dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
 902                                <&dma 8 0 0x0>; /* Logical - MemToDev */
 903                         dma-names = "rx", "tx";
 904                         power-domains = <&pm_domains DOMAIN_VAPE>;
 905                 };
 906
 907                 ssp@80003000 {
 908                         compatible = "arm,pl022", "arm,primecell";
 909                         reg = <0x80003000 0x1000>;
 910                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 911                         #address-cells = <1>;
 912                         #size-cells = <0>;
 913                         clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>;
 914                         clock-names = "SSPCLK", "apb_pclk";
 915                         dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
 916                                <&dma 9 0 0x0>; /* Logical - MemToDev */
 917                         dma-names = "rx", "tx";
 918                         power-domains = <&pm_domains DOMAIN_VAPE>;
 919                 };
 920
 921                 spi@8011a000 {
 922                         compatible = "arm,pl022", "arm,primecell";
 923                         reg = <0x8011a000 0x1000>;
 924                         interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 925                         #address-cells = <1>;
 926                         #size-cells = <0>;
 927                         /* Same clock wired to kernel and pclk */
 928                         clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>;
 929                         clock-names = "SSPCLK", "apb_pclk";
 930                         dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */
 931                                <&dma 0 0 0x0>; /* Logical - MemToDev */
 932                         dma-names = "rx", "tx";
 933                         power-domains = <&pm_domains DOMAIN_VAPE>;
 934                 };
 935
 936                 spi@80112000 {
 937                         compatible = "arm,pl022", "arm,primecell";
 938                         reg = <0x80112000 0x1000>;
 939                         interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
 940                         #address-cells = <1>;
 941                         #size-cells = <0>;
 942                         /* Same clock wired to kernel and pclk */
 943                         clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>;
 944                         clock-names = "SSPCLK", "apb_pclk";
 945                         dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */
 946                                <&dma 35 0 0x0>; /* Logical - MemToDev */
 947                         dma-names = "rx", "tx";
 948                         power-domains = <&pm_domains DOMAIN_VAPE>;
 949                 };
 950
 951                 spi@80111000 {
 952                         compatible = "arm,pl022", "arm,primecell";
 953                         reg = <0x80111000 0x1000>;
 954                         interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 955                         #address-cells = <1>;
 956                         #size-cells = <0>;
 957                         /* Same clock wired to kernel and pclk */
 958                         clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>;
 959                         clock-names = "SSPCLK", "apb_pclk";
 960                         dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */
 961                                <&dma 33 0 0x0>; /* Logical - MemToDev */
 962                         dma-names = "rx", "tx";
 963                         power-domains = <&pm_domains DOMAIN_VAPE>;
 964                 };
 965
 966                 spi@80129000 {
 967                         compatible = "arm,pl022", "arm,primecell";
 968                         reg = <0x80129000 0x1000>;
 969                         interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
 970                         #address-cells = <1>;
 971                         #size-cells = <0>;
 972                         /* Same clock wired to kernel and pclk */
 973                         clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>;
 974                         clock-names = "SSPCLK", "apb_pclk";
 975                         dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */
 976                                <&dma 40 0 0x0>; /* Logical - MemToDev */
 977                         dma-names = "rx", "tx";
 978                         power-domains = <&pm_domains DOMAIN_VAPE>;
 979                 };
 980
 981                 uart@80120000 {
 982                         compatible = "arm,pl011", "arm,primecell";
 983                         reg = <0x80120000 0x1000>;
 984                         interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 985
 986                         dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
 987                                <&dma 13 0 0x0>; /* Logical - MemToDev */
 988                         dma-names = "rx", "tx";
 989
 990                         clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>;
 991                         clock-names = "uart", "apb_pclk";
 992
 993                         status = "disabled";
 994                 };
 995
 996                 uart@80121000 {
 997                         compatible = "arm,pl011", "arm,primecell";
 998                         reg = <0x80121000 0x1000>;
 999                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
1000
1001                         dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */
1002                                <&dma 12 0 0x0>; /* Logical - MemToDev */
1003                         dma-names = "rx", "tx";
1004
1005                         clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>;
1006                         clock-names = "uart", "apb_pclk";
1007
1008                         status = "disabled";
1009                 };
1010
1011                 uart@80007000 {
1012                         compatible = "arm,pl011", "arm,primecell";
1013                         reg = <0x80007000 0x1000>;
1014                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
1015
1016                         dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */
1017                                <&dma 11 0 0x0>; /* Logical - MemToDev */
1018                         dma-names = "rx", "tx";
1019
1020                         clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>;
1021                         clock-names = "uart", "apb_pclk";
1022
1023                         status = "disabled";
1024                 };
1025
1026                 sdi0_per1@80126000 {
1027                         compatible = "arm,pl18x", "arm,primecell";
1028                         reg = <0x80126000 0x1000>;
1029                         interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
1030
1031                         dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
1032                                <&dma 29 0 0x0>; /* Logical - MemToDev */
1033                         dma-names = "rx", "tx";
1034
1035                         clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
1036                         clock-names = "sdi", "apb_pclk";
1037                         power-domains = <&pm_domains DOMAIN_VAPE>;
1038
1039                         status = "disabled";
1040                 };
1041
1042                 sdi1_per2@80118000 {
1043                         compatible = "arm,pl18x", "arm,primecell";
1044                         reg = <0x80118000 0x1000>;
1045                         interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
1046
1047                         dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */
1048                                <&dma 32 0 0x0>; /* Logical - MemToDev */
1049                         dma-names = "rx", "tx";
1050
1051                         clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>;
1052                         clock-names = "sdi", "apb_pclk";
1053                         power-domains = <&pm_domains DOMAIN_VAPE>;
1054
1055                         status = "disabled";
1056                 };
1057
1058                 sdi2_per3@80005000 {
1059                         compatible = "arm,pl18x", "arm,primecell";
1060                         reg = <0x80005000 0x1000>;
1061                         interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
1062
1063                         dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */
1064                                <&dma 28 0 0x0>; /* Logical - MemToDev */
1065                         dma-names = "rx", "tx";
1066
1067                         clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>;
1068                         clock-names = "sdi", "apb_pclk";
1069                         power-domains = <&pm_domains DOMAIN_VAPE>;
1070
1071                         status = "disabled";
1072                 };
1073
1074                 sdi3_per2@80119000 {
1075                         compatible = "arm,pl18x", "arm,primecell";
1076                         reg = <0x80119000 0x1000>;
1077                         interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
1078
1079                         dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */
1080                                <&dma 41 0 0x0>; /* Logical - MemToDev */
1081                         dma-names = "rx", "tx";
1082
1083                         clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>;
1084                         clock-names = "sdi", "apb_pclk";
1085                         power-domains = <&pm_domains DOMAIN_VAPE>;
1086
1087                         status = "disabled";
1088                 };
1089
1090                 sdi4_per2@80114000 {
1091                         compatible = "arm,pl18x", "arm,primecell";
1092                         reg = <0x80114000 0x1000>;
1093                         interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
1094
1095                         dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */
1096                                <&dma 42 0 0x0>; /* Logical - MemToDev */
1097                         dma-names = "rx", "tx";
1098
1099                         clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>;
1100                         clock-names = "sdi", "apb_pclk";
1101                         power-domains = <&pm_domains DOMAIN_VAPE>;
1102
1103                         status = "disabled";
1104                 };
1105
1106                 sdi5_per3@80008000 {
1107                         compatible = "arm,pl18x", "arm,primecell";
1108                         reg = <0x80008000 0x1000>;
1109                         interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
1110
1111                         dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */
1112                                <&dma 43 0 0x0>; /* Logical - MemToDev */
1113                         dma-names = "rx", "tx";
1114
1115                         clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>;
1116                         clock-names = "sdi", "apb_pclk";
1117                         power-domains = <&pm_domains DOMAIN_VAPE>;
1118
1119                         status = "disabled";
1120                 };
1121
1122                 msp0: msp@80123000 {
1123                         compatible = "stericsson,ux500-msp-i2s";
1124                         reg = <0x80123000 0x1000>;
1125                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
1126                         v-ape-supply = <&db8500_vape_reg>;
1127
1128                         dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */
1129                                <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */
1130                         dma-names = "rx", "tx";
1131
1132                         clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>;
1133                         clock-names = "msp", "apb_pclk";
1134
1135                         status = "disabled";
1136                 };
1137
1138                 msp1: msp@80124000 {
1139                         compatible = "stericsson,ux500-msp-i2s";
1140                         reg = <0x80124000 0x1000>;
1141                         interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
1142                         v-ape-supply = <&db8500_vape_reg>;
1143
1144                         /* This DMA channel only exist on DB8500 v1 */
1145                         dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */
1146                         dma-names = "tx";
1147
1148                         clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>;
1149                         clock-names = "msp", "apb_pclk";
1150
1151                         status = "disabled";
1152                 };
1153
1154                 // HDMI sound
1155                 msp2: msp@80117000 {
1156                         compatible = "stericsson,ux500-msp-i2s";
1157                         reg = <0x80117000 0x1000>;
1158                         interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
1159                         v-ape-supply = <&db8500_vape_reg>;
1160
1161                         dmas = <&dma 14 0 0x12>, /* Logical  - DevToMem - HighPrio */
1162                                <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev
1163                                                     HighPrio - Fixed */
1164                         dma-names = "rx", "tx";
1165
1166                         clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>;
1167                         clock-names = "msp", "apb_pclk";
1168
1169                         status = "disabled";
1170                 };
1171
1172                 msp3: msp@80125000 {
1173                         compatible = "stericsson,ux500-msp-i2s";
1174                         reg = <0x80125000 0x1000>;
1175                         interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
1176                         v-ape-supply = <&db8500_vape_reg>;
1177
1178                         /* This DMA channel only exist on DB8500 v2 */
1179                         dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */
1180                         dma-names = "rx";
1181
1182                         clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>;
1183                         clock-names = "msp", "apb_pclk";
1184
1185                         status = "disabled";
1186                 };
1187
1188                 external-bus@50000000 {
1189                         compatible = "simple-bus";
1190                         reg = <0x50000000 0x4000000>;
1191                         #address-cells = <1>;
1192                         #size-cells = <1>;
1193                         ranges = <0 0x50000000 0x4000000>;
1194                         status = "disabled";
1195                 };
1196
1197                 cpufreq-cooling {
1198                         compatible = "stericsson,db8500-cpufreq-cooling";
1199                         status = "disabled";
1200                 };
1201
1202                 mcde@a0350000 {
1203                         compatible = "stericsson,mcde";
1204                         reg = <0xa0350000 0x1000>, /* MCDE */
1205                               <0xa0351000 0x1000>, /* DSI link 1 */
1206                               <0xa0352000 0x1000>, /* DSI link 2 */
1207                               <0xa0353000 0x1000>; /* DSI link 3 */
1208                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
1209                         clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */
1210                                  <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */
1211                                  <&prcmu_clk PRCMU_PLLDSI>, /* HDMI clock */
1212                                  <&prcmu_clk PRCMU_DSI0CLK>, /* DSI 0 */
1213                                  <&prcmu_clk PRCMU_DSI1CLK>, /* DSI 1 */
1214                                  <&prcmu_clk PRCMU_DSI0ESCCLK>, /* TVout clock 0 */
1215                                  <&prcmu_clk PRCMU_DSI1ESCCLK>, /* TVout clock 1 */
1216                                  <&prcmu_clk PRCMU_DSI2ESCCLK>; /* TVout clock 2 */
1217                 };
1218
1219                 cryp@a03cb000 {
1220                         compatible = "stericsson,ux500-cryp";
1221                         reg = <0xa03cb000 0x1000>;
1222                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
1223
1224                         v-ape-supply = <&db8500_vape_reg>;
1225                         clocks = <&prcc_pclk 6 1>;
1226                 };
1227
1228                 hash@a03c2000 {
1229                         compatible = "stericsson,ux500-hash";
1230                         reg = <0xa03c2000 0x1000>;
1231
1232                         v-ape-supply = <&db8500_vape_reg>;
1233                         clocks = <&prcc_pclk 6 2>;
1234                 };
1235         };
1236 };