2 * linux/arch/arm/boot/compressed/head.S
4 * Copyright (C) 1996-2002 Russell King
5 * Copyright (C) 2004 Hyok S. Choi (MPU support)
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/linkage.h>
16 * Note that these macros must not contain any code which is not
17 * 100% relocatable. Any attempt to do so will result in a crash.
18 * Please select one of the following when turning on debugging.
22 #if defined(CONFIG_DEBUG_ICEDCC)
28 mcr p14, 0, \ch, c0, c5, 0
34 mcr p14, 0, \ch, c0, c1, 0
40 #include <asm/arch/debug-macro.S>
46 #if defined(CONFIG_ARCH_SA1100)
48 mov \rb, #0x80000000 @ physical base address
49 #ifdef CONFIG_DEBUG_LL_SER3
50 add \rb, \rb, #0x00050000 @ Ser3
52 add \rb, \rb, #0x00010000 @ Ser1
55 #elif defined(CONFIG_ARCH_OMAP2)
57 mov \rb, #0x48000000 @ physical base address
58 add \rb, \rb, #0x0006a000
59 #ifdef CONFIG_OMAP_LL_DEBUG_UART2
60 add \rb, \rb, #0x00002000
62 #ifdef CONFIG_OMAP_LL_DEBUG_UART3
63 add \rb, \rb, #0x00004000
69 #elif defined(CONFIG_ARCH_IOP331)
72 orr \rb, \rb, #0x00ff0000
73 orr \rb, \rb, #0x0000f700 @ location of the UART
75 #elif defined(CONFIG_ARCH_S3C2410)
78 add \rb, \rb, #0x4000 * CONFIG_S3C2410_LOWLEVEL_UART_PORT
99 .macro debug_reloc_start
102 kphex r6, 8 /* processor id */
104 kphex r7, 8 /* architecture id */
106 mrc p15, 0, r0, c1, c0
107 kphex r0, 8 /* control reg */
109 kphex r5, 8 /* decompressed kernel start */
111 kphex r9, 8 /* decompressed kernel end */
113 kphex r4, 8 /* kernel execution address */
118 .macro debug_reloc_end
120 kphex r5, 8 /* end of kernel */
123 bl memdump /* dump 256 bytes at start of kernel */
127 .section ".start", #alloc, #execinstr
129 * sort out different calling conventions
133 .type start,#function
139 .word 0x016f2818 @ Magic numbers to help the loader
140 .word start @ absolute load/run zImage address
141 .word _edata @ zImage end address
142 1: mov r7, r1 @ save architecture ID
143 mov r8, r2 @ save atags pointer
145 #ifndef __ARM_ARCH_2__
147 * Booting from Angel - need to enter SVC mode and disable
148 * FIQs/IRQs (numeric definitions from angel arm.h source).
149 * We only do this if we were in user mode on entry.
151 mrs r2, cpsr @ get current mode
152 tst r2, #3 @ not user?
154 mov r0, #0x17 @ angel_SWIreason_EnterSVC
155 swi 0x123456 @ angel_SWI_ARM
157 mrs r2, cpsr @ turn off interrupts to
158 orr r2, r2, #0xc0 @ prevent angel from running
161 teqp pc, #0x0c000003 @ turn off interrupts
165 * Note that some cache flushing and other stuff may
166 * be needed here - is there an Angel SWI call for this?
170 * some architecture specific code can be inserted
171 * by the linker here, but it should preserve r7, r8, and r9.
176 ldmia r0, {r1, r2, r3, r4, r5, r6, ip, sp}
177 subs r0, r0, r1 @ calculate the delta offset
179 @ if delta is zero, we are
180 beq not_relocated @ running at the address we
184 * We're running at a different address. We need to fix
185 * up various pointers:
186 * r5 - zImage base address
194 #ifndef CONFIG_ZBOOT_ROM
196 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
197 * we need to fix up pointers into the BSS region.
207 * Relocate all entries in the GOT table.
209 1: ldr r1, [r6, #0] @ relocate entries in the GOT
210 add r1, r1, r0 @ table. This fixes up the
211 str r1, [r6], #4 @ C references.
217 * Relocate entries in the GOT table. We only relocate
218 * the entries that are outside the (relocated) BSS region.
220 1: ldr r1, [r6, #0] @ relocate entries in the GOT
221 cmp r1, r2 @ entry < bss_start ||
222 cmphs r3, r1 @ _end < entry
223 addlo r1, r1, r0 @ table. This fixes up the
224 str r1, [r6], #4 @ C references.
229 not_relocated: mov r0, #0
230 1: str r0, [r2], #4 @ clear bss
238 * The C runtime environment should now be setup
239 * sufficiently. Turn the cache on, set up some
240 * pointers, and start decompressing.
244 mov r1, sp @ malloc space above stack
245 add r2, sp, #0x10000 @ 64k max
248 * Check to see if we will overwrite ourselves.
249 * r4 = final kernel address
250 * r5 = start of this image
251 * r2 = end of malloc space (and therefore this image)
254 * r4 + image length <= r5 -> OK
258 add r0, r4, #4096*1024 @ 4MB largest kernel size
262 mov r5, r2 @ decompress after malloc space
268 bic r0, r0, #127 @ align the kernel length
270 * r0 = decompressed kernel length
272 * r4 = kernel execution address
273 * r5 = decompressed kernel start
275 * r7 = architecture ID
279 add r1, r5, r0 @ end of decompressed kernel
283 1: ldmia r2!, {r9 - r14} @ copy relocation code
284 stmia r1!, {r9 - r14}
285 ldmia r2!, {r9 - r14}
286 stmia r1!, {r9 - r14}
291 add pc, r5, r0 @ call relocation code
294 * We're not in danger of overwriting ourselves. Do this the simple way.
296 * r4 = kernel execution address
297 * r7 = architecture ID
299 wont_overwrite: mov r0, r4
306 .word __bss_start @ r2
310 .word _got_start @ r6
312 .word user_stack+4096 @ sp
313 LC1: .word reloc_end - reloc_start
316 #ifdef CONFIG_ARCH_RPC
318 params: ldr r0, =params_phys
325 * Turn on the cache. We need to setup some page tables so that we
326 * can have both the I and D caches on.
328 * We place the page tables 16k down from the kernel execution address,
329 * and we hope that nothing else is using it. If we're using it, we
333 * r4 = kernel execution address
335 * r7 = architecture number
337 * r9 = run-time address of "start" (???)
339 * r1, r2, r3, r9, r10, r12 corrupted
340 * This routine must preserve:
344 cache_on: mov r3, #8 @ cache_on function
348 * Initialize the highest priority protection region, PR7
349 * to cover all 32bit address and cacheable and bufferable.
351 __armv4_mpu_cache_on:
352 mov r0, #0x3f @ 4G, the whole
353 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
354 mcr p15, 0, r0, c6, c7, 1
357 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
358 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
359 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
362 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
363 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
366 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
367 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
368 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
369 mrc p15, 0, r0, c1, c0, 0 @ read control reg
370 @ ...I .... ..D. WC.M
371 orr r0, r0, #0x002d @ .... .... ..1. 11.1
372 orr r0, r0, #0x1000 @ ...1 .... .... ....
374 mcr p15, 0, r0, c1, c0, 0 @ write control reg
377 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
378 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
381 __armv3_mpu_cache_on:
382 mov r0, #0x3f @ 4G, the whole
383 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
386 mcr p15, 0, r0, c2, c0, 0 @ cache on
387 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
390 mcr p15, 0, r0, c5, c0, 0 @ access permission
393 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
394 mrc p15, 0, r0, c1, c0, 0 @ read control reg
395 @ .... .... .... WC.M
396 orr r0, r0, #0x000d @ .... .... .... 11.1
398 mcr p15, 0, r0, c1, c0, 0 @ write control reg
400 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
403 __setup_mmu: sub r3, r4, #16384 @ Page directory size
404 bic r3, r3, #0xff @ Align the pointer
407 * Initialise the page tables, turning on the cacheable and bufferable
408 * bits for the RAM area only.
412 mov r9, r9, lsl #18 @ start of RAM
413 add r10, r9, #0x10000000 @ a reasonable RAM size
417 1: cmp r1, r9 @ if virt > start of RAM
418 orrhs r1, r1, #0x0c @ set cacheable, bufferable
419 cmp r1, r10 @ if virt > end of RAM
420 bichs r1, r1, #0x0c @ clear cacheable, bufferable
421 str r1, [r0], #4 @ 1:1 mapping
426 * If ever we are running from Flash, then we surely want the cache
427 * to be enabled also for our execution instance... We map 2MB of it
428 * so there is no map overlap problem for up to 1 MB compressed kernel.
429 * If the execution is in RAM then we would only be duplicating the above.
434 orr r1, r1, r2, lsl #20
435 add r0, r3, r2, lsl #2
441 __armv4_mmu_cache_on:
445 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
446 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
447 mrc p15, 0, r0, c1, c0, 0 @ read control reg
448 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
450 bl __common_mmu_cache_on
452 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
459 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
460 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
462 bl __common_mmu_cache_on
464 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
467 __common_mmu_cache_on:
469 orr r0, r0, #0x000d @ Write buffer, mmu
472 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
473 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
475 .align 5 @ cache line aligned
476 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
477 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
478 sub pc, lr, r0, lsr #32 @ properly flush pipeline
481 * All code following this line is relocatable. It is relocated by
482 * the above code to the end of the decompressed kernel image and
483 * executed there. During this time, we have no stacks.
485 * r0 = decompressed kernel length
487 * r4 = kernel execution address
488 * r5 = decompressed kernel start
490 * r7 = architecture ID
495 reloc_start: add r9, r5, r0
500 ldmia r5!, {r0, r2, r3, r10 - r14} @ relocate kernel
501 stmia r1!, {r0, r2, r3, r10 - r14}
508 call_kernel: bl cache_clean_flush
510 mov r0, #0 @ must be zero
511 mov r1, r7 @ restore architecture number
512 mov r2, r8 @ restore atags pointer
513 mov pc, r4 @ call kernel
516 * Here follow the relocatable cache support functions for the
517 * various processors. This is a generic hook for locating an
518 * entry and jumping to an instruction at the specified offset
519 * from the start of the block. Please note this is all position
529 call_cache_fn: adr r12, proc_types
530 mrc p15, 0, r6, c0, c0 @ get processor ID
531 1: ldr r1, [r12, #0] @ get value
532 ldr r2, [r12, #4] @ get mask
533 eor r1, r1, r6 @ (real ^ match)
535 addeq pc, r12, r3 @ call cache function
540 * Table for cache operations. This is basically:
543 * - 'cache on' method instruction
544 * - 'cache off' method instruction
545 * - 'cache flush' method instruction
547 * We match an entry using: ((real_id ^ match) & mask) == 0
549 * Writethrough caches generally only need 'on' and 'off'
550 * methods. Writeback caches _must_ have the flush method
553 .type proc_types,#object
555 .word 0x41560600 @ ARM6/610
557 b __arm6_mmu_cache_off @ works, but slow
558 b __arm6_mmu_cache_off
560 @ b __arm6_mmu_cache_on @ untested
561 @ b __arm6_mmu_cache_off
562 @ b __armv3_mmu_cache_flush
564 .word 0x00000000 @ old ARM ID
570 .word 0x41007000 @ ARM7/710
572 b __arm7_mmu_cache_off
573 b __arm7_mmu_cache_off
576 .word 0x41807200 @ ARM720T (writethrough)
578 b __armv4_mmu_cache_on
579 b __armv4_mmu_cache_off
582 .word 0x41007400 @ ARM74x
584 b __armv3_mpu_cache_on
585 b __armv3_mpu_cache_off
586 b __armv3_mpu_cache_flush
588 .word 0x41009400 @ ARM94x
590 b __armv4_mpu_cache_on
591 b __armv4_mpu_cache_off
592 b __armv4_mpu_cache_flush
594 .word 0x00007000 @ ARM7 IDs
600 @ Everything from here on will be the new ID system.
602 .word 0x4401a100 @ sa110 / sa1100
604 b __armv4_mmu_cache_on
605 b __armv4_mmu_cache_off
606 b __armv4_mmu_cache_flush
608 .word 0x6901b110 @ sa1110
610 b __armv4_mmu_cache_on
611 b __armv4_mmu_cache_off
612 b __armv4_mmu_cache_flush
614 @ These match on the architecture ID
616 .word 0x00020000 @ ARMv4T
618 b __armv4_mmu_cache_on
619 b __armv4_mmu_cache_off
620 b __armv4_mmu_cache_flush
622 .word 0x00050000 @ ARMv5TE
624 b __armv4_mmu_cache_on
625 b __armv4_mmu_cache_off
626 b __armv4_mmu_cache_flush
628 .word 0x00060000 @ ARMv5TEJ
630 b __armv4_mmu_cache_on
631 b __armv4_mmu_cache_off
632 b __armv4_mmu_cache_flush
634 .word 0x0007b000 @ ARMv6
636 b __armv4_mmu_cache_on
637 b __armv4_mmu_cache_off
638 b __armv6_mmu_cache_flush
640 .word 0 @ unrecognised type
646 .size proc_types, . - proc_types
649 * Turn off the Cache and MMU. ARMv3 does not support
650 * reading the control register, but ARMv4 does.
652 * On entry, r6 = processor ID
653 * On exit, r0, r1, r2, r3, r12 corrupted
654 * This routine must preserve: r4, r6, r7
657 cache_off: mov r3, #12 @ cache_off function
660 __armv4_mpu_cache_off:
661 mrc p15, 0, r0, c1, c0
663 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
665 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
666 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
667 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
670 __armv3_mpu_cache_off:
671 mrc p15, 0, r0, c1, c0
673 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
675 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
678 __armv4_mmu_cache_off:
679 mrc p15, 0, r0, c1, c0
681 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
683 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
684 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
687 __arm6_mmu_cache_off:
688 mov r0, #0x00000030 @ ARM6 control reg.
689 b __armv3_mmu_cache_off
691 __arm7_mmu_cache_off:
692 mov r0, #0x00000070 @ ARM7 control reg.
693 b __armv3_mmu_cache_off
695 __armv3_mmu_cache_off:
696 mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off
698 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
699 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
703 * Clean and flush the cache to maintain consistency.
708 * r1, r2, r3, r11, r12 corrupted
709 * This routine must preserve:
717 __armv4_mpu_cache_flush:
720 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
721 mov r1, #7 << 5 @ 8 segments
722 1: orr r3, r1, #63 << 26 @ 64 entries
723 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
724 subs r3, r3, #1 << 26
725 bcs 2b @ entries 63 to 0
727 bcs 1b @ segments 7 to 0
730 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
731 mcr p15, 0, ip, c7, c10, 4 @ drain WB
735 __armv6_mmu_cache_flush:
737 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
738 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
739 mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
740 mcr p15, 0, r1, c7, c10, 4 @ drain WB
743 __armv4_mmu_cache_flush:
744 mov r2, #64*1024 @ default: 32K dcache size (*2)
745 mov r11, #32 @ default: 32 byte line size
746 mrc p15, 0, r3, c0, c0, 1 @ read cache type
747 teq r3, r6 @ cache ID register present?
752 mov r2, r2, lsl r1 @ base dcache size *2
753 tst r3, #1 << 14 @ test M bit
754 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
758 mov r11, r11, lsl r3 @ cache line size in bytes
760 bic r1, pc, #63 @ align to longest cache line
762 1: ldr r3, [r1], r11 @ s/w flush D cache
766 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
767 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
768 mcr p15, 0, r1, c7, c10, 4 @ drain WB
771 __armv3_mmu_cache_flush:
772 __armv3_mpu_cache_flush:
774 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
778 * Various debugging routines for printing hex characters and
779 * memory, which again must be relocatable.
782 .type phexbuf,#object
784 .size phexbuf, . - phexbuf
786 phex: adr r3, phexbuf
823 2: mov r0, r11, lsl #2
831 ldr r0, [r12, r11, lsl #2]
852 .section ".stack", "w"
853 user_stack: .space 4096