5 select HAVE_DMA_API_DEBUG
6 select HAVE_IDE if PCI || ISA || PCMCIA
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
12 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
14 select HAVE_KPROBES if !XIP_KERNEL
15 select HAVE_KRETPROBES if (HAVE_KPROBES)
16 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
17 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
18 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
19 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
20 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
21 select HAVE_GENERIC_DMA_COHERENT
22 select HAVE_KERNEL_GZIP
23 select HAVE_KERNEL_LZO
24 select HAVE_KERNEL_LZMA
27 select HAVE_PERF_EVENTS
28 select PERF_USE_VMALLOC
29 select HAVE_REGS_AND_STACK_ACCESS_API
30 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
31 select HAVE_C_RECORDMCOUNT
32 select HAVE_GENERIC_HARDIRQS
33 select GENERIC_IRQ_SHOW
34 select CPU_PM if (SUSPEND || CPU_IDLE)
35 select GENERIC_PCI_IOMAP
36 select HAVE_BPF_JIT if NET
38 The ARM series is a line of low-power-consumption RISC chip designs
39 licensed by ARM Ltd and targeted at embedded applications and
40 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
41 manufactured, but legacy ARM-based PC hardware remains popular in
42 Europe. There is an ARM Linux project with a web page at
43 <http://www.arm.linux.org.uk/>.
45 config ARM_HAS_SG_CHAIN
54 config SYS_SUPPORTS_APM_EMULATION
60 config ARCH_USES_GETTIMEOFFSET
64 config GENERIC_CLOCKEVENTS
67 config GENERIC_CLOCKEVENTS_BROADCAST
69 depends on GENERIC_CLOCKEVENTS
78 select GENERIC_ALLOCATOR
89 The Extended Industry Standard Architecture (EISA) bus was
90 developed as an open alternative to the IBM MicroChannel bus.
92 The EISA bus provided some of the features of the IBM MicroChannel
93 bus while maintaining backward compatibility with cards made for
94 the older ISA bus. The EISA bus saw limited use between 1988 and
95 1995 when it was made obsolete by the PCI bus.
97 Say Y here if you are building a kernel for an EISA-based machine.
107 MicroChannel Architecture is found in some IBM PS/2 machines and
108 laptops. It is a bus system similar to PCI or ISA. See
109 <file:Documentation/mca.txt> (and especially the web page given
110 there) before attempting to build an MCA bus kernel.
112 config STACKTRACE_SUPPORT
116 config HAVE_LATENCYTOP_SUPPORT
121 config LOCKDEP_SUPPORT
125 config TRACE_IRQFLAGS_SUPPORT
129 config HARDIRQS_SW_RESEND
133 config GENERIC_IRQ_PROBE
137 config GENERIC_LOCKBREAK
140 depends on SMP && PREEMPT
142 config RWSEM_GENERIC_SPINLOCK
146 config RWSEM_XCHGADD_ALGORITHM
149 config ARCH_HAS_ILOG2_U32
152 config ARCH_HAS_ILOG2_U64
155 config ARCH_HAS_CPUFREQ
158 Internal node to signify that the ARCH has CPUFREQ support
159 and that the relevant menu configurations are displayed for
162 config ARCH_HAS_CPU_IDLE_WAIT
165 config GENERIC_HWEIGHT
169 config GENERIC_CALIBRATE_DELAY
173 config ARCH_MAY_HAVE_PC_FDC
179 config NEED_DMA_MAP_STATE
182 config ARCH_HAS_DMA_SET_COHERENT_MASK
185 config GENERIC_ISA_DMA
191 config NEED_RET_TO_USER
199 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
200 default DRAM_BASE if REMAP_VECTORS_TO_RAM
203 The base address of exception vectors.
205 config ARM_PATCH_PHYS_VIRT
206 bool "Patch physical to virtual translations at runtime" if EMBEDDED
208 depends on !XIP_KERNEL && MMU
209 depends on !ARCH_REALVIEW || !SPARSEMEM
211 Patch phys-to-virt and virt-to-phys translation functions at
212 boot and module load time according to the position of the
213 kernel in system memory.
215 This can only be used with non-XIP MMU kernels where the base
216 of physical memory is at a 16MB boundary.
218 Only disable this option if you know that you do not require
219 this feature (eg, building a kernel for a single machine) and
220 you need to shrink the kernel to the minimal size.
222 config NEED_MACH_IO_H
225 Select this when mach/io.h is required to provide special
226 definitions for this platform. The need for mach/io.h should
227 be avoided when possible.
229 config NEED_MACH_MEMORY_H
232 Select this when mach/memory.h is required to provide special
233 definitions for this platform. The need for mach/memory.h should
234 be avoided when possible.
237 hex "Physical address of main memory" if MMU
238 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
239 default DRAM_BASE if !MMU
241 Please provide the physical address corresponding to the
242 location of main memory in your system.
248 source "init/Kconfig"
250 source "kernel/Kconfig.freezer"
255 bool "MMU-based Paged Memory Management Support"
258 Select if you want MMU-based virtualised addressing space
259 support by paged memory management. If unsure, say 'Y'.
262 # The "ARM system type" choice list is ordered alphabetically by option
263 # text. Please add new entries in the option alphabetic order.
266 prompt "ARM system type"
267 default ARCH_VERSATILE
269 config ARCH_INTEGRATOR
270 bool "ARM Ltd. Integrator family"
272 select ARCH_HAS_CPUFREQ
274 select HAVE_MACH_CLKDEV
277 select GENERIC_CLOCKEVENTS
278 select PLAT_VERSATILE
279 select PLAT_VERSATILE_FPGA_IRQ
280 select NEED_MACH_IO_H
281 select NEED_MACH_MEMORY_H
284 Support for ARM's Integrator platform.
287 bool "ARM Ltd. RealView family"
290 select HAVE_MACH_CLKDEV
292 select GENERIC_CLOCKEVENTS
293 select ARCH_WANT_OPTIONAL_GPIOLIB
294 select PLAT_VERSATILE
295 select PLAT_VERSATILE_CLCD
296 select ARM_TIMER_SP804
297 select GPIO_PL061 if GPIOLIB
298 select NEED_MACH_MEMORY_H
300 This enables support for ARM Ltd RealView boards.
302 config ARCH_VERSATILE
303 bool "ARM Ltd. Versatile family"
307 select HAVE_MACH_CLKDEV
309 select GENERIC_CLOCKEVENTS
310 select ARCH_WANT_OPTIONAL_GPIOLIB
311 select PLAT_VERSATILE
312 select PLAT_VERSATILE_CLCD
313 select PLAT_VERSATILE_FPGA_IRQ
314 select ARM_TIMER_SP804
316 This enables support for ARM Ltd Versatile board.
319 bool "ARM Ltd. Versatile Express family"
320 select ARCH_WANT_OPTIONAL_GPIOLIB
322 select ARM_TIMER_SP804
324 select HAVE_MACH_CLKDEV
325 select GENERIC_CLOCKEVENTS
327 select HAVE_PATA_PLATFORM
330 select PLAT_VERSATILE
331 select PLAT_VERSATILE_CLCD
333 This enables support for the ARM Ltd Versatile Express boards.
337 select ARCH_REQUIRE_GPIOLIB
341 select NEED_MACH_IO_H if PCCARD
343 This enables support for systems based on the Atmel AT91RM9200,
347 bool "Broadcom BCMRING"
351 select ARM_TIMER_SP804
353 select GENERIC_CLOCKEVENTS
354 select ARCH_WANT_OPTIONAL_GPIOLIB
356 Support for Broadcom's BCMRing platform.
359 bool "Calxeda Highbank-based"
360 select ARCH_WANT_OPTIONAL_GPIOLIB
363 select ARM_TIMER_SP804
367 select GENERIC_CLOCKEVENTS
373 Support for the Calxeda Highbank SoC based boards.
376 bool "Cirrus Logic CLPS711x/EP721x-based"
378 select ARCH_USES_GETTIMEOFFSET
379 select NEED_MACH_MEMORY_H
381 Support for Cirrus Logic 711x/721x based boards.
384 bool "Cavium Networks CNS3XXX family"
386 select GENERIC_CLOCKEVENTS
388 select MIGHT_HAVE_CACHE_L2X0
389 select MIGHT_HAVE_PCI
390 select PCI_DOMAINS if PCI
392 Support for Cavium Networks CNS3XXX platform.
395 bool "Cortina Systems Gemini"
397 select ARCH_REQUIRE_GPIOLIB
398 select ARCH_USES_GETTIMEOFFSET
400 Support for the Cortina Systems Gemini family SoCs
403 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
406 select GENERIC_CLOCKEVENTS
408 select GENERIC_IRQ_CHIP
409 select MIGHT_HAVE_CACHE_L2X0
413 Support for CSR SiRFSoC ARM Cortex A9 Platform
420 select ARCH_USES_GETTIMEOFFSET
421 select NEED_MACH_IO_H
422 select NEED_MACH_MEMORY_H
424 This is an evaluation board for the StrongARM processor available
425 from Digital. It has limited hardware on-board, including an
426 Ethernet interface, two PCMCIA sockets, two serial ports and a
435 select ARCH_REQUIRE_GPIOLIB
436 select ARCH_HAS_HOLES_MEMORYMODEL
437 select ARCH_USES_GETTIMEOFFSET
438 select NEED_MACH_MEMORY_H
440 This enables support for the Cirrus EP93xx series of CPUs.
442 config ARCH_FOOTBRIDGE
446 select GENERIC_CLOCKEVENTS
448 select NEED_MACH_IO_H
449 select NEED_MACH_MEMORY_H
451 Support for systems based on the DC21285 companion chip
452 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
455 bool "Freescale MXC/iMX-based"
456 select GENERIC_CLOCKEVENTS
457 select ARCH_REQUIRE_GPIOLIB
460 select GENERIC_IRQ_CHIP
461 select MULTI_IRQ_HANDLER
463 Support for Freescale MXC/iMX-based family of processors
466 bool "Freescale MXS-based"
467 select GENERIC_CLOCKEVENTS
468 select ARCH_REQUIRE_GPIOLIB
472 select HAVE_CLK_PREPARE
475 Support for Freescale MXS-based family of processors
478 bool "Hilscher NetX based"
482 select GENERIC_CLOCKEVENTS
484 This enables support for systems based on the Hilscher NetX Soc
487 bool "Hynix HMS720x-based"
490 select ARCH_USES_GETTIMEOFFSET
492 This enables support for systems based on the Hynix HMS720x
500 select ARCH_SUPPORTS_MSI
502 select NEED_MACH_IO_H
503 select NEED_MACH_MEMORY_H
504 select NEED_RET_TO_USER
506 Support for Intel's IOP13XX (XScale) family of processors.
512 select NEED_MACH_IO_H
513 select NEED_RET_TO_USER
516 select ARCH_REQUIRE_GPIOLIB
518 Support for Intel's 80219 and IOP32X (XScale) family of
525 select NEED_MACH_IO_H
526 select NEED_RET_TO_USER
529 select ARCH_REQUIRE_GPIOLIB
531 Support for Intel's IOP33X (XScale) family of processors.
538 select ARCH_USES_GETTIMEOFFSET
539 select NEED_MACH_IO_H
540 select NEED_MACH_MEMORY_H
542 Support for Intel's IXP23xx (XScale) family of processors.
545 bool "IXP2400/2800-based"
549 select ARCH_USES_GETTIMEOFFSET
550 select NEED_MACH_IO_H
551 select NEED_MACH_MEMORY_H
553 Support for Intel's IXP2400/2800 (XScale) family of processors.
558 select ARCH_HAS_DMA_SET_COHERENT_MASK
562 select GENERIC_CLOCKEVENTS
563 select MIGHT_HAVE_PCI
564 select NEED_MACH_IO_H
565 select DMABOUNCE if PCI
567 Support for Intel's IXP4XX (XScale) family of processors.
573 select ARCH_REQUIRE_GPIOLIB
574 select GENERIC_CLOCKEVENTS
575 select NEED_MACH_IO_H
578 Support for the Marvell Dove SoC 88AP510
581 bool "Marvell Kirkwood"
584 select ARCH_REQUIRE_GPIOLIB
585 select GENERIC_CLOCKEVENTS
586 select NEED_MACH_IO_H
589 Support for the following Marvell Kirkwood series SoCs:
590 88F6180, 88F6192 and 88F6281.
596 select ARCH_REQUIRE_GPIOLIB
599 select USB_ARCH_HAS_OHCI
601 select GENERIC_CLOCKEVENTS
603 Support for the NXP LPC32XX family of processors
606 bool "Marvell MV78xx0"
609 select ARCH_REQUIRE_GPIOLIB
610 select GENERIC_CLOCKEVENTS
611 select NEED_MACH_IO_H
614 Support for the following Marvell MV78xx0 series SoCs:
622 select ARCH_REQUIRE_GPIOLIB
623 select GENERIC_CLOCKEVENTS
626 Support for the following Marvell Orion 5x series SoCs:
627 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
628 Orion-2 (5281), Orion-1-90 (6183).
631 bool "Marvell PXA168/910/MMP2"
633 select ARCH_REQUIRE_GPIOLIB
635 select GENERIC_CLOCKEVENTS
640 select GENERIC_ALLOCATOR
642 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
645 bool "Micrel/Kendin KS8695"
647 select ARCH_REQUIRE_GPIOLIB
648 select ARCH_USES_GETTIMEOFFSET
649 select NEED_MACH_MEMORY_H
651 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
652 System-on-Chip devices.
655 bool "Nuvoton W90X900 CPU"
657 select ARCH_REQUIRE_GPIOLIB
660 select GENERIC_CLOCKEVENTS
662 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
663 At present, the w90x900 has been renamed nuc900, regarding
664 the ARM series product line, you can login the following
665 link address to know more.
667 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
668 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
674 select GENERIC_CLOCKEVENTS
678 select MIGHT_HAVE_CACHE_L2X0
679 select NEED_MACH_IO_H if PCI
680 select ARCH_HAS_CPUFREQ
682 This enables support for NVIDIA Tegra based systems (Tegra APX,
683 Tegra 6xx and Tegra 2 series).
685 config ARCH_PICOXCELL
686 bool "Picochip picoXcell"
687 select ARCH_REQUIRE_GPIOLIB
688 select ARM_PATCH_PHYS_VIRT
692 select GENERIC_CLOCKEVENTS
699 This enables support for systems based on the Picochip picoXcell
700 family of Femtocell devices. The picoxcell support requires device tree
704 bool "Philips Nexperia PNX4008 Mobile"
707 select ARCH_USES_GETTIMEOFFSET
709 This enables support for Philips PNX4008 mobile platform.
712 bool "PXA2xx/PXA3xx-based"
715 select ARCH_HAS_CPUFREQ
718 select ARCH_REQUIRE_GPIOLIB
719 select GENERIC_CLOCKEVENTS
725 select MULTI_IRQ_HANDLER
726 select ARM_CPU_SUSPEND if PM
729 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
734 select GENERIC_CLOCKEVENTS
735 select ARCH_REQUIRE_GPIOLIB
738 Support for Qualcomm MSM/QSD based systems. This runs on the
739 apps processor of the MSM/QSD and depends on a shared memory
740 interface to the modem processor which runs the baseband
741 stack and controls some vital subsystems
742 (clock and power control, etc).
745 bool "Renesas SH-Mobile / R-Mobile"
748 select HAVE_MACH_CLKDEV
750 select GENERIC_CLOCKEVENTS
751 select MIGHT_HAVE_CACHE_L2X0
754 select MULTI_IRQ_HANDLER
755 select PM_GENERIC_DOMAINS if PM
756 select NEED_MACH_MEMORY_H
758 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
764 select ARCH_MAY_HAVE_PC_FDC
765 select HAVE_PATA_PLATFORM
768 select ARCH_SPARSEMEM_ENABLE
769 select ARCH_USES_GETTIMEOFFSET
771 select NEED_MACH_IO_H
772 select NEED_MACH_MEMORY_H
774 On the Acorn Risc-PC, Linux can support the internal IDE disk and
775 CD-ROM interface, serial and parallel port, and the floppy drive.
782 select ARCH_SPARSEMEM_ENABLE
784 select ARCH_HAS_CPUFREQ
786 select GENERIC_CLOCKEVENTS
789 select ARCH_REQUIRE_GPIOLIB
791 select NEED_MACH_MEMORY_H
794 Support for StrongARM 11x0 based boards.
797 bool "Samsung S3C24XX SoCs"
799 select ARCH_HAS_CPUFREQ
802 select ARCH_USES_GETTIMEOFFSET
803 select HAVE_S3C2410_I2C if I2C
804 select HAVE_S3C_RTC if RTC_CLASS
805 select HAVE_S3C2410_WATCHDOG if WATCHDOG
806 select NEED_MACH_IO_H
808 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
809 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
810 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
811 Samsung SMDK2410 development board (and derivatives).
814 bool "Samsung S3C64XX"
822 select ARCH_USES_GETTIMEOFFSET
823 select ARCH_HAS_CPUFREQ
824 select ARCH_REQUIRE_GPIOLIB
825 select SAMSUNG_CLKSRC
826 select SAMSUNG_IRQ_VIC_TIMER
827 select S3C_GPIO_TRACK
829 select USB_ARCH_HAS_OHCI
830 select SAMSUNG_GPIOLIB_4BIT
831 select HAVE_S3C2410_I2C if I2C
832 select HAVE_S3C2410_WATCHDOG if WATCHDOG
834 Samsung S3C64XX series based systems
837 bool "Samsung S5P6440 S5P6450"
843 select HAVE_S3C2410_WATCHDOG if WATCHDOG
844 select GENERIC_CLOCKEVENTS
845 select HAVE_S3C2410_I2C if I2C
846 select HAVE_S3C_RTC if RTC_CLASS
848 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
852 bool "Samsung S5PC100"
857 select ARCH_USES_GETTIMEOFFSET
858 select HAVE_S3C2410_I2C if I2C
859 select HAVE_S3C_RTC if RTC_CLASS
860 select HAVE_S3C2410_WATCHDOG if WATCHDOG
862 Samsung S5PC100 series based systems
865 bool "Samsung S5PV210/S5PC110"
867 select ARCH_SPARSEMEM_ENABLE
868 select ARCH_HAS_HOLES_MEMORYMODEL
873 select ARCH_HAS_CPUFREQ
874 select GENERIC_CLOCKEVENTS
875 select HAVE_S3C2410_I2C if I2C
876 select HAVE_S3C_RTC if RTC_CLASS
877 select HAVE_S3C2410_WATCHDOG if WATCHDOG
878 select NEED_MACH_MEMORY_H
880 Samsung S5PV210/S5PC110 series based systems
883 bool "SAMSUNG EXYNOS"
885 select ARCH_SPARSEMEM_ENABLE
886 select ARCH_HAS_HOLES_MEMORYMODEL
890 select ARCH_HAS_CPUFREQ
891 select GENERIC_CLOCKEVENTS
892 select HAVE_S3C_RTC if RTC_CLASS
893 select HAVE_S3C2410_I2C if I2C
894 select HAVE_S3C2410_WATCHDOG if WATCHDOG
895 select NEED_MACH_MEMORY_H
897 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
906 select ARCH_USES_GETTIMEOFFSET
907 select NEED_MACH_MEMORY_H
908 select NEED_MACH_IO_H
910 Support for the StrongARM based Digital DNARD machine, also known
911 as "Shark" (<http://www.shark-linux.de/shark.html>).
914 bool "ST-Ericsson U300 Series"
920 select ARM_PATCH_PHYS_VIRT
922 select GENERIC_CLOCKEVENTS
924 select HAVE_MACH_CLKDEV
926 select ARCH_REQUIRE_GPIOLIB
928 Support for ST-Ericsson U300 series mobile platforms.
931 bool "ST-Ericsson U8500 Series"
935 select GENERIC_CLOCKEVENTS
937 select ARCH_REQUIRE_GPIOLIB
938 select ARCH_HAS_CPUFREQ
940 select MIGHT_HAVE_CACHE_L2X0
942 Support for ST-Ericsson's Ux500 architecture
945 bool "STMicroelectronics Nomadik"
950 select GENERIC_CLOCKEVENTS
951 select MIGHT_HAVE_CACHE_L2X0
952 select ARCH_REQUIRE_GPIOLIB
954 Support for the Nomadik platform by ST-Ericsson
958 select GENERIC_CLOCKEVENTS
959 select ARCH_REQUIRE_GPIOLIB
963 select GENERIC_ALLOCATOR
964 select GENERIC_IRQ_CHIP
965 select ARCH_HAS_HOLES_MEMORYMODEL
967 Support for TI's DaVinci platform.
972 select ARCH_REQUIRE_GPIOLIB
973 select ARCH_HAS_CPUFREQ
975 select GENERIC_CLOCKEVENTS
976 select ARCH_HAS_HOLES_MEMORYMODEL
978 Support for TI's OMAP platform (OMAP1/2/3/4).
983 select ARCH_REQUIRE_GPIOLIB
986 select GENERIC_CLOCKEVENTS
989 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
992 bool "VIA/WonderMedia 85xx"
995 select ARCH_HAS_CPUFREQ
996 select GENERIC_CLOCKEVENTS
997 select ARCH_REQUIRE_GPIOLIB
1000 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
1003 bool "Xilinx Zynq ARM Cortex A9 Platform"
1005 select GENERIC_CLOCKEVENTS
1006 select CLKDEV_LOOKUP
1010 select MIGHT_HAVE_CACHE_L2X0
1013 Support for Xilinx Zynq ARM Cortex A9 Platform
1017 # This is sorted alphabetically by mach-* pathname. However, plat-*
1018 # Kconfigs may be included either alphabetically (according to the
1019 # plat- suffix) or along side the corresponding mach-* source.
1021 source "arch/arm/mach-at91/Kconfig"
1023 source "arch/arm/mach-bcmring/Kconfig"
1025 source "arch/arm/mach-clps711x/Kconfig"
1027 source "arch/arm/mach-cns3xxx/Kconfig"
1029 source "arch/arm/mach-davinci/Kconfig"
1031 source "arch/arm/mach-dove/Kconfig"
1033 source "arch/arm/mach-ep93xx/Kconfig"
1035 source "arch/arm/mach-footbridge/Kconfig"
1037 source "arch/arm/mach-gemini/Kconfig"
1039 source "arch/arm/mach-h720x/Kconfig"
1041 source "arch/arm/mach-integrator/Kconfig"
1043 source "arch/arm/mach-iop32x/Kconfig"
1045 source "arch/arm/mach-iop33x/Kconfig"
1047 source "arch/arm/mach-iop13xx/Kconfig"
1049 source "arch/arm/mach-ixp4xx/Kconfig"
1051 source "arch/arm/mach-ixp2000/Kconfig"
1053 source "arch/arm/mach-ixp23xx/Kconfig"
1055 source "arch/arm/mach-kirkwood/Kconfig"
1057 source "arch/arm/mach-ks8695/Kconfig"
1059 source "arch/arm/mach-lpc32xx/Kconfig"
1061 source "arch/arm/mach-msm/Kconfig"
1063 source "arch/arm/mach-mv78xx0/Kconfig"
1065 source "arch/arm/plat-mxc/Kconfig"
1067 source "arch/arm/mach-mxs/Kconfig"
1069 source "arch/arm/mach-netx/Kconfig"
1071 source "arch/arm/mach-nomadik/Kconfig"
1072 source "arch/arm/plat-nomadik/Kconfig"
1074 source "arch/arm/plat-omap/Kconfig"
1076 source "arch/arm/mach-omap1/Kconfig"
1078 source "arch/arm/mach-omap2/Kconfig"
1080 source "arch/arm/mach-orion5x/Kconfig"
1082 source "arch/arm/mach-pxa/Kconfig"
1083 source "arch/arm/plat-pxa/Kconfig"
1085 source "arch/arm/mach-mmp/Kconfig"
1087 source "arch/arm/mach-realview/Kconfig"
1089 source "arch/arm/mach-sa1100/Kconfig"
1091 source "arch/arm/plat-samsung/Kconfig"
1092 source "arch/arm/plat-s3c24xx/Kconfig"
1093 source "arch/arm/plat-s5p/Kconfig"
1095 source "arch/arm/plat-spear/Kconfig"
1097 source "arch/arm/mach-s3c24xx/Kconfig"
1099 source "arch/arm/mach-s3c2412/Kconfig"
1100 source "arch/arm/mach-s3c2440/Kconfig"
1104 source "arch/arm/mach-s3c64xx/Kconfig"
1107 source "arch/arm/mach-s5p64x0/Kconfig"
1109 source "arch/arm/mach-s5pc100/Kconfig"
1111 source "arch/arm/mach-s5pv210/Kconfig"
1113 source "arch/arm/mach-exynos/Kconfig"
1115 source "arch/arm/mach-shmobile/Kconfig"
1117 source "arch/arm/mach-tegra/Kconfig"
1119 source "arch/arm/mach-u300/Kconfig"
1121 source "arch/arm/mach-ux500/Kconfig"
1123 source "arch/arm/mach-versatile/Kconfig"
1125 source "arch/arm/mach-vexpress/Kconfig"
1126 source "arch/arm/plat-versatile/Kconfig"
1128 source "arch/arm/mach-vt8500/Kconfig"
1130 source "arch/arm/mach-w90x900/Kconfig"
1132 # Definitions to make life easier
1138 select GENERIC_CLOCKEVENTS
1143 select GENERIC_IRQ_CHIP
1148 config PLAT_VERSATILE
1151 config ARM_TIMER_SP804
1154 select HAVE_SCHED_CLOCK
1156 source arch/arm/mm/Kconfig
1160 default 16 if ARCH_EP93XX
1164 bool "Enable iWMMXt support"
1165 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1166 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1168 Enable support for iWMMXt context switching at run time if
1169 running on a CPU that supports it.
1173 depends on CPU_XSCALE
1177 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1178 (!ARCH_OMAP3 || OMAP3_EMU)
1182 config MULTI_IRQ_HANDLER
1185 Allow each machine to specify it's own IRQ handler at run time.
1188 source "arch/arm/Kconfig-nommu"
1191 config ARM_ERRATA_326103
1192 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1195 Executing a SWP instruction to read-only memory does not set bit 11
1196 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1197 treat the access as a read, preventing a COW from occurring and
1198 causing the faulting task to livelock.
1200 config ARM_ERRATA_411920
1201 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1202 depends on CPU_V6 || CPU_V6K
1204 Invalidation of the Instruction Cache operation can
1205 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1206 It does not affect the MPCore. This option enables the ARM Ltd.
1207 recommended workaround.
1209 config ARM_ERRATA_430973
1210 bool "ARM errata: Stale prediction on replaced interworking branch"
1213 This option enables the workaround for the 430973 Cortex-A8
1214 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1215 interworking branch is replaced with another code sequence at the
1216 same virtual address, whether due to self-modifying code or virtual
1217 to physical address re-mapping, Cortex-A8 does not recover from the
1218 stale interworking branch prediction. This results in Cortex-A8
1219 executing the new code sequence in the incorrect ARM or Thumb state.
1220 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1221 and also flushes the branch target cache at every context switch.
1222 Note that setting specific bits in the ACTLR register may not be
1223 available in non-secure mode.
1225 config ARM_ERRATA_458693
1226 bool "ARM errata: Processor deadlock when a false hazard is created"
1229 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1230 erratum. For very specific sequences of memory operations, it is
1231 possible for a hazard condition intended for a cache line to instead
1232 be incorrectly associated with a different cache line. This false
1233 hazard might then cause a processor deadlock. The workaround enables
1234 the L1 caching of the NEON accesses and disables the PLD instruction
1235 in the ACTLR register. Note that setting specific bits in the ACTLR
1236 register may not be available in non-secure mode.
1238 config ARM_ERRATA_460075
1239 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1242 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1243 erratum. Any asynchronous access to the L2 cache may encounter a
1244 situation in which recent store transactions to the L2 cache are lost
1245 and overwritten with stale memory contents from external memory. The
1246 workaround disables the write-allocate mode for the L2 cache via the
1247 ACTLR register. Note that setting specific bits in the ACTLR register
1248 may not be available in non-secure mode.
1250 config ARM_ERRATA_742230
1251 bool "ARM errata: DMB operation may be faulty"
1252 depends on CPU_V7 && SMP
1254 This option enables the workaround for the 742230 Cortex-A9
1255 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1256 between two write operations may not ensure the correct visibility
1257 ordering of the two writes. This workaround sets a specific bit in
1258 the diagnostic register of the Cortex-A9 which causes the DMB
1259 instruction to behave as a DSB, ensuring the correct behaviour of
1262 config ARM_ERRATA_742231
1263 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1264 depends on CPU_V7 && SMP
1266 This option enables the workaround for the 742231 Cortex-A9
1267 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1268 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1269 accessing some data located in the same cache line, may get corrupted
1270 data due to bad handling of the address hazard when the line gets
1271 replaced from one of the CPUs at the same time as another CPU is
1272 accessing it. This workaround sets specific bits in the diagnostic
1273 register of the Cortex-A9 which reduces the linefill issuing
1274 capabilities of the processor.
1276 config PL310_ERRATA_588369
1277 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1278 depends on CACHE_L2X0
1280 The PL310 L2 cache controller implements three types of Clean &
1281 Invalidate maintenance operations: by Physical Address
1282 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1283 They are architecturally defined to behave as the execution of a
1284 clean operation followed immediately by an invalidate operation,
1285 both performing to the same memory location. This functionality
1286 is not correctly implemented in PL310 as clean lines are not
1287 invalidated as a result of these operations.
1289 config ARM_ERRATA_720789
1290 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1293 This option enables the workaround for the 720789 Cortex-A9 (prior to
1294 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1295 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1296 As a consequence of this erratum, some TLB entries which should be
1297 invalidated are not, resulting in an incoherency in the system page
1298 tables. The workaround changes the TLB flushing routines to invalidate
1299 entries regardless of the ASID.
1301 config PL310_ERRATA_727915
1302 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1303 depends on CACHE_L2X0
1305 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1306 operation (offset 0x7FC). This operation runs in background so that
1307 PL310 can handle normal accesses while it is in progress. Under very
1308 rare circumstances, due to this erratum, write data can be lost when
1309 PL310 treats a cacheable write transaction during a Clean &
1310 Invalidate by Way operation.
1312 config ARM_ERRATA_743622
1313 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1316 This option enables the workaround for the 743622 Cortex-A9
1317 (r2p*) erratum. Under very rare conditions, a faulty
1318 optimisation in the Cortex-A9 Store Buffer may lead to data
1319 corruption. This workaround sets a specific bit in the diagnostic
1320 register of the Cortex-A9 which disables the Store Buffer
1321 optimisation, preventing the defect from occurring. This has no
1322 visible impact on the overall performance or power consumption of the
1325 config ARM_ERRATA_751472
1326 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1329 This option enables the workaround for the 751472 Cortex-A9 (prior
1330 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1331 completion of a following broadcasted operation if the second
1332 operation is received by a CPU before the ICIALLUIS has completed,
1333 potentially leading to corrupted entries in the cache or TLB.
1335 config PL310_ERRATA_753970
1336 bool "PL310 errata: cache sync operation may be faulty"
1337 depends on CACHE_PL310
1339 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1341 Under some condition the effect of cache sync operation on
1342 the store buffer still remains when the operation completes.
1343 This means that the store buffer is always asked to drain and
1344 this prevents it from merging any further writes. The workaround
1345 is to replace the normal offset of cache sync operation (0x730)
1346 by another offset targeting an unmapped PL310 register 0x740.
1347 This has the same effect as the cache sync operation: store buffer
1348 drain and waiting for all buffers empty.
1350 config ARM_ERRATA_754322
1351 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1354 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1355 r3p*) erratum. A speculative memory access may cause a page table walk
1356 which starts prior to an ASID switch but completes afterwards. This
1357 can populate the micro-TLB with a stale entry which may be hit with
1358 the new ASID. This workaround places two dsb instructions in the mm
1359 switching code so that no page table walks can cross the ASID switch.
1361 config ARM_ERRATA_754327
1362 bool "ARM errata: no automatic Store Buffer drain"
1363 depends on CPU_V7 && SMP
1365 This option enables the workaround for the 754327 Cortex-A9 (prior to
1366 r2p0) erratum. The Store Buffer does not have any automatic draining
1367 mechanism and therefore a livelock may occur if an external agent
1368 continuously polls a memory location waiting to observe an update.
1369 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1370 written polling loops from denying visibility of updates to memory.
1372 config ARM_ERRATA_364296
1373 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1374 depends on CPU_V6 && !SMP
1376 This options enables the workaround for the 364296 ARM1136
1377 r0p2 erratum (possible cache data corruption with
1378 hit-under-miss enabled). It sets the undocumented bit 31 in
1379 the auxiliary control register and the FI bit in the control
1380 register, thus disabling hit-under-miss without putting the
1381 processor into full low interrupt latency mode. ARM11MPCore
1384 config ARM_ERRATA_764369
1385 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1386 depends on CPU_V7 && SMP
1388 This option enables the workaround for erratum 764369
1389 affecting Cortex-A9 MPCore with two or more processors (all
1390 current revisions). Under certain timing circumstances, a data
1391 cache line maintenance operation by MVA targeting an Inner
1392 Shareable memory region may fail to proceed up to either the
1393 Point of Coherency or to the Point of Unification of the
1394 system. This workaround adds a DSB instruction before the
1395 relevant cache maintenance functions and sets a specific bit
1396 in the diagnostic control register of the SCU.
1398 config PL310_ERRATA_769419
1399 bool "PL310 errata: no automatic Store Buffer drain"
1400 depends on CACHE_L2X0
1402 On revisions of the PL310 prior to r3p2, the Store Buffer does
1403 not automatically drain. This can cause normal, non-cacheable
1404 writes to be retained when the memory system is idle, leading
1405 to suboptimal I/O performance for drivers using coherent DMA.
1406 This option adds a write barrier to the cpu_idle loop so that,
1407 on systems with an outer cache, the store buffer is drained
1412 source "arch/arm/common/Kconfig"
1422 Find out whether you have ISA slots on your motherboard. ISA is the
1423 name of a bus system, i.e. the way the CPU talks to the other stuff
1424 inside your box. Other bus systems are PCI, EISA, MicroChannel
1425 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1426 newer boards don't support it. If you have ISA, say Y, otherwise N.
1428 # Select ISA DMA controller support
1433 # Select ISA DMA interface
1438 bool "PCI support" if MIGHT_HAVE_PCI
1440 Find out whether you have a PCI motherboard. PCI is the name of a
1441 bus system, i.e. the way the CPU talks to the other stuff inside
1442 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1443 VESA. If you have PCI, say Y, otherwise N.
1449 config PCI_NANOENGINE
1450 bool "BSE nanoEngine PCI support"
1451 depends on SA1100_NANOENGINE
1453 Enable PCI on the BSE nanoEngine board.
1458 # Select the host bridge type
1459 config PCI_HOST_VIA82C505
1461 depends on PCI && ARCH_SHARK
1464 config PCI_HOST_ITE8152
1466 depends on PCI && MACH_ARMCORE
1470 source "drivers/pci/Kconfig"
1472 source "drivers/pcmcia/Kconfig"
1476 menu "Kernel Features"
1478 source "kernel/time/Kconfig"
1483 This option should be selected by machines which have an SMP-
1486 The only effect of this option is to make the SMP-related
1487 options available to the user for configuration.
1490 bool "Symmetric Multi-Processing"
1491 depends on CPU_V6K || CPU_V7
1492 depends on GENERIC_CLOCKEVENTS
1495 select USE_GENERIC_SMP_HELPERS
1496 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1498 This enables support for systems with more than one CPU. If you have
1499 a system with only one CPU, like most personal computers, say N. If
1500 you have a system with more than one CPU, say Y.
1502 If you say N here, the kernel will run on single and multiprocessor
1503 machines, but will use only one CPU of a multiprocessor machine. If
1504 you say Y here, the kernel will run on many, but not all, single
1505 processor machines. On a single processor machine, the kernel will
1506 run faster if you say N here.
1508 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1509 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1510 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1512 If you don't know what to do here, say N.
1515 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1516 depends on EXPERIMENTAL
1517 depends on SMP && !XIP_KERNEL
1520 SMP kernels contain instructions which fail on non-SMP processors.
1521 Enabling this option allows the kernel to modify itself to make
1522 these instructions safe. Disabling it allows about 1K of space
1525 If you don't know what to do here, say Y.
1527 config ARM_CPU_TOPOLOGY
1528 bool "Support cpu topology definition"
1529 depends on SMP && CPU_V7
1532 Support ARM cpu topology definition. The MPIDR register defines
1533 affinity between processors which is then used to describe the cpu
1534 topology of an ARM System.
1537 bool "Multi-core scheduler support"
1538 depends on ARM_CPU_TOPOLOGY
1540 Multi-core scheduler support improves the CPU scheduler's decision
1541 making when dealing with multi-core CPU chips at a cost of slightly
1542 increased overhead in some places. If unsure say N here.
1545 bool "SMT scheduler support"
1546 depends on ARM_CPU_TOPOLOGY
1548 Improves the CPU scheduler's decision making when dealing with
1549 MultiThreading at a cost of slightly increased overhead in some
1550 places. If unsure say N here.
1555 This option enables support for the ARM system coherency unit
1562 This options enables support for the ARM timer and watchdog unit
1565 prompt "Memory split"
1568 Select the desired split between kernel and user memory.
1570 If you are not absolutely sure what you are doing, leave this
1574 bool "3G/1G user/kernel split"
1576 bool "2G/2G user/kernel split"
1578 bool "1G/3G user/kernel split"
1583 default 0x40000000 if VMSPLIT_1G
1584 default 0x80000000 if VMSPLIT_2G
1588 int "Maximum number of CPUs (2-32)"
1594 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1595 depends on SMP && HOTPLUG && EXPERIMENTAL
1597 Say Y here to experiment with turning CPUs off and on. CPUs
1598 can be controlled through /sys/devices/system/cpu.
1601 bool "Use local timer interrupts"
1604 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1606 Enable support for local timers on SMP platforms, rather then the
1607 legacy IPI broadcast method. Local timers allows the system
1608 accounting to be spread across the timer interval, preventing a
1609 "thundering herd" at every timer tick.
1613 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1614 default 355 if ARCH_U8500
1615 default 264 if MACH_H4700
1618 Maximum number of GPIOs in the system.
1620 If unsure, leave the default value.
1622 source kernel/Kconfig.preempt
1626 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1627 ARCH_S5PV210 || ARCH_EXYNOS4
1628 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1629 default AT91_TIMER_HZ if ARCH_AT91
1630 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1633 config THUMB2_KERNEL
1634 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1635 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1637 select ARM_ASM_UNIFIED
1640 By enabling this option, the kernel will be compiled in
1641 Thumb-2 mode. A compiler/assembler that understand the unified
1642 ARM-Thumb syntax is needed.
1646 config THUMB2_AVOID_R_ARM_THM_JUMP11
1647 bool "Work around buggy Thumb-2 short branch relocations in gas"
1648 depends on THUMB2_KERNEL && MODULES
1651 Various binutils versions can resolve Thumb-2 branches to
1652 locally-defined, preemptible global symbols as short-range "b.n"
1653 branch instructions.
1655 This is a problem, because there's no guarantee the final
1656 destination of the symbol, or any candidate locations for a
1657 trampoline, are within range of the branch. For this reason, the
1658 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1659 relocation in modules at all, and it makes little sense to add
1662 The symptom is that the kernel fails with an "unsupported
1663 relocation" error when loading some modules.
1665 Until fixed tools are available, passing
1666 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1667 code which hits this problem, at the cost of a bit of extra runtime
1668 stack usage in some cases.
1670 The problem is described in more detail at:
1671 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1673 Only Thumb-2 kernels are affected.
1675 Unless you are sure your tools don't have this problem, say Y.
1677 config ARM_ASM_UNIFIED
1681 bool "Use the ARM EABI to compile the kernel"
1683 This option allows for the kernel to be compiled using the latest
1684 ARM ABI (aka EABI). This is only useful if you are using a user
1685 space environment that is also compiled with EABI.
1687 Since there are major incompatibilities between the legacy ABI and
1688 EABI, especially with regard to structure member alignment, this
1689 option also changes the kernel syscall calling convention to
1690 disambiguate both ABIs and allow for backward compatibility support
1691 (selected with CONFIG_OABI_COMPAT).
1693 To use this you need GCC version 4.0.0 or later.
1696 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1697 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1700 This option preserves the old syscall interface along with the
1701 new (ARM EABI) one. It also provides a compatibility layer to
1702 intercept syscalls that have structure arguments which layout
1703 in memory differs between the legacy ABI and the new ARM EABI
1704 (only for non "thumb" binaries). This option adds a tiny
1705 overhead to all syscalls and produces a slightly larger kernel.
1706 If you know you'll be using only pure EABI user space then you
1707 can say N here. If this option is not selected and you attempt
1708 to execute a legacy ABI binary then the result will be
1709 UNPREDICTABLE (in fact it can be predicted that it won't work
1710 at all). If in doubt say Y.
1712 config ARCH_HAS_HOLES_MEMORYMODEL
1715 config ARCH_SPARSEMEM_ENABLE
1718 config ARCH_SPARSEMEM_DEFAULT
1719 def_bool ARCH_SPARSEMEM_ENABLE
1721 config ARCH_SELECT_MEMORY_MODEL
1722 def_bool ARCH_SPARSEMEM_ENABLE
1724 config HAVE_ARCH_PFN_VALID
1725 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1728 bool "High Memory Support"
1731 The address space of ARM processors is only 4 Gigabytes large
1732 and it has to accommodate user address space, kernel address
1733 space as well as some memory mapped IO. That means that, if you
1734 have a large amount of physical memory and/or IO, not all of the
1735 memory can be "permanently mapped" by the kernel. The physical
1736 memory that is not permanently mapped is called "high memory".
1738 Depending on the selected kernel/user memory split, minimum
1739 vmalloc space and actual amount of RAM, you may not need this
1740 option which should result in a slightly faster kernel.
1745 bool "Allocate 2nd-level pagetables from highmem"
1748 config HW_PERF_EVENTS
1749 bool "Enable hardware performance counter support for perf events"
1750 depends on PERF_EVENTS && CPU_HAS_PMU
1753 Enable hardware performance counter support for perf events. If
1754 disabled, perf events will use software events only.
1758 config FORCE_MAX_ZONEORDER
1759 int "Maximum zone order" if ARCH_SHMOBILE
1760 range 11 64 if ARCH_SHMOBILE
1761 default "9" if SA1111
1764 The kernel memory allocator divides physically contiguous memory
1765 blocks into "zones", where each zone is a power of two number of
1766 pages. This option selects the largest power of two that the kernel
1767 keeps in the memory allocator. If you need to allocate very large
1768 blocks of physically contiguous memory, then you may need to
1769 increase this value.
1771 This config option is actually maximum order plus one. For example,
1772 a value of 11 means that the largest free memory block is 2^10 pages.
1775 bool "Timer and CPU usage LEDs"
1776 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1777 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1778 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1779 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1780 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1781 ARCH_AT91 || ARCH_DAVINCI || \
1782 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1784 If you say Y here, the LEDs on your machine will be used
1785 to provide useful information about your current system status.
1787 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1788 be able to select which LEDs are active using the options below. If
1789 you are compiling a kernel for the EBSA-110 or the LART however, the
1790 red LED will simply flash regularly to indicate that the system is
1791 still functional. It is safe to say Y here if you have a CATS
1792 system, but the driver will do nothing.
1795 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1796 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1797 || MACH_OMAP_PERSEUS2
1799 depends on !GENERIC_CLOCKEVENTS
1800 default y if ARCH_EBSA110
1802 If you say Y here, one of the system LEDs (the green one on the
1803 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1804 will flash regularly to indicate that the system is still
1805 operational. This is mainly useful to kernel hackers who are
1806 debugging unstable kernels.
1808 The LART uses the same LED for both Timer LED and CPU usage LED
1809 functions. You may choose to use both, but the Timer LED function
1810 will overrule the CPU usage LED.
1813 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1815 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1816 || MACH_OMAP_PERSEUS2
1819 If you say Y here, the red LED will be used to give a good real
1820 time indication of CPU usage, by lighting whenever the idle task
1821 is not currently executing.
1823 The LART uses the same LED for both Timer LED and CPU usage LED
1824 functions. You may choose to use both, but the Timer LED function
1825 will overrule the CPU usage LED.
1827 config ALIGNMENT_TRAP
1829 depends on CPU_CP15_MMU
1830 default y if !ARCH_EBSA110
1831 select HAVE_PROC_CPU if PROC_FS
1833 ARM processors cannot fetch/store information which is not
1834 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1835 address divisible by 4. On 32-bit ARM processors, these non-aligned
1836 fetch/store instructions will be emulated in software if you say
1837 here, which has a severe performance impact. This is necessary for
1838 correct operation of some network protocols. With an IP-only
1839 configuration it is safe to say N, otherwise say Y.
1841 config UACCESS_WITH_MEMCPY
1842 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1843 depends on MMU && EXPERIMENTAL
1844 default y if CPU_FEROCEON
1846 Implement faster copy_to_user and clear_user methods for CPU
1847 cores where a 8-word STM instruction give significantly higher
1848 memory write throughput than a sequence of individual 32bit stores.
1850 A possible side effect is a slight increase in scheduling latency
1851 between threads sharing the same address space if they invoke
1852 such copy operations with large buffers.
1854 However, if the CPU data cache is using a write-allocate mode,
1855 this option is unlikely to provide any performance gain.
1859 prompt "Enable seccomp to safely compute untrusted bytecode"
1861 This kernel feature is useful for number crunching applications
1862 that may need to compute untrusted bytecode during their
1863 execution. By using pipes or other transports made available to
1864 the process as file descriptors supporting the read/write
1865 syscalls, it's possible to isolate those applications in
1866 their own address space using seccomp. Once seccomp is
1867 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1868 and the task is only allowed to execute a few safe syscalls
1869 defined by each seccomp mode.
1871 config CC_STACKPROTECTOR
1872 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1873 depends on EXPERIMENTAL
1875 This option turns on the -fstack-protector GCC feature. This
1876 feature puts, at the beginning of functions, a canary value on
1877 the stack just before the return address, and validates
1878 the value just before actually returning. Stack based buffer
1879 overflows (that need to overwrite this return address) now also
1880 overwrite the canary, which gets detected and the attack is then
1881 neutralized via a kernel panic.
1882 This feature requires gcc version 4.2 or above.
1884 config DEPRECATED_PARAM_STRUCT
1885 bool "Provide old way to pass kernel parameters"
1887 This was deprecated in 2001 and announced to live on for 5 years.
1888 Some old boot loaders still use this way.
1895 bool "Flattened Device Tree support"
1897 select OF_EARLY_FLATTREE
1900 Include support for flattened device tree machine descriptions.
1902 # Compressed boot loader in ROM. Yes, we really want to ask about
1903 # TEXT and BSS so we preserve their values in the config files.
1904 config ZBOOT_ROM_TEXT
1905 hex "Compressed ROM boot loader base address"
1908 The physical address at which the ROM-able zImage is to be
1909 placed in the target. Platforms which normally make use of
1910 ROM-able zImage formats normally set this to a suitable
1911 value in their defconfig file.
1913 If ZBOOT_ROM is not enabled, this has no effect.
1915 config ZBOOT_ROM_BSS
1916 hex "Compressed ROM boot loader BSS address"
1919 The base address of an area of read/write memory in the target
1920 for the ROM-able zImage which must be available while the
1921 decompressor is running. It must be large enough to hold the
1922 entire decompressed kernel plus an additional 128 KiB.
1923 Platforms which normally make use of ROM-able zImage formats
1924 normally set this to a suitable value in their defconfig file.
1926 If ZBOOT_ROM is not enabled, this has no effect.
1929 bool "Compressed boot loader in ROM/flash"
1930 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1932 Say Y here if you intend to execute your compressed kernel image
1933 (zImage) directly from ROM or flash. If unsure, say N.
1936 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1937 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1938 default ZBOOT_ROM_NONE
1940 Include experimental SD/MMC loading code in the ROM-able zImage.
1941 With this enabled it is possible to write the the ROM-able zImage
1942 kernel image to an MMC or SD card and boot the kernel straight
1943 from the reset vector. At reset the processor Mask ROM will load
1944 the first part of the the ROM-able zImage which in turn loads the
1945 rest the kernel image to RAM.
1947 config ZBOOT_ROM_NONE
1948 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1950 Do not load image from SD or MMC
1952 config ZBOOT_ROM_MMCIF
1953 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1955 Load image from MMCIF hardware block.
1957 config ZBOOT_ROM_SH_MOBILE_SDHI
1958 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1960 Load image from SDHI hardware block
1964 config ARM_APPENDED_DTB
1965 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1966 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1968 With this option, the boot code will look for a device tree binary
1969 (DTB) appended to zImage
1970 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1972 This is meant as a backward compatibility convenience for those
1973 systems with a bootloader that can't be upgraded to accommodate
1974 the documented boot protocol using a device tree.
1976 Beware that there is very little in terms of protection against
1977 this option being confused by leftover garbage in memory that might
1978 look like a DTB header after a reboot if no actual DTB is appended
1979 to zImage. Do not leave this option active in a production kernel
1980 if you don't intend to always append a DTB. Proper passing of the
1981 location into r2 of a bootloader provided DTB is always preferable
1984 config ARM_ATAG_DTB_COMPAT
1985 bool "Supplement the appended DTB with traditional ATAG information"
1986 depends on ARM_APPENDED_DTB
1988 Some old bootloaders can't be updated to a DTB capable one, yet
1989 they provide ATAGs with memory configuration, the ramdisk address,
1990 the kernel cmdline string, etc. Such information is dynamically
1991 provided by the bootloader and can't always be stored in a static
1992 DTB. To allow a device tree enabled kernel to be used with such
1993 bootloaders, this option allows zImage to extract the information
1994 from the ATAG list and store it at run time into the appended DTB.
1997 string "Default kernel command string"
2000 On some architectures (EBSA110 and CATS), there is currently no way
2001 for the boot loader to pass arguments to the kernel. For these
2002 architectures, you should supply some command-line options at build
2003 time by entering them here. As a minimum, you should specify the
2004 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2007 prompt "Kernel command line type" if CMDLINE != ""
2008 default CMDLINE_FROM_BOOTLOADER
2010 config CMDLINE_FROM_BOOTLOADER
2011 bool "Use bootloader kernel arguments if available"
2013 Uses the command-line options passed by the boot loader. If
2014 the boot loader doesn't provide any, the default kernel command
2015 string provided in CMDLINE will be used.
2017 config CMDLINE_EXTEND
2018 bool "Extend bootloader kernel arguments"
2020 The command-line arguments provided by the boot loader will be
2021 appended to the default kernel command string.
2023 config CMDLINE_FORCE
2024 bool "Always use the default kernel command string"
2026 Always use the default kernel command string, even if the boot
2027 loader passes other arguments to the kernel.
2028 This is useful if you cannot or don't want to change the
2029 command-line options your boot loader passes to the kernel.
2033 bool "Kernel Execute-In-Place from ROM"
2034 depends on !ZBOOT_ROM && !ARM_LPAE
2036 Execute-In-Place allows the kernel to run from non-volatile storage
2037 directly addressable by the CPU, such as NOR flash. This saves RAM
2038 space since the text section of the kernel is not loaded from flash
2039 to RAM. Read-write sections, such as the data section and stack,
2040 are still copied to RAM. The XIP kernel is not compressed since
2041 it has to run directly from flash, so it will take more space to
2042 store it. The flash address used to link the kernel object files,
2043 and for storing it, is configuration dependent. Therefore, if you
2044 say Y here, you must know the proper physical address where to
2045 store the kernel image depending on your own flash memory usage.
2047 Also note that the make target becomes "make xipImage" rather than
2048 "make zImage" or "make Image". The final kernel binary to put in
2049 ROM memory will be arch/arm/boot/xipImage.
2053 config XIP_PHYS_ADDR
2054 hex "XIP Kernel Physical Location"
2055 depends on XIP_KERNEL
2056 default "0x00080000"
2058 This is the physical address in your flash memory the kernel will
2059 be linked for and stored to. This address is dependent on your
2063 bool "Kexec system call (EXPERIMENTAL)"
2064 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2066 kexec is a system call that implements the ability to shutdown your
2067 current kernel, and to start another kernel. It is like a reboot
2068 but it is independent of the system firmware. And like a reboot
2069 you can start any kernel with it, not just Linux.
2071 It is an ongoing process to be certain the hardware in a machine
2072 is properly shutdown, so do not be surprised if this code does not
2073 initially work for you. It may help to enable device hotplugging
2077 bool "Export atags in procfs"
2081 Should the atags used to boot the kernel be exported in an "atags"
2082 file in procfs. Useful with kexec.
2085 bool "Build kdump crash kernel (EXPERIMENTAL)"
2086 depends on EXPERIMENTAL
2088 Generate crash dump after being started by kexec. This should
2089 be normally only set in special crash dump kernels which are
2090 loaded in the main kernel with kexec-tools into a specially
2091 reserved region and then later executed after a crash by
2092 kdump/kexec. The crash dump kernel must be compiled to a
2093 memory address not used by the main kernel
2095 For more details see Documentation/kdump/kdump.txt
2097 config AUTO_ZRELADDR
2098 bool "Auto calculation of the decompressed kernel image address"
2099 depends on !ZBOOT_ROM && !ARCH_U300
2101 ZRELADDR is the physical address where the decompressed kernel
2102 image will be placed. If AUTO_ZRELADDR is selected, the address
2103 will be determined at run-time by masking the current IP with
2104 0xf8000000. This assumes the zImage being placed in the first 128MB
2105 from start of memory.
2109 menu "CPU Power Management"
2113 source "drivers/cpufreq/Kconfig"
2116 tristate "CPUfreq driver for i.MX CPUs"
2117 depends on ARCH_MXC && CPU_FREQ
2119 This enables the CPUfreq driver for i.MX CPUs.
2121 config CPU_FREQ_SA1100
2124 config CPU_FREQ_SA1110
2127 config CPU_FREQ_INTEGRATOR
2128 tristate "CPUfreq driver for ARM Integrator CPUs"
2129 depends on ARCH_INTEGRATOR && CPU_FREQ
2132 This enables the CPUfreq driver for ARM Integrator CPUs.
2134 For details, take a look at <file:Documentation/cpu-freq>.
2140 depends on CPU_FREQ && ARCH_PXA && PXA25x
2142 select CPU_FREQ_TABLE
2143 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2148 Internal configuration node for common cpufreq on Samsung SoC
2150 config CPU_FREQ_S3C24XX
2151 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2152 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2155 This enables the CPUfreq driver for the Samsung S3C24XX family
2158 For details, take a look at <file:Documentation/cpu-freq>.
2162 config CPU_FREQ_S3C24XX_PLL
2163 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2164 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2166 Compile in support for changing the PLL frequency from the
2167 S3C24XX series CPUfreq driver. The PLL takes time to settle
2168 after a frequency change, so by default it is not enabled.
2170 This also means that the PLL tables for the selected CPU(s) will
2171 be built which may increase the size of the kernel image.
2173 config CPU_FREQ_S3C24XX_DEBUG
2174 bool "Debug CPUfreq Samsung driver core"
2175 depends on CPU_FREQ_S3C24XX
2177 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2179 config CPU_FREQ_S3C24XX_IODEBUG
2180 bool "Debug CPUfreq Samsung driver IO timing"
2181 depends on CPU_FREQ_S3C24XX
2183 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2185 config CPU_FREQ_S3C24XX_DEBUGFS
2186 bool "Export debugfs for CPUFreq"
2187 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2189 Export status information via debugfs.
2193 source "drivers/cpuidle/Kconfig"
2197 menu "Floating point emulation"
2199 comment "At least one emulation must be selected"
2202 bool "NWFPE math emulation"
2203 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2205 Say Y to include the NWFPE floating point emulator in the kernel.
2206 This is necessary to run most binaries. Linux does not currently
2207 support floating point hardware so you need to say Y here even if
2208 your machine has an FPA or floating point co-processor podule.
2210 You may say N here if you are going to load the Acorn FPEmulator
2211 early in the bootup.
2214 bool "Support extended precision"
2215 depends on FPE_NWFPE
2217 Say Y to include 80-bit support in the kernel floating-point
2218 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2219 Note that gcc does not generate 80-bit operations by default,
2220 so in most cases this option only enlarges the size of the
2221 floating point emulator without any good reason.
2223 You almost surely want to say N here.
2226 bool "FastFPE math emulation (EXPERIMENTAL)"
2227 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2229 Say Y here to include the FAST floating point emulator in the kernel.
2230 This is an experimental much faster emulator which now also has full
2231 precision for the mantissa. It does not support any exceptions.
2232 It is very simple, and approximately 3-6 times faster than NWFPE.
2234 It should be sufficient for most programs. It may be not suitable
2235 for scientific calculations, but you have to check this for yourself.
2236 If you do not feel you need a faster FP emulation you should better
2240 bool "VFP-format floating point maths"
2241 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2243 Say Y to include VFP support code in the kernel. This is needed
2244 if your hardware includes a VFP unit.
2246 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2247 release notes and additional status information.
2249 Say N if your target does not have VFP hardware.
2257 bool "Advanced SIMD (NEON) Extension support"
2258 depends on VFPv3 && CPU_V7
2260 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2265 menu "Userspace binary formats"
2267 source "fs/Kconfig.binfmt"
2270 tristate "RISC OS personality"
2273 Say Y here to include the kernel code necessary if you want to run
2274 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2275 experimental; if this sounds frightening, say N and sleep in peace.
2276 You can also say M here to compile this support as a module (which
2277 will be called arthur).
2281 menu "Power management options"
2283 source "kernel/power/Kconfig"
2285 config ARCH_SUSPEND_POSSIBLE
2286 depends on !ARCH_S5PC100
2287 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2288 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2291 config ARM_CPU_SUSPEND
2296 source "net/Kconfig"
2298 source "drivers/Kconfig"
2302 source "arch/arm/Kconfig.debug"
2304 source "security/Kconfig"
2306 source "crypto/Kconfig"
2308 source "lib/Kconfig"