5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (!CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
32 The ARM series is a line of low-power-consumption RISC chip designs
33 licensed by ARM Ltd and targeted at embedded applications and
34 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
35 manufactured, but legacy ARM-based PC hardware remains popular in
36 Europe. There is an ARM Linux project with a web page at
37 <http://www.arm.linux.org.uk/>.
45 config SYS_SUPPORTS_APM_EMULATION
48 config HAVE_SCHED_CLOCK
54 config ARCH_USES_GETTIMEOFFSET
58 config GENERIC_CLOCKEVENTS
61 config GENERIC_CLOCKEVENTS_BROADCAST
63 depends on GENERIC_CLOCKEVENTS
72 select GENERIC_ALLOCATOR
83 The Extended Industry Standard Architecture (EISA) bus was
84 developed as an open alternative to the IBM MicroChannel bus.
86 The EISA bus provided some of the features of the IBM MicroChannel
87 bus while maintaining backward compatibility with cards made for
88 the older ISA bus. The EISA bus saw limited use between 1988 and
89 1995 when it was made obsolete by the PCI bus.
91 Say Y here if you are building a kernel for an EISA-based machine.
101 MicroChannel Architecture is found in some IBM PS/2 machines and
102 laptops. It is a bus system similar to PCI or ISA. See
103 <file:Documentation/mca.txt> (and especially the web page given
104 there) before attempting to build an MCA bus kernel.
106 config STACKTRACE_SUPPORT
110 config HAVE_LATENCYTOP_SUPPORT
115 config LOCKDEP_SUPPORT
119 config TRACE_IRQFLAGS_SUPPORT
123 config HARDIRQS_SW_RESEND
127 config GENERIC_IRQ_PROBE
131 config GENERIC_LOCKBREAK
134 depends on SMP && PREEMPT
136 config RWSEM_GENERIC_SPINLOCK
140 config RWSEM_XCHGADD_ALGORITHM
143 config ARCH_HAS_ILOG2_U32
146 config ARCH_HAS_ILOG2_U64
149 config ARCH_HAS_CPUFREQ
152 Internal node to signify that the ARCH has CPUFREQ support
153 and that the relevant menu configurations are displayed for
156 config ARCH_HAS_CPU_IDLE_WAIT
159 config GENERIC_HWEIGHT
163 config GENERIC_CALIBRATE_DELAY
167 config ARCH_MAY_HAVE_PC_FDC
173 config NEED_DMA_MAP_STATE
176 config GENERIC_ISA_DMA
187 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
188 default DRAM_BASE if REMAP_VECTORS_TO_RAM
191 The base address of exception vectors.
193 source "init/Kconfig"
195 source "kernel/Kconfig.freezer"
200 bool "MMU-based Paged Memory Management Support"
203 Select if you want MMU-based virtualised addressing space
204 support by paged memory management. If unsure, say 'Y'.
207 # The "ARM system type" choice list is ordered alphabetically by option
208 # text. Please add new entries in the option alphabetic order.
211 prompt "ARM system type"
212 default ARCH_VERSATILE
215 bool "Agilent AAEC-2000 based"
219 select ARCH_USES_GETTIMEOFFSET
221 This enables support for systems based on the Agilent AAEC-2000
223 config ARCH_INTEGRATOR
224 bool "ARM Ltd. Integrator family"
226 select ARCH_HAS_CPUFREQ
229 select GENERIC_CLOCKEVENTS
230 select PLAT_VERSATILE
232 Support for ARM's Integrator platform.
235 bool "ARM Ltd. RealView family"
238 select HAVE_SCHED_CLOCK
240 select GENERIC_CLOCKEVENTS
241 select ARCH_WANT_OPTIONAL_GPIOLIB
242 select PLAT_VERSATILE
243 select ARM_TIMER_SP804
244 select GPIO_PL061 if GPIOLIB
246 This enables support for ARM Ltd RealView boards.
248 config ARCH_VERSATILE
249 bool "ARM Ltd. Versatile family"
253 select HAVE_SCHED_CLOCK
255 select GENERIC_CLOCKEVENTS
256 select ARCH_WANT_OPTIONAL_GPIOLIB
257 select PLAT_VERSATILE
258 select ARM_TIMER_SP804
260 This enables support for ARM Ltd Versatile board.
263 bool "ARM Ltd. Versatile Express family"
264 select ARCH_WANT_OPTIONAL_GPIOLIB
266 select ARM_TIMER_SP804
268 select GENERIC_CLOCKEVENTS
270 select HAVE_SCHED_CLOCK
272 select PLAT_VERSATILE
274 This enables support for the ARM Ltd Versatile Express boards.
278 select ARCH_REQUIRE_GPIOLIB
281 This enables support for systems based on the Atmel AT91RM9200,
282 AT91SAM9 and AT91CAP9 processors.
285 bool "Broadcom BCMRING"
290 select GENERIC_CLOCKEVENTS
291 select ARCH_WANT_OPTIONAL_GPIOLIB
293 Support for Broadcom's BCMRing platform.
296 bool "Cirrus Logic CLPS711x/EP721x-based"
298 select ARCH_USES_GETTIMEOFFSET
300 Support for Cirrus Logic 711x/721x based boards.
303 bool "Cavium Networks CNS3XXX family"
305 select GENERIC_CLOCKEVENTS
307 select MIGHT_HAVE_PCI
308 select PCI_DOMAINS if PCI
310 Support for Cavium Networks CNS3XXX platform.
313 bool "Cortina Systems Gemini"
315 select ARCH_REQUIRE_GPIOLIB
316 select ARCH_USES_GETTIMEOFFSET
318 Support for the Cortina Systems Gemini family SoCs
325 select ARCH_USES_GETTIMEOFFSET
327 This is an evaluation board for the StrongARM processor available
328 from Digital. It has limited hardware on-board, including an
329 Ethernet interface, two PCMCIA sockets, two serial ports and a
338 select ARCH_REQUIRE_GPIOLIB
339 select ARCH_HAS_HOLES_MEMORYMODEL
340 select ARCH_USES_GETTIMEOFFSET
342 This enables support for the Cirrus EP93xx series of CPUs.
344 config ARCH_FOOTBRIDGE
348 select GENERIC_CLOCKEVENTS
350 Support for systems based on the DC21285 companion chip
351 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
354 bool "Freescale MXC/iMX-based"
355 select GENERIC_CLOCKEVENTS
356 select ARCH_REQUIRE_GPIOLIB
359 Support for Freescale MXC/iMX-based family of processors
362 bool "Freescale MXS-based"
363 select GENERIC_CLOCKEVENTS
364 select ARCH_REQUIRE_GPIOLIB
367 Support for Freescale MXS-based family of processors
370 bool "Freescale STMP3xxx"
373 select ARCH_REQUIRE_GPIOLIB
374 select GENERIC_CLOCKEVENTS
375 select USB_ARCH_HAS_EHCI
377 Support for systems based on the Freescale 3xxx CPUs.
380 bool "Hilscher NetX based"
383 select GENERIC_CLOCKEVENTS
385 This enables support for systems based on the Hilscher NetX Soc
388 bool "Hynix HMS720x-based"
391 select ARCH_USES_GETTIMEOFFSET
393 This enables support for systems based on the Hynix HMS720x
401 select ARCH_SUPPORTS_MSI
404 Support for Intel's IOP13XX (XScale) family of processors.
412 select ARCH_REQUIRE_GPIOLIB
414 Support for Intel's 80219 and IOP32X (XScale) family of
423 select ARCH_REQUIRE_GPIOLIB
425 Support for Intel's IOP33X (XScale) family of processors.
432 select ARCH_USES_GETTIMEOFFSET
434 Support for Intel's IXP23xx (XScale) family of processors.
437 bool "IXP2400/2800-based"
441 select ARCH_USES_GETTIMEOFFSET
443 Support for Intel's IXP2400/2800 (XScale) family of processors.
450 select GENERIC_CLOCKEVENTS
451 select HAVE_SCHED_CLOCK
452 select MIGHT_HAVE_PCI
453 select DMABOUNCE if PCI
455 Support for Intel's IXP4XX (XScale) family of processors.
460 select ARCH_REQUIRE_GPIOLIB
461 select GENERIC_CLOCKEVENTS
464 Support for the Marvell Dove SoC 88AP510
467 bool "Marvell Kirkwood"
470 select ARCH_REQUIRE_GPIOLIB
471 select GENERIC_CLOCKEVENTS
474 Support for the following Marvell Kirkwood series SoCs:
475 88F6180, 88F6192 and 88F6281.
478 bool "Marvell Loki (88RC8480)"
480 select GENERIC_CLOCKEVENTS
483 Support for the Marvell Loki (88RC8480) SoC.
488 select ARCH_REQUIRE_GPIOLIB
491 select USB_ARCH_HAS_OHCI
494 select GENERIC_CLOCKEVENTS
496 Support for the NXP LPC32XX family of processors
499 bool "Marvell MV78xx0"
502 select ARCH_REQUIRE_GPIOLIB
503 select GENERIC_CLOCKEVENTS
506 Support for the following Marvell MV78xx0 series SoCs:
514 select ARCH_REQUIRE_GPIOLIB
515 select GENERIC_CLOCKEVENTS
518 Support for the following Marvell Orion 5x series SoCs:
519 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
520 Orion-2 (5281), Orion-1-90 (6183).
523 bool "Marvell PXA168/910/MMP2"
525 select ARCH_REQUIRE_GPIOLIB
527 select GENERIC_CLOCKEVENTS
528 select HAVE_SCHED_CLOCK
533 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
536 bool "Micrel/Kendin KS8695"
538 select ARCH_REQUIRE_GPIOLIB
539 select ARCH_USES_GETTIMEOFFSET
541 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
542 System-on-Chip devices.
545 bool "NetSilicon NS9xxx"
548 select GENERIC_CLOCKEVENTS
551 Say Y here if you intend to run this kernel on a NetSilicon NS9xxx
554 <http://www.digi.com/products/microprocessors/index.jsp>
557 bool "Nuvoton W90X900 CPU"
559 select ARCH_REQUIRE_GPIOLIB
561 select GENERIC_CLOCKEVENTS
563 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
564 At present, the w90x900 has been renamed nuc900, regarding
565 the ARM series product line, you can login the following
566 link address to know more.
568 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
569 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
572 bool "Nuvoton NUC93X CPU"
576 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
577 low-power and high performance MPEG-4/JPEG multimedia controller chip.
583 select GENERIC_CLOCKEVENTS
586 select HAVE_SCHED_CLOCK
587 select ARCH_HAS_BARRIERS if CACHE_L2X0
588 select ARCH_HAS_CPUFREQ
590 This enables support for NVIDIA Tegra based systems (Tegra APX,
591 Tegra 6xx and Tegra 2 series).
594 bool "Philips Nexperia PNX4008 Mobile"
597 select ARCH_USES_GETTIMEOFFSET
599 This enables support for Philips PNX4008 mobile platform.
602 bool "PXA2xx/PXA3xx-based"
605 select ARCH_HAS_CPUFREQ
607 select ARCH_REQUIRE_GPIOLIB
608 select GENERIC_CLOCKEVENTS
609 select HAVE_SCHED_CLOCK
614 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
619 select GENERIC_CLOCKEVENTS
620 select ARCH_REQUIRE_GPIOLIB
622 Support for Qualcomm MSM/QSD based systems. This runs on the
623 apps processor of the MSM/QSD and depends on a shared memory
624 interface to the modem processor which runs the baseband
625 stack and controls some vital subsystems
626 (clock and power control, etc).
629 bool "Renesas SH-Mobile / R-Mobile"
632 select GENERIC_CLOCKEVENTS
635 select MULTI_IRQ_HANDLER
637 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
644 select ARCH_MAY_HAVE_PC_FDC
645 select HAVE_PATA_PLATFORM
648 select ARCH_SPARSEMEM_ENABLE
649 select ARCH_USES_GETTIMEOFFSET
651 On the Acorn Risc-PC, Linux can support the internal IDE disk and
652 CD-ROM interface, serial and parallel port, and the floppy drive.
658 select ARCH_SPARSEMEM_ENABLE
660 select ARCH_HAS_CPUFREQ
662 select GENERIC_CLOCKEVENTS
664 select HAVE_SCHED_CLOCK
666 select ARCH_REQUIRE_GPIOLIB
668 Support for StrongARM 11x0 based boards.
671 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
673 select ARCH_HAS_CPUFREQ
675 select ARCH_USES_GETTIMEOFFSET
676 select HAVE_S3C2410_I2C if I2C
678 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
679 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
680 the Samsung SMDK2410 development board (and derivatives).
682 Note, the S3C2416 and the S3C2450 are so close that they even share
683 the same SoC ID code. This means that there is no seperate machine
684 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
687 bool "Samsung S3C64XX"
693 select ARCH_USES_GETTIMEOFFSET
694 select ARCH_HAS_CPUFREQ
695 select ARCH_REQUIRE_GPIOLIB
696 select SAMSUNG_CLKSRC
697 select SAMSUNG_IRQ_VIC_TIMER
698 select SAMSUNG_IRQ_UART
699 select S3C_GPIO_TRACK
700 select S3C_GPIO_PULL_UPDOWN
701 select S3C_GPIO_CFG_S3C24XX
702 select S3C_GPIO_CFG_S3C64XX
704 select USB_ARCH_HAS_OHCI
705 select SAMSUNG_GPIOLIB_4BIT
706 select HAVE_S3C2410_I2C if I2C
707 select HAVE_S3C2410_WATCHDOG if WATCHDOG
709 Samsung S3C64XX series based systems
712 bool "Samsung S5P6440 S5P6450"
716 select HAVE_S3C2410_WATCHDOG if WATCHDOG
717 select ARCH_USES_GETTIMEOFFSET
718 select HAVE_S3C2410_I2C if I2C
719 select HAVE_S3C_RTC if RTC_CLASS
721 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
725 bool "Samsung S5P6442"
729 select ARCH_USES_GETTIMEOFFSET
730 select HAVE_S3C2410_WATCHDOG if WATCHDOG
732 Samsung S5P6442 CPU based systems
735 bool "Samsung S5PC100"
739 select ARM_L1_CACHE_SHIFT_6
740 select ARCH_USES_GETTIMEOFFSET
741 select HAVE_S3C2410_I2C if I2C
742 select HAVE_S3C_RTC if RTC_CLASS
743 select HAVE_S3C2410_WATCHDOG if WATCHDOG
745 Samsung S5PC100 series based systems
748 bool "Samsung S5PV210/S5PC110"
750 select ARCH_SPARSEMEM_ENABLE
753 select ARM_L1_CACHE_SHIFT_6
754 select ARCH_HAS_CPUFREQ
755 select ARCH_USES_GETTIMEOFFSET
756 select HAVE_S3C2410_I2C if I2C
757 select HAVE_S3C_RTC if RTC_CLASS
758 select HAVE_S3C2410_WATCHDOG if WATCHDOG
760 Samsung S5PV210/S5PC110 series based systems
763 bool "Samsung S5PV310/S5PC210"
765 select ARCH_SPARSEMEM_ENABLE
768 select ARCH_HAS_CPUFREQ
769 select GENERIC_CLOCKEVENTS
770 select HAVE_S3C_RTC if RTC_CLASS
771 select HAVE_S3C2410_I2C if I2C
772 select HAVE_S3C2410_WATCHDOG if WATCHDOG
774 Samsung S5PV310 series based systems
783 select ARCH_USES_GETTIMEOFFSET
785 Support for the StrongARM based Digital DNARD machine, also known
786 as "Shark" (<http://www.shark-linux.de/shark.html>).
789 bool "Telechips TCC ARM926-based systems"
793 select GENERIC_CLOCKEVENTS
795 Support for Telechips TCC ARM926-based systems.
800 select ARCH_SPARSEMEM_ENABLE if !LH7A40X_CONTIGMEM
801 select ARCH_USES_GETTIMEOFFSET
803 Say Y here for systems based on one of the Sharp LH7A40X
804 System on a Chip processors. These CPUs include an ARM922T
805 core with a wide array of integrated devices for
806 hand-held and low-power applications.
809 bool "ST-Ericsson U300 Series"
812 select HAVE_SCHED_CLOCK
816 select GENERIC_CLOCKEVENTS
820 Support for ST-Ericsson U300 series mobile platforms.
823 bool "ST-Ericsson U8500 Series"
826 select GENERIC_CLOCKEVENTS
828 select ARCH_REQUIRE_GPIOLIB
829 select ARCH_HAS_CPUFREQ
831 Support for ST-Ericsson's Ux500 architecture
834 bool "STMicroelectronics Nomadik"
839 select GENERIC_CLOCKEVENTS
840 select ARCH_REQUIRE_GPIOLIB
842 Support for the Nomadik platform by ST-Ericsson
846 select GENERIC_CLOCKEVENTS
847 select ARCH_REQUIRE_GPIOLIB
851 select GENERIC_ALLOCATOR
852 select ARCH_HAS_HOLES_MEMORYMODEL
854 Support for TI's DaVinci platform.
859 select ARCH_REQUIRE_GPIOLIB
860 select ARCH_HAS_CPUFREQ
861 select GENERIC_CLOCKEVENTS
862 select HAVE_SCHED_CLOCK
863 select ARCH_HAS_HOLES_MEMORYMODEL
865 Support for TI's OMAP platform (OMAP1/2/3/4).
870 select ARCH_REQUIRE_GPIOLIB
872 select GENERIC_CLOCKEVENTS
875 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
878 bool "VIA/WonderMedia 85xx"
881 select ARCH_HAS_CPUFREQ
882 select GENERIC_CLOCKEVENTS
883 select ARCH_REQUIRE_GPIOLIB
886 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
890 # This is sorted alphabetically by mach-* pathname. However, plat-*
891 # Kconfigs may be included either alphabetically (according to the
892 # plat- suffix) or along side the corresponding mach-* source.
894 source "arch/arm/mach-aaec2000/Kconfig"
896 source "arch/arm/mach-at91/Kconfig"
898 source "arch/arm/mach-bcmring/Kconfig"
900 source "arch/arm/mach-clps711x/Kconfig"
902 source "arch/arm/mach-cns3xxx/Kconfig"
904 source "arch/arm/mach-davinci/Kconfig"
906 source "arch/arm/mach-dove/Kconfig"
908 source "arch/arm/mach-ep93xx/Kconfig"
910 source "arch/arm/mach-footbridge/Kconfig"
912 source "arch/arm/mach-gemini/Kconfig"
914 source "arch/arm/mach-h720x/Kconfig"
916 source "arch/arm/mach-integrator/Kconfig"
918 source "arch/arm/mach-iop32x/Kconfig"
920 source "arch/arm/mach-iop33x/Kconfig"
922 source "arch/arm/mach-iop13xx/Kconfig"
924 source "arch/arm/mach-ixp4xx/Kconfig"
926 source "arch/arm/mach-ixp2000/Kconfig"
928 source "arch/arm/mach-ixp23xx/Kconfig"
930 source "arch/arm/mach-kirkwood/Kconfig"
932 source "arch/arm/mach-ks8695/Kconfig"
934 source "arch/arm/mach-lh7a40x/Kconfig"
936 source "arch/arm/mach-loki/Kconfig"
938 source "arch/arm/mach-lpc32xx/Kconfig"
940 source "arch/arm/mach-msm/Kconfig"
942 source "arch/arm/mach-mv78xx0/Kconfig"
944 source "arch/arm/plat-mxc/Kconfig"
946 source "arch/arm/mach-mxs/Kconfig"
948 source "arch/arm/mach-netx/Kconfig"
950 source "arch/arm/mach-nomadik/Kconfig"
951 source "arch/arm/plat-nomadik/Kconfig"
953 source "arch/arm/mach-ns9xxx/Kconfig"
955 source "arch/arm/mach-nuc93x/Kconfig"
957 source "arch/arm/plat-omap/Kconfig"
959 source "arch/arm/mach-omap1/Kconfig"
961 source "arch/arm/mach-omap2/Kconfig"
963 source "arch/arm/mach-orion5x/Kconfig"
965 source "arch/arm/mach-pxa/Kconfig"
966 source "arch/arm/plat-pxa/Kconfig"
968 source "arch/arm/mach-mmp/Kconfig"
970 source "arch/arm/mach-realview/Kconfig"
972 source "arch/arm/mach-sa1100/Kconfig"
974 source "arch/arm/plat-samsung/Kconfig"
975 source "arch/arm/plat-s3c24xx/Kconfig"
976 source "arch/arm/plat-s5p/Kconfig"
978 source "arch/arm/plat-spear/Kconfig"
980 source "arch/arm/plat-tcc/Kconfig"
983 source "arch/arm/mach-s3c2400/Kconfig"
984 source "arch/arm/mach-s3c2410/Kconfig"
985 source "arch/arm/mach-s3c2412/Kconfig"
986 source "arch/arm/mach-s3c2416/Kconfig"
987 source "arch/arm/mach-s3c2440/Kconfig"
988 source "arch/arm/mach-s3c2443/Kconfig"
992 source "arch/arm/mach-s3c64xx/Kconfig"
995 source "arch/arm/mach-s5p64x0/Kconfig"
997 source "arch/arm/mach-s5p6442/Kconfig"
999 source "arch/arm/mach-s5pc100/Kconfig"
1001 source "arch/arm/mach-s5pv210/Kconfig"
1003 source "arch/arm/mach-s5pv310/Kconfig"
1005 source "arch/arm/mach-shmobile/Kconfig"
1007 source "arch/arm/plat-stmp3xxx/Kconfig"
1009 source "arch/arm/mach-tegra/Kconfig"
1011 source "arch/arm/mach-u300/Kconfig"
1013 source "arch/arm/mach-ux500/Kconfig"
1015 source "arch/arm/mach-versatile/Kconfig"
1017 source "arch/arm/mach-vexpress/Kconfig"
1019 source "arch/arm/mach-vt8500/Kconfig"
1021 source "arch/arm/mach-w90x900/Kconfig"
1023 # Definitions to make life easier
1029 select GENERIC_CLOCKEVENTS
1030 select HAVE_SCHED_CLOCK
1034 select HAVE_SCHED_CLOCK
1039 config PLAT_VERSATILE
1042 config ARM_TIMER_SP804
1045 source arch/arm/mm/Kconfig
1048 bool "Enable iWMMXt support"
1049 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1050 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1052 Enable support for iWMMXt context switching at run time if
1053 running on a CPU that supports it.
1055 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1058 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1062 depends on (CPU_V6 || CPU_V7 || XSCALE_PMU) && \
1063 (!ARCH_OMAP3 || OMAP3_EMU)
1067 config MULTI_IRQ_HANDLER
1070 Allow each machine to specify it's own IRQ handler at run time.
1073 source "arch/arm/Kconfig-nommu"
1076 config ARM_ERRATA_411920
1077 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1080 Invalidation of the Instruction Cache operation can
1081 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1082 It does not affect the MPCore. This option enables the ARM Ltd.
1083 recommended workaround.
1085 config ARM_ERRATA_430973
1086 bool "ARM errata: Stale prediction on replaced interworking branch"
1089 This option enables the workaround for the 430973 Cortex-A8
1090 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1091 interworking branch is replaced with another code sequence at the
1092 same virtual address, whether due to self-modifying code or virtual
1093 to physical address re-mapping, Cortex-A8 does not recover from the
1094 stale interworking branch prediction. This results in Cortex-A8
1095 executing the new code sequence in the incorrect ARM or Thumb state.
1096 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1097 and also flushes the branch target cache at every context switch.
1098 Note that setting specific bits in the ACTLR register may not be
1099 available in non-secure mode.
1101 config ARM_ERRATA_458693
1102 bool "ARM errata: Processor deadlock when a false hazard is created"
1105 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1106 erratum. For very specific sequences of memory operations, it is
1107 possible for a hazard condition intended for a cache line to instead
1108 be incorrectly associated with a different cache line. This false
1109 hazard might then cause a processor deadlock. The workaround enables
1110 the L1 caching of the NEON accesses and disables the PLD instruction
1111 in the ACTLR register. Note that setting specific bits in the ACTLR
1112 register may not be available in non-secure mode.
1114 config ARM_ERRATA_460075
1115 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1118 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1119 erratum. Any asynchronous access to the L2 cache may encounter a
1120 situation in which recent store transactions to the L2 cache are lost
1121 and overwritten with stale memory contents from external memory. The
1122 workaround disables the write-allocate mode for the L2 cache via the
1123 ACTLR register. Note that setting specific bits in the ACTLR register
1124 may not be available in non-secure mode.
1126 config ARM_ERRATA_742230
1127 bool "ARM errata: DMB operation may be faulty"
1128 depends on CPU_V7 && SMP
1130 This option enables the workaround for the 742230 Cortex-A9
1131 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1132 between two write operations may not ensure the correct visibility
1133 ordering of the two writes. This workaround sets a specific bit in
1134 the diagnostic register of the Cortex-A9 which causes the DMB
1135 instruction to behave as a DSB, ensuring the correct behaviour of
1138 config ARM_ERRATA_742231
1139 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1140 depends on CPU_V7 && SMP
1142 This option enables the workaround for the 742231 Cortex-A9
1143 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1144 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1145 accessing some data located in the same cache line, may get corrupted
1146 data due to bad handling of the address hazard when the line gets
1147 replaced from one of the CPUs at the same time as another CPU is
1148 accessing it. This workaround sets specific bits in the diagnostic
1149 register of the Cortex-A9 which reduces the linefill issuing
1150 capabilities of the processor.
1152 config PL310_ERRATA_588369
1153 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1154 depends on CACHE_L2X0
1156 The PL310 L2 cache controller implements three types of Clean &
1157 Invalidate maintenance operations: by Physical Address
1158 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1159 They are architecturally defined to behave as the execution of a
1160 clean operation followed immediately by an invalidate operation,
1161 both performing to the same memory location. This functionality
1162 is not correctly implemented in PL310 as clean lines are not
1163 invalidated as a result of these operations.
1165 config ARM_ERRATA_720789
1166 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1167 depends on CPU_V7 && SMP
1169 This option enables the workaround for the 720789 Cortex-A9 (prior to
1170 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1171 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1172 As a consequence of this erratum, some TLB entries which should be
1173 invalidated are not, resulting in an incoherency in the system page
1174 tables. The workaround changes the TLB flushing routines to invalidate
1175 entries regardless of the ASID.
1177 config PL310_ERRATA_727915
1178 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1179 depends on CACHE_L2X0
1181 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1182 operation (offset 0x7FC). This operation runs in background so that
1183 PL310 can handle normal accesses while it is in progress. Under very
1184 rare circumstances, due to this erratum, write data can be lost when
1185 PL310 treats a cacheable write transaction during a Clean &
1186 Invalidate by Way operation.
1188 config ARM_ERRATA_743622
1189 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1192 This option enables the workaround for the 743622 Cortex-A9
1193 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1194 optimisation in the Cortex-A9 Store Buffer may lead to data
1195 corruption. This workaround sets a specific bit in the diagnostic
1196 register of the Cortex-A9 which disables the Store Buffer
1197 optimisation, preventing the defect from occurring. This has no
1198 visible impact on the overall performance or power consumption of the
1201 config ARM_ERRATA_751472
1202 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1203 depends on CPU_V7 && SMP
1205 This option enables the workaround for the 751472 Cortex-A9 (prior
1206 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1207 completion of a following broadcasted operation if the second
1208 operation is received by a CPU before the ICIALLUIS has completed,
1209 potentially leading to corrupted entries in the cache or TLB.
1211 config ARM_ERRATA_753970
1212 bool "ARM errata: cache sync operation may be faulty"
1213 depends on CACHE_PL310
1215 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1217 Under some condition the effect of cache sync operation on
1218 the store buffer still remains when the operation completes.
1219 This means that the store buffer is always asked to drain and
1220 this prevents it from merging any further writes. The workaround
1221 is to replace the normal offset of cache sync operation (0x730)
1222 by another offset targeting an unmapped PL310 register 0x740.
1223 This has the same effect as the cache sync operation: store buffer
1224 drain and waiting for all buffers empty.
1226 config ARM_ERRATA_754322
1227 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1230 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1231 r3p*) erratum. A speculative memory access may cause a page table walk
1232 which starts prior to an ASID switch but completes afterwards. This
1233 can populate the micro-TLB with a stale entry which may be hit with
1234 the new ASID. This workaround places two dsb instructions in the mm
1235 switching code so that no page table walks can cross the ASID switch.
1237 config ARM_ERRATA_754327
1238 bool "ARM errata: no automatic Store Buffer drain"
1239 depends on CPU_V7 && SMP
1241 This option enables the workaround for the 754327 Cortex-A9 (prior to
1242 r2p0) erratum. The Store Buffer does not have any automatic draining
1243 mechanism and therefore a livelock may occur if an external agent
1244 continuously polls a memory location waiting to observe an update.
1245 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1246 written polling loops from denying visibility of updates to memory.
1250 source "arch/arm/common/Kconfig"
1260 Find out whether you have ISA slots on your motherboard. ISA is the
1261 name of a bus system, i.e. the way the CPU talks to the other stuff
1262 inside your box. Other bus systems are PCI, EISA, MicroChannel
1263 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1264 newer boards don't support it. If you have ISA, say Y, otherwise N.
1266 # Select ISA DMA controller support
1271 # Select ISA DMA interface
1276 bool "PCI support" if MIGHT_HAVE_PCI
1278 Find out whether you have a PCI motherboard. PCI is the name of a
1279 bus system, i.e. the way the CPU talks to the other stuff inside
1280 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1281 VESA. If you have PCI, say Y, otherwise N.
1287 config PCI_NANOENGINE
1288 bool "BSE nanoEngine PCI support"
1289 depends on SA1100_NANOENGINE
1291 Enable PCI on the BSE nanoEngine board.
1296 # Select the host bridge type
1297 config PCI_HOST_VIA82C505
1299 depends on PCI && ARCH_SHARK
1302 config PCI_HOST_ITE8152
1304 depends on PCI && MACH_ARMCORE
1308 source "drivers/pci/Kconfig"
1310 source "drivers/pcmcia/Kconfig"
1314 menu "Kernel Features"
1316 source "kernel/time/Kconfig"
1319 bool "Symmetric Multi-Processing (EXPERIMENTAL)"
1320 depends on EXPERIMENTAL
1321 depends on GENERIC_CLOCKEVENTS
1322 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1323 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1324 ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1325 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1326 select USE_GENERIC_SMP_HELPERS
1327 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1329 This enables support for systems with more than one CPU. If you have
1330 a system with only one CPU, like most personal computers, say N. If
1331 you have a system with more than one CPU, say Y.
1333 If you say N here, the kernel will run on single and multiprocessor
1334 machines, but will use only one CPU of a multiprocessor machine. If
1335 you say Y here, the kernel will run on many, but not all, single
1336 processor machines. On a single processor machine, the kernel will
1337 run faster if you say N here.
1339 See also <file:Documentation/i386/IO-APIC.txt>,
1340 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1341 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1343 If you don't know what to do here, say N.
1346 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1347 depends on EXPERIMENTAL
1348 depends on SMP && !XIP_KERNEL
1351 SMP kernels contain instructions which fail on non-SMP processors.
1352 Enabling this option allows the kernel to modify itself to make
1353 these instructions safe. Disabling it allows about 1K of space
1356 If you don't know what to do here, say Y.
1362 This option enables support for the ARM system coherency unit
1369 This options enables support for the ARM timer and watchdog unit
1372 prompt "Memory split"
1375 Select the desired split between kernel and user memory.
1377 If you are not absolutely sure what you are doing, leave this
1381 bool "3G/1G user/kernel split"
1383 bool "2G/2G user/kernel split"
1385 bool "1G/3G user/kernel split"
1390 default 0x40000000 if VMSPLIT_1G
1391 default 0x80000000 if VMSPLIT_2G
1395 int "Maximum number of CPUs (2-32)"
1401 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1402 depends on SMP && HOTPLUG && EXPERIMENTAL
1403 depends on !ARCH_MSM
1405 Say Y here to experiment with turning CPUs off and on. CPUs
1406 can be controlled through /sys/devices/system/cpu.
1409 bool "Use local timer interrupts"
1412 select HAVE_ARM_TWD if !ARCH_MSM_SCORPIONMP
1414 Enable support for local timers on SMP platforms, rather then the
1415 legacy IPI broadcast method. Local timers allows the system
1416 accounting to be spread across the timer interval, preventing a
1417 "thundering herd" at every timer tick.
1419 source kernel/Kconfig.preempt
1423 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1424 ARCH_S5P6442 || ARCH_S5PV210 || ARCH_S5PV310
1425 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1426 default AT91_TIMER_HZ if ARCH_AT91
1427 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1430 config THUMB2_KERNEL
1431 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1432 depends on CPU_V7 && !CPU_V6 && EXPERIMENTAL
1434 select ARM_ASM_UNIFIED
1436 By enabling this option, the kernel will be compiled in
1437 Thumb-2 mode. A compiler/assembler that understand the unified
1438 ARM-Thumb syntax is needed.
1442 config THUMB2_AVOID_R_ARM_THM_JUMP11
1443 bool "Work around buggy Thumb-2 short branch relocations in gas"
1444 depends on THUMB2_KERNEL && MODULES
1447 Various binutils versions can resolve Thumb-2 branches to
1448 locally-defined, preemptible global symbols as short-range "b.n"
1449 branch instructions.
1451 This is a problem, because there's no guarantee the final
1452 destination of the symbol, or any candidate locations for a
1453 trampoline, are within range of the branch. For this reason, the
1454 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1455 relocation in modules at all, and it makes little sense to add
1458 The symptom is that the kernel fails with an "unsupported
1459 relocation" error when loading some modules.
1461 Until fixed tools are available, passing
1462 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1463 code which hits this problem, at the cost of a bit of extra runtime
1464 stack usage in some cases.
1466 The problem is described in more detail at:
1467 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1469 Only Thumb-2 kernels are affected.
1471 Unless you are sure your tools don't have this problem, say Y.
1473 config ARM_ASM_UNIFIED
1477 bool "Use the ARM EABI to compile the kernel"
1479 This option allows for the kernel to be compiled using the latest
1480 ARM ABI (aka EABI). This is only useful if you are using a user
1481 space environment that is also compiled with EABI.
1483 Since there are major incompatibilities between the legacy ABI and
1484 EABI, especially with regard to structure member alignment, this
1485 option also changes the kernel syscall calling convention to
1486 disambiguate both ABIs and allow for backward compatibility support
1487 (selected with CONFIG_OABI_COMPAT).
1489 To use this you need GCC version 4.0.0 or later.
1492 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1493 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1496 This option preserves the old syscall interface along with the
1497 new (ARM EABI) one. It also provides a compatibility layer to
1498 intercept syscalls that have structure arguments which layout
1499 in memory differs between the legacy ABI and the new ARM EABI
1500 (only for non "thumb" binaries). This option adds a tiny
1501 overhead to all syscalls and produces a slightly larger kernel.
1502 If you know you'll be using only pure EABI user space then you
1503 can say N here. If this option is not selected and you attempt
1504 to execute a legacy ABI binary then the result will be
1505 UNPREDICTABLE (in fact it can be predicted that it won't work
1506 at all). If in doubt say Y.
1508 config ARCH_HAS_HOLES_MEMORYMODEL
1511 config ARCH_SPARSEMEM_ENABLE
1514 config ARCH_SPARSEMEM_DEFAULT
1515 def_bool ARCH_SPARSEMEM_ENABLE
1517 config ARCH_SELECT_MEMORY_MODEL
1518 def_bool ARCH_SPARSEMEM_ENABLE
1521 bool "High Memory Support (EXPERIMENTAL)"
1522 depends on MMU && EXPERIMENTAL
1524 The address space of ARM processors is only 4 Gigabytes large
1525 and it has to accommodate user address space, kernel address
1526 space as well as some memory mapped IO. That means that, if you
1527 have a large amount of physical memory and/or IO, not all of the
1528 memory can be "permanently mapped" by the kernel. The physical
1529 memory that is not permanently mapped is called "high memory".
1531 Depending on the selected kernel/user memory split, minimum
1532 vmalloc space and actual amount of RAM, you may not need this
1533 option which should result in a slightly faster kernel.
1538 bool "Allocate 2nd-level pagetables from highmem"
1540 depends on !OUTER_CACHE
1542 config HW_PERF_EVENTS
1543 bool "Enable hardware performance counter support for perf events"
1544 depends on PERF_EVENTS && CPU_HAS_PMU
1547 Enable hardware performance counter support for perf events. If
1548 disabled, perf events will use software events only.
1552 config FORCE_MAX_ZONEORDER
1553 int "Maximum zone order" if ARCH_SHMOBILE
1554 range 11 64 if ARCH_SHMOBILE
1555 default "9" if SA1111
1558 The kernel memory allocator divides physically contiguous memory
1559 blocks into "zones", where each zone is a power of two number of
1560 pages. This option selects the largest power of two that the kernel
1561 keeps in the memory allocator. If you need to allocate very large
1562 blocks of physically contiguous memory, then you may need to
1563 increase this value.
1565 This config option is actually maximum order plus one. For example,
1566 a value of 11 means that the largest free memory block is 2^10 pages.
1569 bool "Timer and CPU usage LEDs"
1570 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1571 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1572 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1573 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1574 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1575 ARCH_AT91 || ARCH_DAVINCI || \
1576 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1578 If you say Y here, the LEDs on your machine will be used
1579 to provide useful information about your current system status.
1581 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1582 be able to select which LEDs are active using the options below. If
1583 you are compiling a kernel for the EBSA-110 or the LART however, the
1584 red LED will simply flash regularly to indicate that the system is
1585 still functional. It is safe to say Y here if you have a CATS
1586 system, but the driver will do nothing.
1589 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1590 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1591 || MACH_OMAP_PERSEUS2
1593 depends on !GENERIC_CLOCKEVENTS
1594 default y if ARCH_EBSA110
1596 If you say Y here, one of the system LEDs (the green one on the
1597 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1598 will flash regularly to indicate that the system is still
1599 operational. This is mainly useful to kernel hackers who are
1600 debugging unstable kernels.
1602 The LART uses the same LED for both Timer LED and CPU usage LED
1603 functions. You may choose to use both, but the Timer LED function
1604 will overrule the CPU usage LED.
1607 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1609 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1610 || MACH_OMAP_PERSEUS2
1613 If you say Y here, the red LED will be used to give a good real
1614 time indication of CPU usage, by lighting whenever the idle task
1615 is not currently executing.
1617 The LART uses the same LED for both Timer LED and CPU usage LED
1618 functions. You may choose to use both, but the Timer LED function
1619 will overrule the CPU usage LED.
1621 config ALIGNMENT_TRAP
1623 depends on CPU_CP15_MMU
1624 default y if !ARCH_EBSA110
1625 select HAVE_PROC_CPU if PROC_FS
1627 ARM processors cannot fetch/store information which is not
1628 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1629 address divisible by 4. On 32-bit ARM processors, these non-aligned
1630 fetch/store instructions will be emulated in software if you say
1631 here, which has a severe performance impact. This is necessary for
1632 correct operation of some network protocols. With an IP-only
1633 configuration it is safe to say N, otherwise say Y.
1635 config UACCESS_WITH_MEMCPY
1636 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1637 depends on MMU && EXPERIMENTAL
1638 default y if CPU_FEROCEON
1640 Implement faster copy_to_user and clear_user methods for CPU
1641 cores where a 8-word STM instruction give significantly higher
1642 memory write throughput than a sequence of individual 32bit stores.
1644 A possible side effect is a slight increase in scheduling latency
1645 between threads sharing the same address space if they invoke
1646 such copy operations with large buffers.
1648 However, if the CPU data cache is using a write-allocate mode,
1649 this option is unlikely to provide any performance gain.
1653 prompt "Enable seccomp to safely compute untrusted bytecode"
1655 This kernel feature is useful for number crunching applications
1656 that may need to compute untrusted bytecode during their
1657 execution. By using pipes or other transports made available to
1658 the process as file descriptors supporting the read/write
1659 syscalls, it's possible to isolate those applications in
1660 their own address space using seccomp. Once seccomp is
1661 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1662 and the task is only allowed to execute a few safe syscalls
1663 defined by each seccomp mode.
1665 config CC_STACKPROTECTOR
1666 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1667 depends on EXPERIMENTAL
1669 This option turns on the -fstack-protector GCC feature. This
1670 feature puts, at the beginning of functions, a canary value on
1671 the stack just before the return address, and validates
1672 the value just before actually returning. Stack based buffer
1673 overflows (that need to overwrite this return address) now also
1674 overwrite the canary, which gets detected and the attack is then
1675 neutralized via a kernel panic.
1676 This feature requires gcc version 4.2 or above.
1678 config DEPRECATED_PARAM_STRUCT
1679 bool "Provide old way to pass kernel parameters"
1681 This was deprecated in 2001 and announced to live on for 5 years.
1682 Some old boot loaders still use this way.
1688 # Compressed boot loader in ROM. Yes, we really want to ask about
1689 # TEXT and BSS so we preserve their values in the config files.
1690 config ZBOOT_ROM_TEXT
1691 hex "Compressed ROM boot loader base address"
1694 The physical address at which the ROM-able zImage is to be
1695 placed in the target. Platforms which normally make use of
1696 ROM-able zImage formats normally set this to a suitable
1697 value in their defconfig file.
1699 If ZBOOT_ROM is not enabled, this has no effect.
1701 config ZBOOT_ROM_BSS
1702 hex "Compressed ROM boot loader BSS address"
1705 The base address of an area of read/write memory in the target
1706 for the ROM-able zImage which must be available while the
1707 decompressor is running. It must be large enough to hold the
1708 entire decompressed kernel plus an additional 128 KiB.
1709 Platforms which normally make use of ROM-able zImage formats
1710 normally set this to a suitable value in their defconfig file.
1712 If ZBOOT_ROM is not enabled, this has no effect.
1715 bool "Compressed boot loader in ROM/flash"
1716 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1718 Say Y here if you intend to execute your compressed kernel image
1719 (zImage) directly from ROM or flash. If unsure, say N.
1721 config ZBOOT_ROM_MMCIF
1722 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1723 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1725 Say Y here to include experimental MMCIF loading code in the
1726 ROM-able zImage. With this enabled it is possible to write the
1727 the ROM-able zImage kernel image to an MMC card and boot the
1728 kernel straight from the reset vector. At reset the processor
1729 Mask ROM will load the first part of the the ROM-able zImage
1730 which in turn loads the rest the kernel image to RAM using the
1731 MMCIF hardware block.
1734 string "Default kernel command string"
1737 On some architectures (EBSA110 and CATS), there is currently no way
1738 for the boot loader to pass arguments to the kernel. For these
1739 architectures, you should supply some command-line options at build
1740 time by entering them here. As a minimum, you should specify the
1741 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1743 config CMDLINE_FORCE
1744 bool "Always use the default kernel command string"
1745 depends on CMDLINE != ""
1747 Always use the default kernel command string, even if the boot
1748 loader passes other arguments to the kernel.
1749 This is useful if you cannot or don't want to change the
1750 command-line options your boot loader passes to the kernel.
1755 bool "Kernel Execute-In-Place from ROM"
1756 depends on !ZBOOT_ROM
1758 Execute-In-Place allows the kernel to run from non-volatile storage
1759 directly addressable by the CPU, such as NOR flash. This saves RAM
1760 space since the text section of the kernel is not loaded from flash
1761 to RAM. Read-write sections, such as the data section and stack,
1762 are still copied to RAM. The XIP kernel is not compressed since
1763 it has to run directly from flash, so it will take more space to
1764 store it. The flash address used to link the kernel object files,
1765 and for storing it, is configuration dependent. Therefore, if you
1766 say Y here, you must know the proper physical address where to
1767 store the kernel image depending on your own flash memory usage.
1769 Also note that the make target becomes "make xipImage" rather than
1770 "make zImage" or "make Image". The final kernel binary to put in
1771 ROM memory will be arch/arm/boot/xipImage.
1775 config XIP_PHYS_ADDR
1776 hex "XIP Kernel Physical Location"
1777 depends on XIP_KERNEL
1778 default "0x00080000"
1780 This is the physical address in your flash memory the kernel will
1781 be linked for and stored to. This address is dependent on your
1785 bool "Kexec system call (EXPERIMENTAL)"
1786 depends on EXPERIMENTAL
1788 kexec is a system call that implements the ability to shutdown your
1789 current kernel, and to start another kernel. It is like a reboot
1790 but it is independent of the system firmware. And like a reboot
1791 you can start any kernel with it, not just Linux.
1793 It is an ongoing process to be certain the hardware in a machine
1794 is properly shutdown, so do not be surprised if this code does not
1795 initially work for you. It may help to enable device hotplugging
1799 bool "Export atags in procfs"
1803 Should the atags used to boot the kernel be exported in an "atags"
1804 file in procfs. Useful with kexec.
1807 bool "Build kdump crash kernel (EXPERIMENTAL)"
1808 depends on EXPERIMENTAL
1810 Generate crash dump after being started by kexec. This should
1811 be normally only set in special crash dump kernels which are
1812 loaded in the main kernel with kexec-tools into a specially
1813 reserved region and then later executed after a crash by
1814 kdump/kexec. The crash dump kernel must be compiled to a
1815 memory address not used by the main kernel
1817 For more details see Documentation/kdump/kdump.txt
1819 config AUTO_ZRELADDR
1820 bool "Auto calculation of the decompressed kernel image address"
1821 depends on !ZBOOT_ROM && !ARCH_U300
1823 ZRELADDR is the physical address where the decompressed kernel
1824 image will be placed. If AUTO_ZRELADDR is selected, the address
1825 will be determined at run-time by masking the current IP with
1826 0xf8000000. This assumes the zImage being placed in the first 128MB
1827 from start of memory.
1831 menu "CPU Power Management"
1835 source "drivers/cpufreq/Kconfig"
1838 tristate "CPUfreq driver for i.MX CPUs"
1839 depends on ARCH_MXC && CPU_FREQ
1841 This enables the CPUfreq driver for i.MX CPUs.
1843 config CPU_FREQ_SA1100
1846 config CPU_FREQ_SA1110
1849 config CPU_FREQ_INTEGRATOR
1850 tristate "CPUfreq driver for ARM Integrator CPUs"
1851 depends on ARCH_INTEGRATOR && CPU_FREQ
1854 This enables the CPUfreq driver for ARM Integrator CPUs.
1856 For details, take a look at <file:Documentation/cpu-freq>.
1862 depends on CPU_FREQ && ARCH_PXA && PXA25x
1864 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1866 config CPU_FREQ_S3C64XX
1867 bool "CPUfreq support for Samsung S3C64XX CPUs"
1868 depends on CPU_FREQ && CPU_S3C6410
1873 Internal configuration node for common cpufreq on Samsung SoC
1875 config CPU_FREQ_S3C24XX
1876 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1877 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1880 This enables the CPUfreq driver for the Samsung S3C24XX family
1883 For details, take a look at <file:Documentation/cpu-freq>.
1887 config CPU_FREQ_S3C24XX_PLL
1888 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1889 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1891 Compile in support for changing the PLL frequency from the
1892 S3C24XX series CPUfreq driver. The PLL takes time to settle
1893 after a frequency change, so by default it is not enabled.
1895 This also means that the PLL tables for the selected CPU(s) will
1896 be built which may increase the size of the kernel image.
1898 config CPU_FREQ_S3C24XX_DEBUG
1899 bool "Debug CPUfreq Samsung driver core"
1900 depends on CPU_FREQ_S3C24XX
1902 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1904 config CPU_FREQ_S3C24XX_IODEBUG
1905 bool "Debug CPUfreq Samsung driver IO timing"
1906 depends on CPU_FREQ_S3C24XX
1908 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
1910 config CPU_FREQ_S3C24XX_DEBUGFS
1911 bool "Export debugfs for CPUFreq"
1912 depends on CPU_FREQ_S3C24XX && DEBUG_FS
1914 Export status information via debugfs.
1918 source "drivers/cpuidle/Kconfig"
1922 menu "Floating point emulation"
1924 comment "At least one emulation must be selected"
1927 bool "NWFPE math emulation"
1928 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1930 Say Y to include the NWFPE floating point emulator in the kernel.
1931 This is necessary to run most binaries. Linux does not currently
1932 support floating point hardware so you need to say Y here even if
1933 your machine has an FPA or floating point co-processor podule.
1935 You may say N here if you are going to load the Acorn FPEmulator
1936 early in the bootup.
1939 bool "Support extended precision"
1940 depends on FPE_NWFPE
1942 Say Y to include 80-bit support in the kernel floating-point
1943 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1944 Note that gcc does not generate 80-bit operations by default,
1945 so in most cases this option only enlarges the size of the
1946 floating point emulator without any good reason.
1948 You almost surely want to say N here.
1951 bool "FastFPE math emulation (EXPERIMENTAL)"
1952 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
1954 Say Y here to include the FAST floating point emulator in the kernel.
1955 This is an experimental much faster emulator which now also has full
1956 precision for the mantissa. It does not support any exceptions.
1957 It is very simple, and approximately 3-6 times faster than NWFPE.
1959 It should be sufficient for most programs. It may be not suitable
1960 for scientific calculations, but you have to check this for yourself.
1961 If you do not feel you need a faster FP emulation you should better
1965 bool "VFP-format floating point maths"
1966 depends on CPU_V6 || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1968 Say Y to include VFP support code in the kernel. This is needed
1969 if your hardware includes a VFP unit.
1971 Please see <file:Documentation/arm/VFP/release-notes.txt> for
1972 release notes and additional status information.
1974 Say N if your target does not have VFP hardware.
1982 bool "Advanced SIMD (NEON) Extension support"
1983 depends on VFPv3 && CPU_V7
1985 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1990 menu "Userspace binary formats"
1992 source "fs/Kconfig.binfmt"
1995 tristate "RISC OS personality"
1998 Say Y here to include the kernel code necessary if you want to run
1999 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2000 experimental; if this sounds frightening, say N and sleep in peace.
2001 You can also say M here to compile this support as a module (which
2002 will be called arthur).
2006 menu "Power management options"
2008 source "kernel/power/Kconfig"
2010 config ARCH_SUSPEND_POSSIBLE
2015 source "net/Kconfig"
2017 source "drivers/Kconfig"
2021 source "arch/arm/Kconfig.debug"
2023 source "security/Kconfig"
2025 source "crypto/Kconfig"
2027 source "lib/Kconfig"