xloader: Panda - fix ROM OTG boot path

When the OMAP 4 on Panda sees that USB OTG external power is present,
it changes the boot flow in the ROM to try to boot via that before
trying MMC1.  If it isn't satisfied, it falls through to try MMC1.

Without this patch, under those conditions X-Loader is unable to
update the DPLL as it needs to do during dram initialization, because
the EMIF never goes idle allowing the shadow update mechanism to
apply the new settings.

It therefore loops for a long period waiting to confirm the settings
applied and boot is hung (with LEDs off, so the device looks OFF).

This patch re-enables EMIF idle which was previously commented out with
"No IDLE: BUG in SDC" to allow the new DPLL settings to apply.

With the patch against http://gitorious.org/x-loader HEAD the Panda is
able to boot from either USB OTG power applied or DC Jack power OK.

Note that I saw peak current during boot of 650mA, higher than the
500mA allowed by USB.  It may go higher with other peripherals enabled
or trying to use USB host on Panda.

Signed-off-by: Andy Green <andy.green@linaro.org>
Signed-off-by: Anand Gadiyar <gadiyar@ti.com>

diff --git a/board/omap4430panda/clock.c b/board/omap4430panda/clock.c
index 454f7ce..d1f6903 100644 (file)
--- a/board/omap4430panda/clock.c
+++ b/board/omap4430panda/clock.c
@@ -536,6 +536,12 @@ void lock_core_dpll_shadow(void)
         */
        __raw_writel(0x70D | (dpll_param_p->m2 << 11), 0x4A004260);
 
+       /*
+        * if the EMIF never goes idle, and eg, if ROM enabled USB,
+        * we loop for a very very long time here becuse shadow updates wait
+        * until EMIF idle
+        */
+
        /* Wait for Freq_Update to get cleared: CM_SHADOW_FREQ_CONFIG1 */
        while (__raw_readl(0x4A004260) & 1)
                ;

diff --git a/board/omap4430panda/omap4430panda.c b/board/omap4430panda/omap4430panda.c
index 0f95c39..3acd8b5 100644 (file)
--- a/board/omap4430panda/omap4430panda.c
+++ b/board/omap4430panda/omap4430panda.c
@@ -438,6 +438,20 @@ static void ddr_init(void)
         */
        configure_core_dpll_no_lock();
 
+       /*
+        * the following is re-enabled because without the EMIF going idle,
+        * the shadow DPLL update scheme can delay for minutes until it is
+        * able to apply the new settings... it waits until EMIF idle.
+        *
+        * This is seen in the case the ROM enabled USB boot being tried before
+        * normal boot over MMC.
+        */
+
+       /* No IDLE: BUG in SDC */
+       sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x2);
+       while ((__raw_readl(CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700)
+               ;
+
        __raw_writel(0, EMIF1_BASE + EMIF_PWR_MGMT_CTRL);
        __raw_writel(0, EMIF2_BASE + EMIF_PWR_MGMT_CTRL);
 
@@ -645,7 +659,14 @@ void s_init(void)
 {
        unsigned int rev = omap_revision();
 
+       /*
+        * this is required to survive the muxconf in the case the ROM
+        * started up USB OTG
+        */
+       prcm_init();
+
        set_muxconf_regs();
+
        delay(100);
 
        /* Writing to AuxCR in U-boot using SMI for GP/EMU DEV */
@@ -660,7 +681,6 @@ void s_init(void)
 #if defined(CONFIG_MPU_600) || defined(CONFIG_MPU_1000)
        scale_vcores();
 #endif
-       prcm_init();
 
        if (rev != OMAP4430_ES1_0) {
                if (__raw_readl(0x4805D138) & (1<<22)) {