-
- if (rev == OMAP4430_ES1_0)
- return;
-
- if (__raw_readl(OMAP44XX_GPIO_BASE6 + __GPIO_DATAIN) & (1 << 22)) {
- /* enable software ioreq */
- sr32(OMAP44XX_SCRM_AUXCLK3, 8, 1, 0x1);
- /* set for sys_clk (38.4MHz) */
- sr32(OMAP44XX_SCRM_AUXCLK3, 1, 2, 0x0);
- /* set divisor to 2 */
- sr32(OMAP44XX_SCRM_AUXCLK3, 16, 4, 0x1);
- /* set the clock source to active */
- sr32(OMAP44XX_SCRM_ALTCLKSRC, 0, 1, 0x1);
- /* enable clocks */
- sr32(OMAP44XX_SCRM_ALTCLKSRC, 2, 2, 0x3);
- } else {
- /* enable software ioreq */
- sr32(OMAP44XX_SCRM_AUXCLK1, 8, 1, 0x1);
- /* set for PER_DPLL */
- sr32(OMAP44XX_SCRM_AUXCLK1, 1, 2, 0x2);
- /* set divisor to 16 */
- sr32(OMAP44XX_SCRM_AUXCLK1, 16, 4, 0xf);
- /* set the clock source to active */
- sr32(OMAP44XX_SCRM_ALTCLKSRC, 0, 1, 0x1);
- /* enable clocks */
- sr32(OMAP44XX_SCRM_ALTCLKSRC, 2, 2, 0x3);
- }