2 * Copyright 2005 (C) Texas Instruments, <www.ti.com>
4 * Texas Instruments, <www.ti.com>
5 * Richard Woodruff <r-woodruff2@ti.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #ifndef _OMAP24XX_SYS_INFO_H_
27 #define _OMAP24XX_SYS_INFO_H_
30 typedef struct h4_system_data {
32 u32 base_b_rev; /* rev from base board i2c */
34 u32 cpu_b_rev; /* rev from cpu board i2c */
35 u32 cpu_b_mux; /* mux type on daughter board */
36 u32 cpu_b_ddr_type; /* mem type */
37 u32 cpu_b_ddr_speed; /* ddr speed rating */
38 u32 cpu_b_switches; /* boot ctrl switch settings */
40 u32 cpu_type; /* type of cpu; 2420, 2422, 2430,...*/
41 u32 cpu_rev; /* rev of given cpu; ES1, ES2,...*/
46 #define XDR_POP 5 /* package on package part */
47 #define SDR_DISCRETE 4 /* 128M memory SDR module*/
48 #define DDR_STACKED 3 /* stacked part on 2422 */
49 #define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */
50 #define DDR_DISCRETE 1 /* 2x16 parts on daughter card */
52 #define DDR_100 100 /* type found on most mem d-boards */
53 #define DDR_111 111 /* some combo parts */
54 #define DDR_133 133 /* most combo, some mem d-boards */
55 #define DDR_165 165 /* future parts */
57 #define CPU_2420 0x2420
58 #define CPU_2422 0x2422 /* 2420 + 64M stacked */
59 #define CPU_2423 0x2423 /* 2420 + 96M stacked */
60 #define CPU_2430 0x2430
62 /* 242x real hardware:
77 #define CPU_2422_ES1 1
78 #define CPU_2422_ES2 2
79 #define CPU_2422_ES2_05 3
80 #define CPU_2422_ES2_1 4
81 #define CPU_2422_ES2_1_1 5
83 #define CPU_2420_ES1 1
84 #define CPU_2420_ES2 2
85 #define CPU_2420_ES2_05 3
86 #define CPU_2420_ES2_1 4
87 #define CPU_2420_ES2_1_1 5
89 #define CPU_242X_ES1 1
90 #define CPU_242X_ES2 2
91 #define CPU_242X_ES2_05 3
92 #define CPU_242X_ES2_1 4
93 #define CPU_242X_ES2_1_1 5
95 #define CPU_2420_2422_ES1 1
96 #define CPU_2420_2422_ES2_1 4
98 /* 243x real hardware:
106 #define CPU_2430_ES1 1
107 #define CPU_2430_ES2 2
110 # define CPU_2430_VIRTIO 3
112 # define CPU_2430_VIRTIO 1
114 #define CPU_2430_ZEBU 0xD
116 #define CPU_2420_CHIPID 0x0B5D9000
117 #define CPU_2430_CHIPID 0x0B68A000
118 #define CPU_24XX_ID_MASK 0x0FFFF000
119 #define CPU_242X_REV_MASK 0xF0000000
120 #define CPU_242X_PID_MASK 0x000F0000
122 #define BOARD_H4_MENELAUS 1
123 #define BOARD_H4_SDP 2
124 #define BOARD_H4_MENELAUS_HRP 3
125 #define BOARD_SDP_2430 4
128 #define GPMC_NONMUXED 0
130 #define TYPE_NAND 0x800 /* bit pos for nand in gpmc reg */
131 #define TYPE_NOR 0x000
132 #define TYPE_ONENAND 0x800
134 #define WIDTH_8BIT 0x0000
135 #define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */
137 #define I2C_MENELAUS 0x72 /* i2c id for companion chip */