3 * Texas Instruments, <www.ti.com>
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Rajendra Nayak <rnayak@ti.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/arch/cpu.h>
26 #include <asm/arch/bits.h>
27 #include <asm/arch/clocks.h>
28 #include <asm/arch/mem.h>
29 #include <asm/arch/sys_proto.h>
30 #include <asm/arch/sys_info.h>
31 #include <asm/arch/clocks443x.h>
34 #define CONFIG_OMAP4_SDC 1
36 /* Used to index into DPLL parameter tables */
48 /* Tables having M,N,M2 et al values for different sys_clk speeds
49 * This table is generated only for OPP100
50 * The tables are organized as follows:
51 * Rows : 1 - 12M, 2 - 13M, 3 - 16.8M, 4 - 19.2M, 5 - 26M, 6 - 27M, 7 - 38.4M
55 struct dpll_param mpu_dpll_param[7] = {
57 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
59 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
61 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
63 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
65 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
67 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
70 /* RUN MPU @ 600 MHz */
71 {0x7d, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00},
73 {0x69, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00},
75 {0x1a, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00},
80 struct dpll_param iva_dpll_param[7] = {
82 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
84 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
86 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
88 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
90 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
92 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
94 #ifdef CONFIG_OMAP4_SDC
95 {0x61, 0x03, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00},
97 {0x61, 0x03, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00},
101 /* CORE parameters */
102 struct dpll_param core_dpll_param[7] = {
104 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
106 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
108 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
110 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
112 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
114 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
115 /* 38.4M values - DDR@200MHz*/
116 {0x7d, 0x05, 0x02, 0x05, 0x08, 0x04, 0x06, 0x05},
119 /* CORE parameters - ES2.1 */
120 struct dpll_param core_dpll_param_ddr400[7] = {
122 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
124 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
126 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
128 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
130 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
132 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
133 /* 38.4M values - DDR@400MHz*/
134 {0x7d, 0x05, 0x01, 0x05, 0x08, 0x04, 0x06, 0x05},
137 /* CORE parameters for L3 at 190 MHz - For ES1 only*/
138 struct dpll_param core_dpll_param_l3_190[7] = {
140 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
142 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
144 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
146 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
148 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
150 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
152 #ifdef CONFIG_OMAP4_SDC
154 {0x1f0, 0x18, 0x01, 0x05, 0x08, 0x04, 0x06, 0x05},
155 #else /* Default CORE @166MHz */
156 {0x1b0, 0x18, 0x01, 0x05, 0x08, 0x04, 0x06, 0x05},
159 {0x7d, 0x05, 0x01, 0x05, 0x08, 0x04, 0x06, 0x08},
164 struct dpll_param per_dpll_param[7] = {
166 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
168 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
170 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
172 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
174 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
176 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
180 {0x0a, 0x00, 0x04, 0x03, 0x06, 0x05, 0x02, 0x03},
182 {0x14, 0x00, 0x08, 0x06, 0x0c, 0x09, 0x04, 0x05},
186 struct dpll_param abe_dpll_param[7] = {
188 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
190 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
192 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
194 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
196 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
198 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
200 #ifdef CONFIG_OMAP4_SDC
201 {0x40, 0x18, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0},
203 {0x40, 0x18, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0},
208 struct dpll_param usb_dpll_param[7] = {
210 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
212 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
214 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
216 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
218 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
220 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
222 #ifdef CONFIG_OMAP4_SDC
223 {0x32, 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0},
225 {0x32, 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0},
229 static void configure_mpu_dpll(u32 clk_index)
231 struct dpll_param *dpll_param_p;
233 /* Unlock the MPU dpll */
234 sr32(CM_CLKMODE_DPLL_MPU, 0, 3, PLL_MN_POWER_BYPASS);
235 wait_on_value(BIT0, 0, CM_IDLEST_DPLL_MPU, LDELAY);
237 /* Program MPU DPLL */
238 dpll_param_p = &mpu_dpll_param[clk_index];
240 sr32(CM_AUTOIDLE_DPLL_MPU, 0, 3, 0x0); /* Disable DPLL autoidle */
242 /* Set M,N,M2 values */
243 sr32(CM_CLKSEL_DPLL_MPU, 8, 11, dpll_param_p->m);
244 sr32(CM_CLKSEL_DPLL_MPU, 0, 6, dpll_param_p->n);
245 sr32(CM_DIV_M2_DPLL_MPU, 0, 5, dpll_param_p->m2);
246 sr32(CM_DIV_M2_DPLL_MPU, 8, 1, 0x1);
248 /* Lock the mpu dpll */
249 sr32(CM_CLKMODE_DPLL_MPU, 0, 3, PLL_LOCK | 0x10);
250 wait_on_value(BIT0, 1, CM_IDLEST_DPLL_MPU, LDELAY);
253 static void configure_iva_dpll(u32 clk_index)
255 struct dpll_param *dpll_param_p;
257 /* Unlock the IVA dpll */
258 sr32(CM_CLKMODE_DPLL_IVA, 0, 3, PLL_MN_POWER_BYPASS);
259 wait_on_value(BIT0, 0, CM_IDLEST_DPLL_IVA, LDELAY);
261 /* CM_BYPCLK_DPLL_IVA = CORE_X2_CLK/2 */
262 sr32(CM_BYPCLK_DPLL_IVA, 0, 2, 0x1);
264 /* Program IVA DPLL */
265 dpll_param_p = &iva_dpll_param[clk_index];
267 sr32(CM_AUTOIDLE_DPLL_IVA, 0, 3, 0x0); /* Disable DPLL autoidle */
270 sr32(CM_CLKSEL_DPLL_IVA, 8, 11, dpll_param_p->m);
271 sr32(CM_CLKSEL_DPLL_IVA, 0, 7, dpll_param_p->n);
272 sr32(CM_DIV_M4_DPLL_IVA, 0, 5, dpll_param_p->m4);
273 sr32(CM_DIV_M4_DPLL_IVA, 8, 1, 0x1);
274 sr32(CM_DIV_M5_DPLL_IVA, 0, 5, dpll_param_p->m5);
275 sr32(CM_DIV_M5_DPLL_IVA, 8, 1, 0x1);
277 /* Lock the iva dpll */
278 sr32(CM_CLKMODE_DPLL_IVA, 0, 3, PLL_LOCK);
279 wait_on_value(BIT0, 1, CM_IDLEST_DPLL_IVA, LDELAY);
282 static void configure_per_dpll(u32 clk_index)
284 struct dpll_param *dpll_param_p;
286 /* Unlock the PER dpll */
287 sr32(CM_CLKMODE_DPLL_PER, 0, 3, PLL_MN_POWER_BYPASS);
288 wait_on_value(BIT0, 0, CM_IDLEST_DPLL_PER, LDELAY);
290 /* Program PER DPLL */
291 dpll_param_p = &per_dpll_param[clk_index];
293 /* Disable autoidle */
294 sr32(CM_AUTOIDLE_DPLL_PER, 0, 3, 0x0);
296 sr32(CM_CLKSEL_DPLL_PER, 8, 11, dpll_param_p->m);
297 sr32(CM_CLKSEL_DPLL_PER, 0, 6, dpll_param_p->n);
298 sr32(CM_DIV_M2_DPLL_PER, 0, 5, dpll_param_p->m2);
299 sr32(CM_DIV_M3_DPLL_PER, 0, 5, dpll_param_p->m3);
300 sr32(CM_DIV_M4_DPLL_PER, 0, 5, dpll_param_p->m4);
301 sr32(CM_DIV_M5_DPLL_PER, 0, 5, dpll_param_p->m5);
302 sr32(CM_DIV_M6_DPLL_PER, 0, 5, dpll_param_p->m6);
303 sr32(CM_DIV_M7_DPLL_PER, 0, 5, dpll_param_p->m7);
306 sr32(CM_DIV_M2_DPLL_PER, 8, 1, 0x1);
307 sr32(CM_DIV_M3_DPLL_PER, 8, 1, 0x1);
308 sr32(CM_DIV_M4_DPLL_PER, 8, 1, 0x1);
309 sr32(CM_DIV_M5_DPLL_PER, 8, 1, 0x1);
310 sr32(CM_DIV_M6_DPLL_PER, 8, 1, 0x1);
311 sr32(CM_DIV_M7_DPLL_PER, 8, 1, 0x1);
313 /* Lock the per dpll */
314 sr32(CM_CLKMODE_DPLL_PER, 0, 3, PLL_LOCK);
315 wait_on_value(BIT0, 1, CM_IDLEST_DPLL_PER, LDELAY);
318 static void configure_abe_dpll(u32 clk_index)
320 struct dpll_param *dpll_param_p;
322 /* Select sys_clk as ref clk for ABE dpll */
323 sr32(CM_ABE_PLL_REF_CLKSEL, 0, 32, 0x0);
325 /* Unlock the ABE dpll */
326 sr32(CM_CLKMODE_DPLL_ABE, 0, 3, PLL_MN_POWER_BYPASS);
327 wait_on_value(BIT0, 0, CM_IDLEST_DPLL_ABE, LDELAY);
329 /* Program ABE DPLL */
330 dpll_param_p = &abe_dpll_param[clk_index];
332 /* Disable autoidle */
333 sr32(CM_AUTOIDLE_DPLL_ABE, 0, 3, 0x0);
335 sr32(CM_CLKSEL_DPLL_ABE, 8, 11, dpll_param_p->m);
336 sr32(CM_CLKSEL_DPLL_ABE, 0, 6, dpll_param_p->n);
338 /* Force DPLL CLKOUTHIF to stay enabled */
339 sr32(CM_DIV_M2_DPLL_ABE, 0, 32, 0x500);
340 sr32(CM_DIV_M2_DPLL_ABE, 0, 5, dpll_param_p->m2);
341 sr32(CM_DIV_M2_DPLL_ABE, 8, 1, 0x1);
342 /* Force DPLL CLKOUTHIF to stay enabled */
343 sr32(CM_DIV_M3_DPLL_ABE, 0, 32, 0x100);
344 sr32(CM_DIV_M3_DPLL_ABE, 0, 5, dpll_param_p->m3);
345 sr32(CM_DIV_M3_DPLL_ABE, 8, 1, 0x1);
347 /* Lock the abe dpll */
348 sr32(CM_CLKMODE_DPLL_ABE, 0, 3, PLL_LOCK);
349 wait_on_value(BIT0, 1, CM_IDLEST_DPLL_ABE, LDELAY);
352 static void configure_usb_dpll(u32 clk_index)
354 struct dpll_param *dpll_param_p;
356 /* Select the 60Mhz clock 480/8 = 60*/
357 sr32(CM_CLKSEL_USB_60MHz, 0, 32, 0x1);
359 /* Unlock the USB dpll */
360 sr32(CM_CLKMODE_DPLL_USB, 0, 3, PLL_MN_POWER_BYPASS);
361 wait_on_value(BIT0, 0, CM_IDLEST_DPLL_USB, LDELAY);
363 /* Program USB DPLL */
364 dpll_param_p = &usb_dpll_param[clk_index];
366 /* Disable autoidle */
367 sr32(CM_AUTOIDLE_DPLL_USB, 0, 3, 0x0);
369 sr32(CM_CLKSEL_DPLL_USB, 8, 11, dpll_param_p->m);
370 sr32(CM_CLKSEL_DPLL_USB, 0, 6, dpll_param_p->n);
372 /* Force DPLL CLKOUT to stay active */
373 sr32(CM_DIV_M2_DPLL_USB, 0, 32, 0x100);
374 sr32(CM_DIV_M2_DPLL_USB, 0, 5, dpll_param_p->m2);
375 sr32(CM_DIV_M2_DPLL_USB, 8, 1, 0x1);
376 sr32(CM_CLKDCOLDO_DPLL_USB, 8, 1, 0x1);
378 /* Lock the usb dpll */
379 sr32(CM_CLKMODE_DPLL_USB, 0, 3, PLL_LOCK);
380 wait_on_value(BIT0, 1, CM_IDLEST_DPLL_USB, LDELAY);
382 /* force enable the CLKDCOLDO clock */
383 sr32(CM_CLKDCOLDO_DPLL_USB, 0, 32, 0x100);
388 /* to remove warning about unused function; will be deleted in decruft patch */
389 static void configure_core_dpll(int clk_index)
391 struct dpll_param *dpll_param_p;
393 /* Get the sysclk speed from cm_sys_clksel
394 * Set it to 38.4 MHz, in case ROM code is bypassed
399 /* CORE_CLK=CORE_X2_CLK/2, L3_CLK=CORE_CLK/2, L4_CLK=L3_CLK/2 */
400 sr32(CM_CLKSEL_CORE, 0, 32, 0x110);
402 /* Unlock the CORE dpll */
403 sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_MN_POWER_BYPASS);
404 wait_on_value(BIT0, 0, CM_IDLEST_DPLL_CORE, LDELAY);
406 /* Program Core DPLL */
407 switch (omap_revision()) {
409 dpll_param_p = &core_dpll_param_l3_190[clk_index];
412 dpll_param_p = &core_dpll_param[clk_index];
416 dpll_param_p = &core_dpll_param_ddr400[clk_index];
420 /* Disable autoidle */
421 sr32(CM_AUTOIDLE_DPLL_CORE, 0, 3, 0x0);
423 sr32(CM_CLKSEL_DPLL_CORE, 8, 11, dpll_param_p->m);
424 sr32(CM_CLKSEL_DPLL_CORE, 0, 6, dpll_param_p->n);
425 sr32(CM_DIV_M2_DPLL_CORE, 0, 5, dpll_param_p->m2);
426 sr32(CM_DIV_M3_DPLL_CORE, 0, 5, dpll_param_p->m3);
427 sr32(CM_DIV_M4_DPLL_CORE, 0, 5, dpll_param_p->m4);
428 sr32(CM_DIV_M5_DPLL_CORE, 0, 5, dpll_param_p->m5);
429 sr32(CM_DIV_M6_DPLL_CORE, 0, 5, dpll_param_p->m6);
430 sr32(CM_DIV_M7_DPLL_CORE, 0, 5, dpll_param_p->m7);
432 if (omap_revision() == OMAP4430_ES1_0) {
433 /* Do this only on ES1.0 */
434 sr32(CM_DIV_M2_DPLL_CORE, 8, 1, 0x1);
435 sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1);
436 sr32(CM_DIV_M4_DPLL_CORE, 8, 1, 0x1);
437 sr32(CM_DIV_M5_DPLL_CORE, 8, 1, 0x1);
438 sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x0);
439 sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1);
442 /* Lock the core dpll */
443 sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_LOCK);
444 wait_on_value(BIT0, 1, CM_IDLEST_DPLL_CORE, LDELAY);
448 void configure_core_dpll_no_lock(void)
450 struct dpll_param *dpll_param_p = NULL;
453 /* Get the sysclk speed from cm_sys_clksel
454 * Set it to 38.4 MHz, in case ROM code is bypassed
456 __raw_writel(0x7, CM_SYS_CLKSEL);
459 clk_index = clk_index - 1;
460 /* CORE_CLK=CORE_X2_CLK/2, L3_CLK=CORE_CLK/2, L4_CLK=L3_CLK/2 */
461 sr32(CM_CLKSEL_CORE, 0, 32, 0x110);
463 /* Unlock the CORE dpll */
464 sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_MN_POWER_BYPASS);
465 wait_on_value(BIT0, 0, CM_IDLEST_DPLL_CORE, LDELAY);
467 /* Program Core DPLL */
468 switch (omap_revision()) {
470 dpll_param_p = &core_dpll_param_l3_190[clk_index];
473 dpll_param_p = &core_dpll_param[clk_index];
477 dpll_param_p = &core_dpll_param_ddr400[clk_index];
481 /* Disable autoidle */
482 sr32(CM_AUTOIDLE_DPLL_CORE, 0, 3, 0x0);
484 sr32(CM_CLKSEL_DPLL_CORE, 8, 11, dpll_param_p->m);
485 sr32(CM_CLKSEL_DPLL_CORE, 0, 6, dpll_param_p->n);
486 sr32(CM_DIV_M2_DPLL_CORE, 0, 5, dpll_param_p->m2);
487 sr32(CM_DIV_M3_DPLL_CORE, 0, 5, dpll_param_p->m3);
488 sr32(CM_DIV_M4_DPLL_CORE, 0, 5, dpll_param_p->m4);
489 sr32(CM_DIV_M5_DPLL_CORE, 0, 5, dpll_param_p->m5);
490 sr32(CM_DIV_M6_DPLL_CORE, 0, 5, dpll_param_p->m6);
491 sr32(CM_DIV_M7_DPLL_CORE, 0, 5, dpll_param_p->m7);
493 sr32(CM_DIV_M2_DPLL_CORE, 8, 1, 0x1);
494 sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1);
495 sr32(CM_DIV_M4_DPLL_CORE, 8, 1, 0x1);
496 sr32(CM_DIV_M5_DPLL_CORE, 8, 1, 0x1);
497 sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x0);
498 sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1);
501 void lock_core_dpll(void)
503 /* Lock the core dpll */
504 sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_LOCK);
505 wait_on_value(BIT0, 1, CM_IDLEST_DPLL_CORE, LDELAY);
508 void lock_core_dpll_shadow(void)
510 struct dpll_param *dpll_param_p = NULL;
512 /* Lock the core dpll using freq update method */
513 __raw_writel(10, 0x4A004120); /* CM_CLKMODE_DPLL_CORE */
515 switch (omap_revision()) {
517 dpll_param_p = &core_dpll_param_l3_190[6];
520 dpll_param_p = &core_dpll_param[6];
524 dpll_param_p = &core_dpll_param_ddr400[6];
528 /* CM_SHADOW_FREQ_CONFIG1: DLL_OVERRIDE = 1(hack), DLL_RESET = 1,
529 * DPLL_CORE_M2_DIV =1, DPLL_CORE_DPLL_EN = 0x7, FREQ_UPDATE = 1
531 __raw_writel(0x70D | (dpll_param_p->m2 << 11), 0x4A004260);
534 * if the EMIF never goes idle, and eg, if ROM enabled USB,
535 * we loop for a very very long time here becuse shadow updates wait
539 /* Wait for Freq_Update to get cleared: CM_SHADOW_FREQ_CONFIG1 */
540 while (__raw_readl(0x4A004260) & 1)
543 /* Wait for DPLL to Lock : CM_IDLEST_DPLL_CORE */
544 wait_on_value(BIT0, 1, CM_IDLEST_DPLL_CORE, LDELAY);
545 /* lock_core_dpll(); */
548 static void enable_all_clocks(void)
550 /* Enable Ducati clocks */
551 sr32(CM_DUCATI_DUCATI_CLKCTRL, 0, 32, 0x1);
552 sr32(CM_DUCATI_CLKSTCTRL, 0, 32, 0x2);
554 wait_on_value(BIT8, BIT8, CM_DUCATI_CLKSTCTRL, LDELAY);
556 /* Enable ivahd and sl2 clocks */
557 sr32(IVAHD_IVAHD_CLKCTRL, 0, 32, 0x1);
558 sr32(IVAHD_SL2_CLKCTRL, 0, 32, 0x1);
559 sr32(IVAHD_CLKSTCTRL, 0, 32, 0x2);
561 wait_on_value(BIT8, BIT8, IVAHD_CLKSTCTRL, LDELAY);
563 /* Enable Tesla clocks */
564 sr32(DSP_DSP_CLKCTRL, 0, 32, 0x1);
565 sr32(DSP_CLKSTCTRL, 0, 32, 0x2);
567 wait_on_value(BIT8, BIT8, DSP_CLKSTCTRL, LDELAY);
569 /* wait for tesla to become accessible */
572 sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x3);
573 sr32(CM1_ABE_AESS_CLKCTRL, 0, 32, 0x2);
574 sr32(CM1_ABE_PDM_CLKCTRL, 0, 32, 0x2);
575 sr32(CM1_ABE_DMIC_CLKCTRL, 0, 32, 0x2);
576 sr32(CM1_ABE_MCASP_CLKCTRL, 0, 32, 0x2);
577 sr32(CM1_ABE_MCBSP1_CLKCTRL, 0, 32, 0x08000002);
578 sr32(CM1_ABE_MCBSP2_CLKCTRL, 0, 32, 0x08000002);
579 sr32(CM1_ABE_MCBSP3_CLKCTRL, 0, 32, 0x08000002);
580 sr32(CM1_ABE_SLIMBUS_CLKCTRL, 0, 32, 0xf02);
581 sr32(CM1_ABE_TIMER5_CLKCTRL, 0, 32, 0x2);
582 sr32(CM1_ABE_TIMER6_CLKCTRL, 0, 32, 0x2);
583 sr32(CM1_ABE_TIMER7_CLKCTRL, 0, 32, 0x2);
584 sr32(CM1_ABE_TIMER8_CLKCTRL, 0, 32, 0x2);
585 sr32(CM1_ABE_WDT3_CLKCTRL, 0, 32, 0x2);
586 /* Disable sleep transitions */
587 sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x0);
590 sr32(CM_L4PER_CLKSTCTRL, 0, 32, 0x2);
591 sr32(CM_L4PER_DMTIMER10_CLKCTRL, 0, 32, 0x2);
592 wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER10_CLKCTRL, LDELAY);
593 sr32(CM_L4PER_DMTIMER11_CLKCTRL, 0, 32, 0x2);
594 wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER11_CLKCTRL, LDELAY);
595 sr32(CM_L4PER_DMTIMER2_CLKCTRL, 0, 32, 0x2);
596 wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER2_CLKCTRL, LDELAY);
597 sr32(CM_L4PER_DMTIMER3_CLKCTRL, 0, 32, 0x2);
598 wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER3_CLKCTRL, LDELAY);
599 sr32(CM_L4PER_DMTIMER4_CLKCTRL, 0, 32, 0x2);
600 wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER4_CLKCTRL, LDELAY);
601 sr32(CM_L4PER_DMTIMER9_CLKCTRL, 0, 32, 0x2);
602 wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER9_CLKCTRL, LDELAY);
605 sr32(CM_L4PER_GPIO2_CLKCTRL, 0, 32, 0x1);
606 wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO2_CLKCTRL, LDELAY);
607 sr32(CM_L4PER_GPIO3_CLKCTRL, 0, 32, 0x1);
608 wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO3_CLKCTRL, LDELAY);
609 sr32(CM_L4PER_GPIO4_CLKCTRL, 0, 32, 0x1);
610 wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO4_CLKCTRL, LDELAY);
611 sr32(CM_L4PER_GPIO5_CLKCTRL, 0, 32, 0x1);
612 wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO5_CLKCTRL, LDELAY);
613 sr32(CM_L4PER_GPIO6_CLKCTRL, 0, 32, 0x1);
614 wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO6_CLKCTRL, LDELAY);
616 sr32(CM_L4PER_HDQ1W_CLKCTRL, 0, 32, 0x2);
619 sr32(CM_L4PER_I2C1_CLKCTRL, 0, 32, 0x2);
620 wait_on_value(BIT17|BIT16, 0, CM_L4PER_I2C1_CLKCTRL, LDELAY);
621 sr32(CM_L4PER_I2C2_CLKCTRL, 0, 32, 0x2);
622 wait_on_value(BIT17|BIT16, 0, CM_L4PER_I2C2_CLKCTRL, LDELAY);
623 sr32(CM_L4PER_I2C3_CLKCTRL, 0, 32, 0x2);
624 wait_on_value(BIT17|BIT16, 0, CM_L4PER_I2C3_CLKCTRL, LDELAY);
625 sr32(CM_L4PER_I2C4_CLKCTRL, 0, 32, 0x2);
626 wait_on_value(BIT17|BIT16, 0, CM_L4PER_I2C4_CLKCTRL, LDELAY);
628 sr32(CM_L4PER_MCBSP4_CLKCTRL, 0, 32, 0x2);
629 wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCBSP4_CLKCTRL, LDELAY);
632 sr32(CM_L4PER_MCSPI1_CLKCTRL, 0, 32, 0x2);
633 wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI1_CLKCTRL, LDELAY);
634 sr32(CM_L4PER_MCSPI2_CLKCTRL, 0, 32, 0x2);
635 wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI2_CLKCTRL, LDELAY);
636 sr32(CM_L4PER_MCSPI3_CLKCTRL, 0, 32, 0x2);
637 wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI3_CLKCTRL, LDELAY);
638 sr32(CM_L4PER_MCSPI4_CLKCTRL, 0, 32, 0x2);
639 wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI4_CLKCTRL, LDELAY);
642 sr32(CM_L3INIT_HSMMC1_CLKCTRL, 0, 2, 0x2);
643 sr32(CM_L3INIT_HSMMC1_CLKCTRL, 24, 1, 0x1);
644 sr32(CM_L3INIT_HSMMC2_CLKCTRL, 0, 2, 0x2);
645 sr32(CM_L3INIT_HSMMC2_CLKCTRL, 24, 1, 0x1);
646 sr32(CM_L4PER_MMCSD3_CLKCTRL, 0, 32, 0x2);
647 wait_on_value(BIT18|BIT17|BIT16, 0, CM_L4PER_MMCSD3_CLKCTRL, LDELAY);
648 sr32(CM_L4PER_MMCSD4_CLKCTRL, 0, 32, 0x2);
649 wait_on_value(BIT18|BIT17|BIT16, 0, CM_L4PER_MMCSD4_CLKCTRL, LDELAY);
650 sr32(CM_L4PER_MMCSD5_CLKCTRL, 0, 32, 0x2);
651 wait_on_value(BIT17|BIT16, 0, CM_L4PER_MMCSD5_CLKCTRL, LDELAY);
654 sr32(CM_L4PER_UART1_CLKCTRL, 0, 32, 0x2);
655 wait_on_value(BIT17|BIT16, 0, CM_L4PER_UART1_CLKCTRL, LDELAY);
656 sr32(CM_L4PER_UART2_CLKCTRL, 0, 32, 0x2);
657 wait_on_value(BIT17|BIT16, 0, CM_L4PER_UART2_CLKCTRL, LDELAY);
658 sr32(CM_L4PER_UART3_CLKCTRL, 0, 32, 0x2);
659 wait_on_value(BIT17|BIT16, 0, CM_L4PER_UART3_CLKCTRL, LDELAY);
660 sr32(CM_L4PER_UART4_CLKCTRL, 0, 32, 0x2);
661 wait_on_value(BIT17|BIT16, 0, CM_L4PER_UART4_CLKCTRL, LDELAY);
664 sr32(CM_WKUP_GPIO1_CLKCTRL, 0, 32, 0x1);
665 wait_on_value(BIT17|BIT16, 0, CM_WKUP_GPIO1_CLKCTRL, LDELAY);
666 sr32(CM_WKUP_TIMER1_CLKCTRL, 0, 32, 0x01000002);
667 wait_on_value(BIT17|BIT16, 0, CM_WKUP_TIMER1_CLKCTRL, LDELAY);
669 sr32(CM_WKUP_KEYBOARD_CLKCTRL, 0, 32, 0x2);
670 wait_on_value(BIT17|BIT16, 0, CM_WKUP_KEYBOARD_CLKCTRL, LDELAY);
672 sr32(CM_SDMA_CLKSTCTRL, 0, 32, 0x0);
673 sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x3);
674 sr32(CM_MEMIF_EMIF_1_CLKCTRL, 0, 32, 0x1);
675 wait_on_value(BIT17|BIT16, 0, CM_MEMIF_EMIF_1_CLKCTRL, LDELAY);
676 sr32(CM_MEMIF_EMIF_2_CLKCTRL, 0, 32, 0x1);
677 wait_on_value(BIT17|BIT16, 0, CM_MEMIF_EMIF_2_CLKCTRL, LDELAY);
678 sr32(CM_D2D_CLKSTCTRL, 0, 32, 0x3);
679 sr32(CM_L3_2_GPMC_CLKCTRL, 0, 32, 0x1);
680 wait_on_value(BIT17|BIT16, 0, CM_L3_2_GPMC_CLKCTRL, LDELAY);
681 sr32(CM_L3INSTR_L3_3_CLKCTRL, 0, 32, 0x1);
682 wait_on_value(BIT17|BIT16, 0, CM_L3INSTR_L3_3_CLKCTRL, LDELAY);
683 sr32(CM_L3INSTR_L3_INSTR_CLKCTRL, 0, 32, 0x1);
684 wait_on_value(BIT17|BIT16, 0, CM_L3INSTR_L3_INSTR_CLKCTRL, LDELAY);
685 sr32(CM_L3INSTR_OCP_WP1_CLKCTRL, 0, 32, 0x1);
686 wait_on_value(BIT17|BIT16, 0, CM_L3INSTR_OCP_WP1_CLKCTRL, LDELAY);
689 sr32(CM_WKUP_WDT2_CLKCTRL, 0, 32, 0x2);
690 wait_on_value(BIT17|BIT16, 0, CM_WKUP_WDT2_CLKCTRL, LDELAY);
692 /* Enable Camera clocks */
693 sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x3);
694 sr32(CM_CAM_ISS_CLKCTRL, 0, 32, 0x102);
695 sr32(CM_CAM_FDIF_CLKCTRL, 0, 32, 0x2);
696 sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x0);
698 /* Enable DSS clocks */
699 /* PM_DSS_PWRSTCTRL ON State and LogicState = 1 (Retention) */
700 __raw_writel(7, 0x4A307100); /* DSS_PRM */
702 sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x2);
703 sr32(CM_DSS_DSS_CLKCTRL, 0, 32, 0xf02);
704 sr32(CM_DSS_DEISS_CLKCTRL, 0, 32, 0x2);
706 /* Check for DSS Clocks */
707 while ((__raw_readl(0x4A009100) & 0xF00) != 0xE00)
709 /* Set HW_AUTO transition mode */
710 sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x3);
712 /* Enable SGX clocks */
713 sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x2);
714 sr32(CM_SGX_SGX_CLKCTRL, 0, 32, 0x2);
715 /* Select DPLL PER CLOCK as source for SGX FCLK */
716 sr32(CM_SGX_SGX_CLKCTRL, 24, 1, 0x1);
717 /* Check for SGX FCLK and ICLK */
718 while (__raw_readl(0x4A009200) != 0x302)
720 /* Enable hsi/unipro/usb clocks */
721 sr32(CM_L3INIT_HSI_CLKCTRL, 0, 32, 0x1);
722 sr32(CM_L3INIT_UNIPRO1_CLKCTRL, 0, 32, 0x2);
723 sr32(CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, 0x2);
724 sr32(CM_L3INIT_HSUSBOTG_CLKCTRL, 0, 32, 0x1);
725 sr32(CM_L3INIT_HSUSBTLL_CLKCTRL, 0, 32, 0x1);
726 sr32(CM_L3INIT_FSUSB_CLKCTRL, 0, 32, 0x2);
727 /* enable the 32K, 48M optional clocks and enable the module */
728 sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x301);
731 /******************************************************************************
732 * prcm_init() - inits clocks for PRCM as defined in clocks.h
733 * -- called from SRAM, or Flash (using temp SRAM stack).
734 *****************************************************************************/
739 /* Get the sysclk speed from cm_sys_clksel
740 * Set the CM_SYS_CLKSEL in case ROM code has not set
742 __raw_writel(0x7, CM_SYS_CLKSEL);
743 clk_index = readl(CM_SYS_CLKSEL);
745 return; /* Sys clk uninitialized */
746 /* Core DPLL is locked using FREQ update method */
747 /* configure_core_dpll(clk_index - 1); */
749 /* Configure all DPLL's at 100% OPP */
750 configure_mpu_dpll(clk_index - 1);
751 configure_iva_dpll(clk_index - 1);
752 configure_per_dpll(clk_index - 1);
753 configure_abe_dpll(clk_index - 1);
754 configure_usb_dpll(clk_index - 1);
756 #ifdef CONFIG_OMAP4_SDC
757 /* Enable all clocks */