2 * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port
4 * Copyright (C) 2008 Nokia Corporation
6 * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
7 * Peter Ujfalusi <peter.ujfalusi@ti.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/device.h>
28 #include <sound/core.h>
29 #include <sound/pcm.h>
30 #include <sound/pcm_params.h>
31 #include <sound/initval.h>
32 #include <sound/soc.h>
35 #include <plat/mcbsp.h>
36 #include "omap-mcbsp.h"
39 #define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000)
41 #define OMAP_MCBSP_SOC_SINGLE_S16_EXT(xname, xmin, xmax, \
42 xhandler_get, xhandler_put) \
43 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
44 .info = omap_mcbsp_st_info_volsw, \
45 .get = xhandler_get, .put = xhandler_put, \
46 .private_value = (unsigned long) &(struct soc_mixer_control) \
47 {.min = xmin, .max = xmax} }
49 struct omap_mcbsp_data {
51 struct omap_mcbsp_reg_cfg regs;
54 * Flags indicating is the bus already activated and configured by
64 static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
67 * Stream DMA parameters. DMA request line and port address are set runtime
68 * since they are different between OMAP1 and later OMAPs
70 static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];
72 static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream)
74 struct snd_soc_pcm_runtime *rtd = substream->private_data;
75 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
76 struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
77 struct omap_pcm_dma_data *dma_data;
78 int dma_op_mode = omap_mcbsp_get_dma_op_mode(mcbsp_data->bus_id);
81 dma_data = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
83 /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
84 if (dma_op_mode == MCBSP_DMA_MODE_THRESHOLD)
86 * Configure McBSP threshold based on either:
87 * packet_size, when the sDMA is in packet mode, or
88 * based on the period size.
90 if (dma_data->packet_size)
91 words = dma_data->packet_size;
93 words = snd_pcm_lib_period_bytes(substream) /
94 (mcbsp_data->wlen / 8);
98 /* Configure McBSP internal buffer usage */
99 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
100 omap_mcbsp_set_tx_threshold(mcbsp_data->bus_id, words);
102 omap_mcbsp_set_rx_threshold(mcbsp_data->bus_id, words);
105 static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params,
106 struct snd_pcm_hw_rule *rule)
108 struct snd_interval *buffer_size = hw_param_interval(params,
109 SNDRV_PCM_HW_PARAM_BUFFER_SIZE);
110 struct snd_interval *channels = hw_param_interval(params,
111 SNDRV_PCM_HW_PARAM_CHANNELS);
112 struct omap_mcbsp_data *mcbsp_data = rule->private;
113 struct snd_interval frames;
116 snd_interval_any(&frames);
117 size = omap_mcbsp_get_fifo_size(mcbsp_data->bus_id);
119 frames.min = size / channels->min;
121 return snd_interval_refine(buffer_size, &frames);
124 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
125 struct snd_soc_dai *cpu_dai)
127 struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
128 int bus_id = mcbsp_data->bus_id;
131 if (!cpu_dai->active)
132 err = omap_mcbsp_request(bus_id);
135 * OMAP3 McBSP FIFO is word structured.
136 * McBSP2 has 1024 + 256 = 1280 word long buffer,
137 * McBSP1,3,4,5 has 128 word long buffer
138 * This means that the size of the FIFO depends on the sample format.
139 * For example on McBSP3:
140 * 16bit samples: size is 128 * 2 = 256 bytes
141 * 32bit samples: size is 128 * 4 = 512 bytes
142 * It is simpler to place constraint for buffer and period based on
144 * McBSP3 as example again (16 or 32 bit samples):
145 * 1 channel (mono): size is 128 frames (128 words)
146 * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words)
147 * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words)
149 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
151 * Rule for the buffer size. We should not allow
152 * smaller buffer than the FIFO size to avoid underruns
154 snd_pcm_hw_rule_add(substream->runtime, 0,
155 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
156 omap_mcbsp_hwrule_min_buffersize,
158 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
160 /* Make sure, that the period size is always even */
161 snd_pcm_hw_constraint_step(substream->runtime, 0,
162 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
168 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
169 struct snd_soc_dai *cpu_dai)
171 struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
173 if (!cpu_dai->active) {
174 omap_mcbsp_free(mcbsp_data->bus_id);
175 mcbsp_data->configured = 0;
179 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
180 struct snd_soc_dai *cpu_dai)
182 struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
183 int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
186 case SNDRV_PCM_TRIGGER_START:
187 case SNDRV_PCM_TRIGGER_RESUME:
188 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
189 mcbsp_data->active++;
190 omap_mcbsp_start(mcbsp_data->bus_id, play, !play);
193 case SNDRV_PCM_TRIGGER_STOP:
194 case SNDRV_PCM_TRIGGER_SUSPEND:
195 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
196 omap_mcbsp_stop(mcbsp_data->bus_id, play, !play);
197 mcbsp_data->active--;
206 static snd_pcm_sframes_t omap_mcbsp_dai_delay(
207 struct snd_pcm_substream *substream,
208 struct snd_soc_dai *dai)
210 struct snd_soc_pcm_runtime *rtd = substream->private_data;
211 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
212 struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
214 snd_pcm_sframes_t delay;
216 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
217 fifo_use = omap_mcbsp_get_tx_delay(mcbsp_data->bus_id);
219 fifo_use = omap_mcbsp_get_rx_delay(mcbsp_data->bus_id);
222 * Divide the used locations with the channel count to get the
223 * FIFO usage in samples (don't care about partial samples in the
226 delay = fifo_use / substream->runtime->channels;
231 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
232 struct snd_pcm_hw_params *params,
233 struct snd_soc_dai *cpu_dai)
235 struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
236 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
237 struct omap_pcm_dma_data *dma_data;
238 int dma, bus_id = mcbsp_data->bus_id;
239 int wlen, channels, wpf, sync_mode = OMAP_DMA_SYNC_ELEMENT;
242 unsigned int format, div, framesize, master;
244 dma_data = &omap_mcbsp_dai_dma_params[cpu_dai->id][substream->stream];
246 dma = omap_mcbsp_dma_ch_params(bus_id, substream->stream);
247 port = omap_mcbsp_dma_reg_params(bus_id, substream->stream);
249 switch (params_format(params)) {
250 case SNDRV_PCM_FORMAT_S16_LE:
251 dma_data->data_type = OMAP_DMA_DATA_TYPE_S16;
254 case SNDRV_PCM_FORMAT_S32_LE:
255 dma_data->data_type = OMAP_DMA_DATA_TYPE_S32;
261 if (cpu_is_omap34xx()) {
262 dma_data->set_threshold = omap_mcbsp_set_threshold;
263 /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
264 if (omap_mcbsp_get_dma_op_mode(bus_id) ==
265 MCBSP_DMA_MODE_THRESHOLD) {
266 int period_words, max_thrsh;
268 period_words = params_period_bytes(params) / (wlen / 8);
269 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
270 max_thrsh = omap_mcbsp_get_max_tx_threshold(
273 max_thrsh = omap_mcbsp_get_max_rx_threshold(
276 * If the period contains less or equal number of words,
277 * we are using the original threshold mode setup:
278 * McBSP threshold = sDMA frame size = period_size
279 * Otherwise we switch to sDMA packet mode:
280 * McBSP threshold = sDMA packet size
281 * sDMA frame size = period size
283 if (period_words > max_thrsh) {
287 * Look for the biggest threshold value, which
288 * divides the period size evenly.
290 divider = period_words / max_thrsh;
291 if (period_words % max_thrsh)
293 while (period_words % divider &&
294 divider < period_words)
296 if (divider == period_words)
299 pkt_size = period_words / divider;
300 sync_mode = OMAP_DMA_SYNC_PACKET;
302 sync_mode = OMAP_DMA_SYNC_FRAME;
307 dma_data->name = substream->stream ? "Audio Capture" : "Audio Playback";
308 dma_data->dma_req = dma;
309 dma_data->port_addr = port;
310 dma_data->sync_mode = sync_mode;
311 dma_data->packet_size = pkt_size;
313 snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
316 if (mcbsp_data->configured) {
317 /* McBSP already configured by another stream */
322 regs->rcr2 &= ~(RPHASE | RFRLEN2(0x7f) | RWDLEN2(7));
323 regs->xcr2 &= ~(RPHASE | XFRLEN2(0x7f) | XWDLEN2(7));
324 regs->rcr1 &= ~(RFRLEN1(0x7f) | RWDLEN1(7));
325 regs->xcr1 &= ~(XFRLEN1(0x7f) | XWDLEN1(7));
326 format = mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
327 wpf = channels = params_channels(params);
328 if (channels == 2 && (format == SND_SOC_DAIFMT_I2S ||
329 format == SND_SOC_DAIFMT_LEFT_J)) {
330 /* Use dual-phase frames */
331 regs->rcr2 |= RPHASE;
332 regs->xcr2 |= XPHASE;
333 /* Set 1 word per (McBSP) frame for phase1 and phase2 */
335 regs->rcr2 |= RFRLEN2(wpf - 1);
336 regs->xcr2 |= XFRLEN2(wpf - 1);
339 regs->rcr1 |= RFRLEN1(wpf - 1);
340 regs->xcr1 |= XFRLEN1(wpf - 1);
342 switch (params_format(params)) {
343 case SNDRV_PCM_FORMAT_S16_LE:
344 /* Set word lengths */
345 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16);
346 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16);
347 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_16);
348 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16);
350 case SNDRV_PCM_FORMAT_S32_LE:
351 /* Set word lengths */
352 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_32);
353 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_32);
354 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_32);
355 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_32);
358 /* Unsupported PCM format */
362 /* In McBSP master modes, FRAME (i.e. sample rate) is generated
363 * by _counting_ BCLKs. Calculate frame size in BCLKs */
364 master = mcbsp_data->fmt & SND_SOC_DAIFMT_MASTER_MASK;
365 if (master == SND_SOC_DAIFMT_CBS_CFS) {
366 div = mcbsp_data->clk_div ? mcbsp_data->clk_div : 1;
367 framesize = (mcbsp_data->in_freq / div) / params_rate(params);
369 if (framesize < wlen * channels) {
370 printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
371 "channels\n", __func__);
375 framesize = wlen * channels;
377 /* Set FS period and length in terms of bit clock periods */
378 regs->srgr2 &= ~FPER(0xfff);
379 regs->srgr1 &= ~FWID(0xff);
381 case SND_SOC_DAIFMT_I2S:
382 case SND_SOC_DAIFMT_LEFT_J:
383 regs->srgr2 |= FPER(framesize - 1);
384 regs->srgr1 |= FWID((framesize >> 1) - 1);
386 case SND_SOC_DAIFMT_DSP_A:
387 case SND_SOC_DAIFMT_DSP_B:
388 regs->srgr2 |= FPER(framesize - 1);
389 regs->srgr1 |= FWID(0);
393 omap_mcbsp_config(bus_id, &mcbsp_data->regs);
394 mcbsp_data->wlen = wlen;
395 mcbsp_data->configured = 1;
401 * This must be called before _set_clkdiv and _set_sysclk since McBSP register
402 * cache is initialized here
404 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
407 struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
408 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
411 if (mcbsp_data->configured)
414 mcbsp_data->fmt = fmt;
415 memset(regs, 0, sizeof(*regs));
416 /* Generic McBSP register settings */
417 regs->spcr2 |= XINTM(3) | FREE;
418 regs->spcr1 |= RINTM(3);
419 /* RFIG and XFIG are not defined in 34xx */
420 if (!cpu_is_omap34xx() && !cpu_is_omap44xx()) {
424 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
425 regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
426 regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
429 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
430 case SND_SOC_DAIFMT_I2S:
431 /* 1-bit data delay */
432 regs->rcr2 |= RDATDLY(1);
433 regs->xcr2 |= XDATDLY(1);
435 case SND_SOC_DAIFMT_LEFT_J:
436 /* 0-bit data delay */
437 regs->rcr2 |= RDATDLY(0);
438 regs->xcr2 |= XDATDLY(0);
439 regs->spcr1 |= RJUST(2);
440 /* Invert FS polarity configuration */
443 case SND_SOC_DAIFMT_DSP_A:
444 /* 1-bit data delay */
445 regs->rcr2 |= RDATDLY(1);
446 regs->xcr2 |= XDATDLY(1);
447 /* Invert FS polarity configuration */
450 case SND_SOC_DAIFMT_DSP_B:
451 /* 0-bit data delay */
452 regs->rcr2 |= RDATDLY(0);
453 regs->xcr2 |= XDATDLY(0);
454 /* Invert FS polarity configuration */
458 /* Unsupported data format */
462 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
463 case SND_SOC_DAIFMT_CBS_CFS:
464 /* McBSP master. Set FS and bit clocks as outputs */
465 regs->pcr0 |= FSXM | FSRM |
467 /* Sample rate generator drives the FS */
470 case SND_SOC_DAIFMT_CBM_CFM:
474 /* Unsupported master/slave configuration */
478 /* Set bit clock (CLKX/CLKR) and FS polarities */
479 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
480 case SND_SOC_DAIFMT_NB_NF:
483 * FS active low. TX data driven on falling edge of bit clock
484 * and RX data sampled on rising edge of bit clock.
486 regs->pcr0 |= FSXP | FSRP |
489 case SND_SOC_DAIFMT_NB_IF:
490 regs->pcr0 |= CLKXP | CLKRP;
492 case SND_SOC_DAIFMT_IB_NF:
493 regs->pcr0 |= FSXP | FSRP;
495 case SND_SOC_DAIFMT_IB_IF:
501 regs->pcr0 ^= FSXP | FSRP;
506 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
509 struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
510 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
512 if (div_id != OMAP_MCBSP_CLKGDV)
515 mcbsp_data->clk_div = div;
516 regs->srgr1 &= ~CLKGDV(0xff);
517 regs->srgr1 |= CLKGDV(div - 1);
522 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
523 int clk_id, unsigned int freq,
526 struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
527 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
530 if (mcbsp_data->active) {
531 if (freq == mcbsp_data->in_freq)
537 /* The McBSP signal muxing functions are only available on McBSP1 */
538 if (clk_id == OMAP_MCBSP_CLKR_SRC_CLKR ||
539 clk_id == OMAP_MCBSP_CLKR_SRC_CLKX ||
540 clk_id == OMAP_MCBSP_FSR_SRC_FSR ||
541 clk_id == OMAP_MCBSP_FSR_SRC_FSX)
542 if (cpu_class_is_omap1() || mcbsp_data->bus_id != 0)
545 mcbsp_data->in_freq = freq;
546 regs->srgr2 &= ~CLKSM;
547 regs->pcr0 &= ~SCLKME;
550 case OMAP_MCBSP_SYSCLK_CLK:
551 regs->srgr2 |= CLKSM;
553 case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
554 if (cpu_class_is_omap1()) {
558 err = omap2_mcbsp_set_clks_src(mcbsp_data->bus_id,
559 MCBSP_CLKS_PRCM_SRC);
561 case OMAP_MCBSP_SYSCLK_CLKS_EXT:
562 if (cpu_class_is_omap1()) {
566 err = omap2_mcbsp_set_clks_src(mcbsp_data->bus_id,
570 case OMAP_MCBSP_SYSCLK_CLKX_EXT:
571 regs->srgr2 |= CLKSM;
572 case OMAP_MCBSP_SYSCLK_CLKR_EXT:
573 regs->pcr0 |= SCLKME;
577 case OMAP_MCBSP_CLKR_SRC_CLKR:
578 if (cpu_class_is_omap1())
580 omap2_mcbsp1_mux_clkr_src(CLKR_SRC_CLKR);
582 case OMAP_MCBSP_CLKR_SRC_CLKX:
583 if (cpu_class_is_omap1())
585 omap2_mcbsp1_mux_clkr_src(CLKR_SRC_CLKX);
587 case OMAP_MCBSP_FSR_SRC_FSR:
588 if (cpu_class_is_omap1())
590 omap2_mcbsp1_mux_fsr_src(FSR_SRC_FSR);
592 case OMAP_MCBSP_FSR_SRC_FSX:
593 if (cpu_class_is_omap1())
595 omap2_mcbsp1_mux_fsr_src(FSR_SRC_FSX);
604 static struct snd_soc_dai_ops mcbsp_dai_ops = {
605 .startup = omap_mcbsp_dai_startup,
606 .shutdown = omap_mcbsp_dai_shutdown,
607 .trigger = omap_mcbsp_dai_trigger,
608 .delay = omap_mcbsp_dai_delay,
609 .hw_params = omap_mcbsp_dai_hw_params,
610 .set_fmt = omap_mcbsp_dai_set_dai_fmt,
611 .set_clkdiv = omap_mcbsp_dai_set_clkdiv,
612 .set_sysclk = omap_mcbsp_dai_set_dai_sysclk,
615 static int mcbsp_dai_probe(struct snd_soc_dai *dai)
617 mcbsp_data[dai->id].bus_id = dai->id;
618 snd_soc_dai_set_drvdata(dai, &mcbsp_data[dai->id].bus_id);
622 static struct snd_soc_dai_driver omap_mcbsp_dai = {
623 .probe = mcbsp_dai_probe,
627 .rates = OMAP_MCBSP_RATES,
628 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
633 .rates = OMAP_MCBSP_RATES,
634 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
636 .ops = &mcbsp_dai_ops,
639 static int omap_mcbsp_st_info_volsw(struct snd_kcontrol *kcontrol,
640 struct snd_ctl_elem_info *uinfo)
642 struct soc_mixer_control *mc =
643 (struct soc_mixer_control *)kcontrol->private_value;
647 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
649 uinfo->value.integer.min = min;
650 uinfo->value.integer.max = max;
654 #define OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(id, channel) \
656 omap_mcbsp##id##_set_st_ch##channel##_volume(struct snd_kcontrol *kc, \
657 struct snd_ctl_elem_value *uc) \
659 struct soc_mixer_control *mc = \
660 (struct soc_mixer_control *)kc->private_value; \
663 int val = uc->value.integer.value[0]; \
665 if (val < min || val > max) \
668 /* OMAP McBSP implementation uses index values 0..4 */ \
669 return omap_st_set_chgain((id)-1, channel, val); \
672 #define OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(id, channel) \
674 omap_mcbsp##id##_get_st_ch##channel##_volume(struct snd_kcontrol *kc, \
675 struct snd_ctl_elem_value *uc) \
679 if (omap_st_get_chgain((id)-1, channel, &chgain)) \
682 uc->value.integer.value[0] = chgain; \
686 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 0)
687 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 1)
688 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 0)
689 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 1)
690 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 0)
691 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 1)
692 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 0)
693 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 1)
695 static int omap_mcbsp_st_put_mode(struct snd_kcontrol *kcontrol,
696 struct snd_ctl_elem_value *ucontrol)
698 struct soc_mixer_control *mc =
699 (struct soc_mixer_control *)kcontrol->private_value;
700 u8 value = ucontrol->value.integer.value[0];
702 if (value == omap_st_is_enabled(mc->reg))
706 omap_st_enable(mc->reg);
708 omap_st_disable(mc->reg);
713 static int omap_mcbsp_st_get_mode(struct snd_kcontrol *kcontrol,
714 struct snd_ctl_elem_value *ucontrol)
716 struct soc_mixer_control *mc =
717 (struct soc_mixer_control *)kcontrol->private_value;
719 ucontrol->value.integer.value[0] = omap_st_is_enabled(mc->reg);
723 static const struct snd_kcontrol_new omap_mcbsp2_st_controls[] = {
724 SOC_SINGLE_EXT("McBSP2 Sidetone Switch", 1, 0, 1, 0,
725 omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
726 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 0 Volume",
728 omap_mcbsp2_get_st_ch0_volume,
729 omap_mcbsp2_set_st_ch0_volume),
730 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 1 Volume",
732 omap_mcbsp2_get_st_ch1_volume,
733 omap_mcbsp2_set_st_ch1_volume),
736 static const struct snd_kcontrol_new omap_mcbsp3_st_controls[] = {
737 SOC_SINGLE_EXT("McBSP3 Sidetone Switch", 2, 0, 1, 0,
738 omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
739 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 0 Volume",
741 omap_mcbsp3_get_st_ch0_volume,
742 omap_mcbsp3_set_st_ch0_volume),
743 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 1 Volume",
745 omap_mcbsp3_get_st_ch1_volume,
746 omap_mcbsp3_set_st_ch1_volume),
749 int omap_mcbsp_st_add_controls(struct snd_soc_codec *codec, int mcbsp_id)
751 if (!cpu_is_omap34xx())
755 case 1: /* McBSP 2 */
756 return snd_soc_add_controls(codec, omap_mcbsp2_st_controls,
757 ARRAY_SIZE(omap_mcbsp2_st_controls));
758 case 2: /* McBSP 3 */
759 return snd_soc_add_controls(codec, omap_mcbsp3_st_controls,
760 ARRAY_SIZE(omap_mcbsp3_st_controls));
767 EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls);
769 static __devinit int asoc_mcbsp_probe(struct platform_device *pdev)
771 return snd_soc_register_dai(&pdev->dev, &omap_mcbsp_dai);
774 static int __devexit asoc_mcbsp_remove(struct platform_device *pdev)
776 snd_soc_unregister_dai(&pdev->dev);
780 static struct platform_driver asoc_mcbsp_driver = {
782 .name = "omap-mcbsp-dai",
783 .owner = THIS_MODULE,
786 .probe = asoc_mcbsp_probe,
787 .remove = __devexit_p(asoc_mcbsp_remove),
790 static int __init snd_omap_mcbsp_init(void)
792 return platform_driver_register(&asoc_mcbsp_driver);
794 module_init(snd_omap_mcbsp_init);
796 static void __exit snd_omap_mcbsp_exit(void)
798 platform_driver_unregister(&asoc_mcbsp_driver);
800 module_exit(snd_omap_mcbsp_exit);
802 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@bitmer.com>");
803 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
804 MODULE_LICENSE("GPL");