drivers/usb/musb/tusb6010_omap.c

   1 /*
   2  * TUSB6010 USB 2.0 OTG Dual Role controller OMAP DMA interface
   3  *
   4  * Copyright (C) 2006 Nokia Corporation
   5  * Tony Lindgren <tony@atomide.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11 #include <linux/module.h>
  12 #include <linux/kernel.h>
  13 #include <linux/errno.h>
  14 #include <linux/init.h>
  15 #include <linux/usb.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/slab.h>
  19 #include <plat/dma.h>
  20 #include <plat/mux.h>
  21
  22 #include "musb_core.h"
  23 #include "tusb6010.h"
  24
  25 #define to_chdat(c)             ((struct tusb_omap_dma_ch *)(c)->private_data)
  26
  27 #define MAX_DMAREQ              5       /* REVISIT: Really 6, but req5 not OK */
  28
  29 struct tusb_omap_dma_ch {
  30         struct musb             *musb;
  31         void __iomem            *tbase;
  32         unsigned long           phys_offset;
  33         int                     epnum;
  34         u8                      tx;
  35         struct musb_hw_ep       *hw_ep;
  36
  37         int                     ch;
  38         s8                      dmareq;
  39         s8                      sync_dev;
  40
  41         struct tusb_omap_dma    *tusb_dma;
  42
  43         dma_addr_t              dma_addr;
  44
  45         u32                     len;
  46         u16                     packet_sz;
  47         u16                     transfer_packet_sz;
  48         u32                     transfer_len;
  49         u32                     completed_len;
  50 };
  51
  52 struct tusb_omap_dma {
  53         struct dma_controller           controller;
  54         struct musb                     *musb;
  55         void __iomem                    *tbase;
  56
  57         int                             ch;
  58         s8                              dmareq;
  59         s8                              sync_dev;
  60         unsigned                        multichannel:1;
  61 };
  62
  63 static int tusb_omap_dma_start(struct dma_controller *c)
  64 {
  65         struct tusb_omap_dma    *tusb_dma;
  66
  67         tusb_dma = container_of(c, struct tusb_omap_dma, controller);
  68
  69         /* dev_dbg(musb->controller, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */
  70
  71         return 0;
  72 }
  73
  74 static int tusb_omap_dma_stop(struct dma_controller *c)
  75 {
  76         struct tusb_omap_dma    *tusb_dma;
  77
  78         tusb_dma = container_of(c, struct tusb_omap_dma, controller);
  79
  80         /* dev_dbg(musb->controller, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */
  81
  82         return 0;
  83 }
  84
  85 /*
  86  * Allocate dmareq0 to the current channel unless it's already taken
  87  */
  88 static inline int tusb_omap_use_shared_dmareq(struct tusb_omap_dma_ch *chdat)
  89 {
  90         u32             reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
  91
  92         if (reg != 0) {
  93                 dev_dbg(chdat->musb->controller, "ep%i dmareq0 is busy for ep%i\n",
  94                         chdat->epnum, reg & 0xf);
  95                 return -EAGAIN;
  96         }
  97
  98         if (chdat->tx)
  99                 reg = (1 << 4) | chdat->epnum;
 100         else
 101                 reg = chdat->epnum;
 102
 103         musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg);
 104
 105         return 0;
 106 }
 107
 108 static inline void tusb_omap_free_shared_dmareq(struct tusb_omap_dma_ch *chdat)
 109 {
 110         u32             reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
 111
 112         if ((reg & 0xf) != chdat->epnum) {
 113                 printk(KERN_ERR "ep%i trying to release dmareq0 for ep%i\n",
 114                         chdat->epnum, reg & 0xf);
 115                 return;
 116         }
 117         musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, 0);
 118 }
 119
 120 /*
 121  * See also musb_dma_completion in plat_uds.c and musb_g_[tx|rx]() in
 122  * musb_gadget.c.
 123  */
 124 static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data)
 125 {
 126         struct dma_channel      *channel = (struct dma_channel *)data;
 127         struct tusb_omap_dma_ch *chdat = to_chdat(channel);
 128         struct tusb_omap_dma    *tusb_dma = chdat->tusb_dma;
 129         struct musb             *musb = chdat->musb;
 130         struct device           *dev = musb->controller;
 131         struct musb_hw_ep       *hw_ep = chdat->hw_ep;
 132         void __iomem            *ep_conf = hw_ep->conf;
 133         void __iomem            *mbase = musb->mregs;
 134         unsigned long           remaining, flags, pio;
 135         int                     ch;
 136
 137         spin_lock_irqsave(&musb->lock, flags);
 138
 139         if (tusb_dma->multichannel)
 140                 ch = chdat->ch;
 141         else
 142                 ch = tusb_dma->ch;
 143
 144         if (ch_status != OMAP_DMA_BLOCK_IRQ)
 145                 printk(KERN_ERR "TUSB DMA error status: %i\n", ch_status);
 146
 147         dev_dbg(musb->controller, "ep%i %s dma callback ch: %i status: %x\n",
 148                 chdat->epnum, chdat->tx ? "tx" : "rx",
 149                 ch, ch_status);
 150
 151         if (chdat->tx)
 152                 remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET);
 153         else
 154                 remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET);
 155
 156         remaining = TUSB_EP_CONFIG_XFR_SIZE(remaining);
 157
 158         /* HW issue #10: XFR_SIZE may get corrupt on DMA (both async & sync) */
 159         if (unlikely(remaining > chdat->transfer_len)) {
 160                 dev_dbg(musb->controller, "Corrupt %s dma ch%i XFR_SIZE: 0x%08lx\n",
 161                         chdat->tx ? "tx" : "rx", chdat->ch,
 162                         remaining);
 163                 remaining = 0;
 164         }
 165
 166         channel->actual_len = chdat->transfer_len - remaining;
 167         pio = chdat->len - channel->actual_len;
 168
 169         dev_dbg(musb->controller, "DMA remaining %lu/%u\n", remaining, chdat->transfer_len);
 170
 171         /* Transfer remaining 1 - 31 bytes */
 172         if (pio > 0 && pio < 32) {
 173                 u8      *buf;
 174
 175                 dev_dbg(musb->controller, "Using PIO for remaining %lu bytes\n", pio);
 176                 buf = phys_to_virt((u32)chdat->dma_addr) + chdat->transfer_len;
 177                 if (chdat->tx) {
 178                         dma_unmap_single(dev, chdat->dma_addr,
 179                                                 chdat->transfer_len,
 180                                                 DMA_TO_DEVICE);
 181                         musb_write_fifo(hw_ep, pio, buf);
 182                 } else {
 183                         dma_unmap_single(dev, chdat->dma_addr,
 184                                                 chdat->transfer_len,
 185                                                 DMA_FROM_DEVICE);
 186                         musb_read_fifo(hw_ep, pio, buf);
 187                 }
 188                 channel->actual_len += pio;
 189         }
 190
 191         if (!tusb_dma->multichannel)
 192                 tusb_omap_free_shared_dmareq(chdat);
 193
 194         channel->status = MUSB_DMA_STATUS_FREE;
 195
 196         /* Handle only RX callbacks here. TX callbacks must be handled based
 197          * on the TUSB DMA status interrupt.
 198          * REVISIT: Use both TUSB DMA status interrupt and OMAP DMA callback
 199          * interrupt for RX and TX.
 200          */
 201         if (!chdat->tx)
 202                 musb_dma_completion(musb, chdat->epnum, chdat->tx);
 203
 204         /* We must terminate short tx transfers manually by setting TXPKTRDY.
 205          * REVISIT: This same problem may occur with other MUSB dma as well.
 206          * Easy to test with g_ether by pinging the MUSB board with ping -s54.
 207          */
 208         if ((chdat->transfer_len < chdat->packet_sz)
 209                         || (chdat->transfer_len % chdat->packet_sz != 0)) {
 210                 u16     csr;
 211
 212                 if (chdat->tx) {
 213                         dev_dbg(musb->controller, "terminating short tx packet\n");
 214                         musb_ep_select(mbase, chdat->epnum);
 215                         csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
 216                         csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY
 217                                 | MUSB_TXCSR_P_WZC_BITS;
 218                         musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
 219                 }
 220         }
 221
 222         spin_unlock_irqrestore(&musb->lock, flags);
 223 }
 224
 225 static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz,
 226                                 u8 rndis_mode, dma_addr_t dma_addr, u32 len)
 227 {
 228         struct tusb_omap_dma_ch         *chdat = to_chdat(channel);
 229         struct tusb_omap_dma            *tusb_dma = chdat->tusb_dma;
 230         struct musb                     *musb = chdat->musb;
 231         struct device                   *dev = musb->controller;
 232         struct musb_hw_ep               *hw_ep = chdat->hw_ep;
 233         void __iomem                    *mbase = musb->mregs;
 234         void __iomem                    *ep_conf = hw_ep->conf;
 235         dma_addr_t                      fifo = hw_ep->fifo_sync;
 236         struct omap_dma_channel_params  dma_params;
 237         u32                             dma_remaining;
 238         int                             src_burst, dst_burst;
 239         u16                             csr;
 240         u32                             psize;
 241         int                             ch;
 242         s8                              dmareq;
 243         s8                              sync_dev;
 244
 245         if (unlikely(dma_addr & 0x1) || (len < 32) || (len > packet_sz))
 246                 return false;
 247
 248         /*
 249          * HW issue #10: Async dma will eventually corrupt the XFR_SIZE
 250          * register which will cause missed DMA interrupt. We could try to
 251          * use a timer for the callback, but it is unsafe as the XFR_SIZE
 252          * register is corrupt, and we won't know if the DMA worked.
 253          */
 254         if (dma_addr & 0x2)
 255                 return false;
 256
 257         /*
 258          * Because of HW issue #10, it seems like mixing sync DMA and async
 259          * PIO access can confuse the DMA. Make sure XFR_SIZE is reset before
 260          * using the channel for DMA.
 261          */
 262         if (chdat->tx)
 263                 dma_remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET);
 264         else
 265                 dma_remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET);
 266
 267         dma_remaining = TUSB_EP_CONFIG_XFR_SIZE(dma_remaining);
 268         if (dma_remaining) {
 269                 dev_dbg(musb->controller, "Busy %s dma ch%i, not using: %08x\n",
 270                         chdat->tx ? "tx" : "rx", chdat->ch,
 271                         dma_remaining);
 272                 return false;
 273         }
 274
 275         chdat->transfer_len = len & ~0x1f;
 276
 277         if (len < packet_sz)
 278                 chdat->transfer_packet_sz = chdat->transfer_len;
 279         else
 280                 chdat->transfer_packet_sz = packet_sz;
 281
 282         if (tusb_dma->multichannel) {
 283                 ch = chdat->ch;
 284                 dmareq = chdat->dmareq;
 285                 sync_dev = chdat->sync_dev;
 286         } else {
 287                 if (tusb_omap_use_shared_dmareq(chdat) != 0) {
 288                         dev_dbg(musb->controller, "could not get dma for ep%i\n", chdat->epnum);
 289                         return false;
 290                 }
 291                 if (tusb_dma->ch < 0) {
 292                         /* REVISIT: This should get blocked earlier, happens
 293                          * with MSC ErrorRecoveryTest
 294                          */
 295                         WARN_ON(1);
 296                         return false;
 297                 }
 298
 299                 ch = tusb_dma->ch;
 300                 dmareq = tusb_dma->dmareq;
 301                 sync_dev = tusb_dma->sync_dev;
 302                 omap_set_dma_callback(ch, tusb_omap_dma_cb, channel);
 303         }
 304
 305         chdat->packet_sz = packet_sz;
 306         chdat->len = len;
 307         channel->actual_len = 0;
 308         chdat->dma_addr = dma_addr;
 309         channel->status = MUSB_DMA_STATUS_BUSY;
 310
 311         /* Since we're recycling dma areas, we need to clean or invalidate */
 312         if (chdat->tx)
 313                 dma_map_single(dev, phys_to_virt(dma_addr), len,
 314                                 DMA_TO_DEVICE);
 315         else
 316                 dma_map_single(dev, phys_to_virt(dma_addr), len,
 317                                 DMA_FROM_DEVICE);
 318
 319         /* Use 16-bit transfer if dma_addr is not 32-bit aligned */
 320         if ((dma_addr & 0x3) == 0) {
 321                 dma_params.data_type = OMAP_DMA_DATA_TYPE_S32;
 322                 dma_params.elem_count = 8;              /* Elements in frame */
 323         } else {
 324                 dma_params.data_type = OMAP_DMA_DATA_TYPE_S16;
 325                 dma_params.elem_count = 16;             /* Elements in frame */
 326                 fifo = hw_ep->fifo_async;
 327         }
 328
 329         dma_params.frame_count  = chdat->transfer_len / 32; /* Burst sz frame */
 330
 331         dev_dbg(musb->controller, "ep%i %s dma ch%i dma: %08x len: %u(%u) packet_sz: %i(%i)\n",
 332                 chdat->epnum, chdat->tx ? "tx" : "rx",
 333                 ch, dma_addr, chdat->transfer_len, len,
 334                 chdat->transfer_packet_sz, packet_sz);
 335
 336         /*
 337          * Prepare omap DMA for transfer
 338          */
 339         if (chdat->tx) {
 340                 dma_params.src_amode    = OMAP_DMA_AMODE_POST_INC;
 341                 dma_params.src_start    = (unsigned long)dma_addr;
 342                 dma_params.src_ei       = 0;
 343                 dma_params.src_fi       = 0;
 344
 345                 dma_params.dst_amode    = OMAP_DMA_AMODE_DOUBLE_IDX;
 346                 dma_params.dst_start    = (unsigned long)fifo;
 347                 dma_params.dst_ei       = 1;
 348                 dma_params.dst_fi       = -31;  /* Loop 32 byte window */
 349
 350                 dma_params.trigger      = sync_dev;
 351                 dma_params.sync_mode    = OMAP_DMA_SYNC_FRAME;
 352                 dma_params.src_or_dst_synch     = 0;    /* Dest sync */
 353
 354                 src_burst = OMAP_DMA_DATA_BURST_16;     /* 16x32 read */
 355                 dst_burst = OMAP_DMA_DATA_BURST_8;      /* 8x32 write */
 356         } else {
 357                 dma_params.src_amode    = OMAP_DMA_AMODE_DOUBLE_IDX;
 358                 dma_params.src_start    = (unsigned long)fifo;
 359                 dma_params.src_ei       = 1;
 360                 dma_params.src_fi       = -31;  /* Loop 32 byte window */
 361
 362                 dma_params.dst_amode    = OMAP_DMA_AMODE_POST_INC;
 363                 dma_params.dst_start    = (unsigned long)dma_addr;
 364                 dma_params.dst_ei       = 0;
 365                 dma_params.dst_fi       = 0;
 366
 367                 dma_params.trigger      = sync_dev;
 368                 dma_params.sync_mode    = OMAP_DMA_SYNC_FRAME;
 369                 dma_params.src_or_dst_synch     = 1;    /* Source sync */
 370
 371                 src_burst = OMAP_DMA_DATA_BURST_8;      /* 8x32 read */
 372                 dst_burst = OMAP_DMA_DATA_BURST_16;     /* 16x32 write */
 373         }
 374
 375         dev_dbg(musb->controller, "ep%i %s using %i-bit %s dma from 0x%08lx to 0x%08lx\n",
 376                 chdat->epnum, chdat->tx ? "tx" : "rx",
 377                 (dma_params.data_type == OMAP_DMA_DATA_TYPE_S32) ? 32 : 16,
 378                 ((dma_addr & 0x3) == 0) ? "sync" : "async",
 379                 dma_params.src_start, dma_params.dst_start);
 380
 381         omap_set_dma_params(ch, &dma_params);
 382         omap_set_dma_src_burst_mode(ch, src_burst);
 383         omap_set_dma_dest_burst_mode(ch, dst_burst);
 384         omap_set_dma_write_mode(ch, OMAP_DMA_WRITE_LAST_NON_POSTED);
 385
 386         /*
 387          * Prepare MUSB for DMA transfer
 388          */
 389         if (chdat->tx) {
 390                 musb_ep_select(mbase, chdat->epnum);
 391                 csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
 392                 csr |= (MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB
 393                         | MUSB_TXCSR_DMAMODE | MUSB_TXCSR_MODE);
 394                 csr &= ~MUSB_TXCSR_P_UNDERRUN;
 395                 musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
 396         } else {
 397                 musb_ep_select(mbase, chdat->epnum);
 398                 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
 399                 csr |= MUSB_RXCSR_DMAENAB;
 400                 csr &= ~(MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAMODE);
 401                 musb_writew(hw_ep->regs, MUSB_RXCSR,
 402                         csr | MUSB_RXCSR_P_WZC_BITS);
 403         }
 404
 405         /*
 406          * Start DMA transfer
 407          */
 408         omap_start_dma(ch);
 409
 410         if (chdat->tx) {
 411                 /* Send transfer_packet_sz packets at a time */
 412                 psize = musb_readl(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET);
 413                 psize &= ~0x7ff;
 414                 psize |= chdat->transfer_packet_sz;
 415                 musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET, psize);
 416
 417                 musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
 418                         TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len));
 419         } else {
 420                 /* Receive transfer_packet_sz packets at a time */
 421                 psize = musb_readl(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET);
 422                 psize &= ~(0x7ff << 16);
 423                 psize |= (chdat->transfer_packet_sz << 16);
 424                 musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET, psize);
 425
 426                 musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
 427                         TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len));
 428         }
 429
 430         return true;
 431 }
 432
 433 static int tusb_omap_dma_abort(struct dma_channel *channel)
 434 {
 435         struct tusb_omap_dma_ch *chdat = to_chdat(channel);
 436         struct tusb_omap_dma    *tusb_dma = chdat->tusb_dma;
 437
 438         if (!tusb_dma->multichannel) {
 439                 if (tusb_dma->ch >= 0) {
 440                         omap_stop_dma(tusb_dma->ch);
 441                         omap_free_dma(tusb_dma->ch);
 442                         tusb_dma->ch = -1;
 443                 }
 444
 445                 tusb_dma->dmareq = -1;
 446                 tusb_dma->sync_dev = -1;
 447         }
 448
 449         channel->status = MUSB_DMA_STATUS_FREE;
 450
 451         return 0;
 452 }
 453
 454 static inline int tusb_omap_dma_allocate_dmareq(struct tusb_omap_dma_ch *chdat)
 455 {
 456         u32             reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
 457         int             i, dmareq_nr = -1;
 458
 459         const int sync_dev[6] = {
 460                 OMAP24XX_DMA_EXT_DMAREQ0,
 461                 OMAP24XX_DMA_EXT_DMAREQ1,
 462                 OMAP242X_DMA_EXT_DMAREQ2,
 463                 OMAP242X_DMA_EXT_DMAREQ3,
 464                 OMAP242X_DMA_EXT_DMAREQ4,
 465                 OMAP242X_DMA_EXT_DMAREQ5,
 466         };
 467
 468         for (i = 0; i < MAX_DMAREQ; i++) {
 469                 int cur = (reg & (0xf << (i * 5))) >> (i * 5);
 470                 if (cur == 0) {
 471                         dmareq_nr = i;
 472                         break;
 473                 }
 474         }
 475
 476         if (dmareq_nr == -1)
 477                 return -EAGAIN;
 478
 479         reg |= (chdat->epnum << (dmareq_nr * 5));
 480         if (chdat->tx)
 481                 reg |= ((1 << 4) << (dmareq_nr * 5));
 482         musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg);
 483
 484         chdat->dmareq = dmareq_nr;
 485         chdat->sync_dev = sync_dev[chdat->dmareq];
 486
 487         return 0;
 488 }
 489
 490 static inline void tusb_omap_dma_free_dmareq(struct tusb_omap_dma_ch *chdat)
 491 {
 492         u32 reg;
 493
 494         if (!chdat || chdat->dmareq < 0)
 495                 return;
 496
 497         reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
 498         reg &= ~(0x1f << (chdat->dmareq * 5));
 499         musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg);
 500
 501         chdat->dmareq = -1;
 502         chdat->sync_dev = -1;
 503 }
 504
 505 static struct dma_channel *dma_channel_pool[MAX_DMAREQ];
 506
 507 static struct dma_channel *
 508 tusb_omap_dma_allocate(struct dma_controller *c,
 509                 struct musb_hw_ep *hw_ep,
 510                 u8 tx)
 511 {
 512         int ret, i;
 513         const char              *dev_name;
 514         struct tusb_omap_dma    *tusb_dma;
 515         struct musb             *musb;
 516         void __iomem            *tbase;
 517         struct dma_channel      *channel = NULL;
 518         struct tusb_omap_dma_ch *chdat = NULL;
 519         u32                     reg;
 520
 521         tusb_dma = container_of(c, struct tusb_omap_dma, controller);
 522         musb = tusb_dma->musb;
 523         tbase = musb->ctrl_base;
 524
 525         reg = musb_readl(tbase, TUSB_DMA_INT_MASK);
 526         if (tx)
 527                 reg &= ~(1 << hw_ep->epnum);
 528         else
 529                 reg &= ~(1 << (hw_ep->epnum + 15));
 530         musb_writel(tbase, TUSB_DMA_INT_MASK, reg);
 531
 532         /* REVISIT: Why does dmareq5 not work? */
 533         if (hw_ep->epnum == 0) {
 534                 dev_dbg(musb->controller, "Not allowing DMA for ep0 %s\n", tx ? "tx" : "rx");
 535                 return NULL;
 536         }
 537
 538         for (i = 0; i < MAX_DMAREQ; i++) {
 539                 struct dma_channel *ch = dma_channel_pool[i];
 540                 if (ch->status == MUSB_DMA_STATUS_UNKNOWN) {
 541                         ch->status = MUSB_DMA_STATUS_FREE;
 542                         channel = ch;
 543                         chdat = ch->private_data;
 544                         break;
 545                 }
 546         }
 547
 548         if (!channel)
 549                 return NULL;
 550
 551         if (tx) {
 552                 chdat->tx = 1;
 553                 dev_name = "TUSB transmit";
 554         } else {
 555                 chdat->tx = 0;
 556                 dev_name = "TUSB receive";
 557         }
 558
 559         chdat->musb = tusb_dma->musb;
 560         chdat->tbase = tusb_dma->tbase;
 561         chdat->hw_ep = hw_ep;
 562         chdat->epnum = hw_ep->epnum;
 563         chdat->dmareq = -1;
 564         chdat->completed_len = 0;
 565         chdat->tusb_dma = tusb_dma;
 566
 567         channel->max_len = 0x7fffffff;
 568         channel->desired_mode = 0;
 569         channel->actual_len = 0;
 570
 571         if (tusb_dma->multichannel) {
 572                 ret = tusb_omap_dma_allocate_dmareq(chdat);
 573                 if (ret != 0)
 574                         goto free_dmareq;
 575
 576                 ret = omap_request_dma(chdat->sync_dev, dev_name,
 577                                 tusb_omap_dma_cb, channel, &chdat->ch);
 578                 if (ret != 0)
 579                         goto free_dmareq;
 580         } else if (tusb_dma->ch == -1) {
 581                 tusb_dma->dmareq = 0;
 582                 tusb_dma->sync_dev = OMAP24XX_DMA_EXT_DMAREQ0;
 583
 584                 /* Callback data gets set later in the shared dmareq case */
 585                 ret = omap_request_dma(tusb_dma->sync_dev, "TUSB shared",
 586                                 tusb_omap_dma_cb, NULL, &tusb_dma->ch);
 587                 if (ret != 0)
 588                         goto free_dmareq;
 589
 590                 chdat->dmareq = -1;
 591                 chdat->ch = -1;
 592         }
 593
 594         dev_dbg(musb->controller, "ep%i %s dma: %s dma%i dmareq%i sync%i\n",
 595                 chdat->epnum,
 596                 chdat->tx ? "tx" : "rx",
 597                 chdat->ch >= 0 ? "dedicated" : "shared",
 598                 chdat->ch >= 0 ? chdat->ch : tusb_dma->ch,
 599                 chdat->dmareq >= 0 ? chdat->dmareq : tusb_dma->dmareq,
 600                 chdat->sync_dev >= 0 ? chdat->sync_dev : tusb_dma->sync_dev);
 601
 602         return channel;
 603
 604 free_dmareq:
 605         tusb_omap_dma_free_dmareq(chdat);
 606
 607         dev_dbg(musb->controller, "ep%i: Could not get a DMA channel\n", chdat->epnum);
 608         channel->status = MUSB_DMA_STATUS_UNKNOWN;
 609
 610         return NULL;
 611 }
 612
 613 static void tusb_omap_dma_release(struct dma_channel *channel)
 614 {
 615         struct tusb_omap_dma_ch *chdat = to_chdat(channel);
 616         struct musb             *musb = chdat->musb;
 617         void __iomem            *tbase = musb->ctrl_base;
 618         u32                     reg;
 619
 620         dev_dbg(musb->controller, "ep%i ch%i\n", chdat->epnum, chdat->ch);
 621
 622         reg = musb_readl(tbase, TUSB_DMA_INT_MASK);
 623         if (chdat->tx)
 624                 reg |= (1 << chdat->epnum);
 625         else
 626                 reg |= (1 << (chdat->epnum + 15));
 627         musb_writel(tbase, TUSB_DMA_INT_MASK, reg);
 628
 629         reg = musb_readl(tbase, TUSB_DMA_INT_CLEAR);
 630         if (chdat->tx)
 631                 reg |= (1 << chdat->epnum);
 632         else
 633                 reg |= (1 << (chdat->epnum + 15));
 634         musb_writel(tbase, TUSB_DMA_INT_CLEAR, reg);
 635
 636         channel->status = MUSB_DMA_STATUS_UNKNOWN;
 637
 638         if (chdat->ch >= 0) {
 639                 omap_stop_dma(chdat->ch);
 640                 omap_free_dma(chdat->ch);
 641                 chdat->ch = -1;
 642         }
 643
 644         if (chdat->dmareq >= 0)
 645                 tusb_omap_dma_free_dmareq(chdat);
 646
 647         channel = NULL;
 648 }
 649
 650 void dma_controller_destroy(struct dma_controller *c)
 651 {
 652         struct tusb_omap_dma    *tusb_dma;
 653         int                     i;
 654
 655         tusb_dma = container_of(c, struct tusb_omap_dma, controller);
 656         for (i = 0; i < MAX_DMAREQ; i++) {
 657                 struct dma_channel *ch = dma_channel_pool[i];
 658                 if (ch) {
 659                         kfree(ch->private_data);
 660                         kfree(ch);
 661                 }
 662         }
 663
 664         if (tusb_dma && !tusb_dma->multichannel && tusb_dma->ch >= 0)
 665                 omap_free_dma(tusb_dma->ch);
 666
 667         kfree(tusb_dma);
 668 }
 669
 670 struct dma_controller *__init
 671 dma_controller_create(struct musb *musb, void __iomem *base)
 672 {
 673         void __iomem            *tbase = musb->ctrl_base;
 674         struct tusb_omap_dma    *tusb_dma;
 675         int                     i;
 676
 677         /* REVISIT: Get dmareq lines used from board-*.c */
 678
 679         musb_writel(musb->ctrl_base, TUSB_DMA_INT_MASK, 0x7fffffff);
 680         musb_writel(musb->ctrl_base, TUSB_DMA_EP_MAP, 0);
 681
 682         musb_writel(tbase, TUSB_DMA_REQ_CONF,
 683                 TUSB_DMA_REQ_CONF_BURST_SIZE(2)
 684                 | TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f)
 685                 | TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
 686
 687         tusb_dma = kzalloc(sizeof(struct tusb_omap_dma), GFP_KERNEL);
 688         if (!tusb_dma)
 689                 goto out;
 690
 691         tusb_dma->musb = musb;
 692         tusb_dma->tbase = musb->ctrl_base;
 693
 694         tusb_dma->ch = -1;
 695         tusb_dma->dmareq = -1;
 696         tusb_dma->sync_dev = -1;
 697
 698         tusb_dma->controller.start = tusb_omap_dma_start;
 699         tusb_dma->controller.stop = tusb_omap_dma_stop;
 700         tusb_dma->controller.channel_alloc = tusb_omap_dma_allocate;
 701         tusb_dma->controller.channel_release = tusb_omap_dma_release;
 702         tusb_dma->controller.channel_program = tusb_omap_dma_program;
 703         tusb_dma->controller.channel_abort = tusb_omap_dma_abort;
 704
 705         if (tusb_get_revision(musb) >= TUSB_REV_30)
 706                 tusb_dma->multichannel = 1;
 707
 708         for (i = 0; i < MAX_DMAREQ; i++) {
 709                 struct dma_channel      *ch;
 710                 struct tusb_omap_dma_ch *chdat;
 711
 712                 ch = kzalloc(sizeof(struct dma_channel), GFP_KERNEL);
 713                 if (!ch)
 714                         goto cleanup;
 715
 716                 dma_channel_pool[i] = ch;
 717
 718                 chdat = kzalloc(sizeof(struct tusb_omap_dma_ch), GFP_KERNEL);
 719                 if (!chdat)
 720                         goto cleanup;
 721
 722                 ch->status = MUSB_DMA_STATUS_UNKNOWN;
 723                 ch->private_data = chdat;
 724         }
 725
 726         return &tusb_dma->controller;
 727
 728 cleanup:
 729         dma_controller_destroy(&tusb_dma->controller);
 730 out:
 731         return NULL;
 732 }