2 * Copyright (c) 2001-2002 by David Brownell
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 #ifndef __LINUX_EHCI_HCD_H
20 #define __LINUX_EHCI_HCD_H
22 /* definitions used for the EHCI driver */
25 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
26 * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
27 * the host controller implementation.
29 * To facilitate the strongest possible byte-order checking from "sparse"
30 * and so on, we use __leXX unless that's not practical.
32 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
33 typedef __u32 __bitwise __hc32;
34 typedef __u16 __bitwise __hc16;
40 /* statistics can be kept for tuning/monitoring */
45 unsigned long reclaim;
46 unsigned long lost_iaa;
48 /* termination of urbs from core */
49 unsigned long complete;
53 /* ehci_hcd->lock guards shared data against other CPUs:
54 * ehci_hcd: async, reclaim, periodic (and shadow), ...
55 * usb_host_endpoint: hcpriv
56 * ehci_qh: qh_next, qtd_list
59 * Also, hold this lock when talking to HC registers or
60 * when updating hw_* fields in shared qh/qtd/... structures.
63 #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */
65 struct ehci_hcd { /* one per controller */
66 /* glue to PCI and HCD framework */
67 struct ehci_caps __iomem *caps;
68 struct ehci_regs __iomem *regs;
69 struct ehci_dbg_port __iomem *debug;
71 __u32 hcs_params; /* cached register copy */
74 /* async schedule support */
75 struct ehci_qh *async;
76 struct ehci_qh *dummy; /* For AMD quirk use */
77 struct ehci_qh *reclaim;
78 unsigned scanning : 1;
80 /* periodic schedule support */
81 #define DEFAULT_I_TDPS 1024 /* some HCs can do less */
82 unsigned periodic_size;
83 __hc32 *periodic; /* hw periodic table */
84 dma_addr_t periodic_dma;
85 unsigned i_thresh; /* uframes HC might cache */
87 union ehci_shadow *pshadow; /* mirror hw periodic table */
88 int next_uframe; /* scan periodic, start here */
89 unsigned periodic_sched; /* periodic activity count */
90 unsigned uframe_periodic_max; /* max periodic time per uframe */
93 /* list of itds & sitds completed while clock_frame was still active */
94 struct list_head cached_itd_list;
95 struct list_head cached_sitd_list;
98 /* per root hub port */
99 unsigned long reset_done [EHCI_MAX_ROOT_PORTS];
101 /* bit vectors (one bit per port) */
102 unsigned long bus_suspended; /* which ports were
103 already suspended at the start of a bus suspend */
104 unsigned long companion_ports; /* which ports are
105 dedicated to the companion controller */
106 unsigned long owned_ports; /* which ports are
107 owned by the companion during a bus suspend */
108 unsigned long port_c_suspend; /* which ports have
109 the change-suspend feature turned on */
110 unsigned long suspended_ports; /* which ports are
113 /* per-HC memory pools (could be per-bus, but ...) */
114 struct dma_pool *qh_pool; /* qh per active urb */
115 struct dma_pool *qtd_pool; /* one or more per qh */
116 struct dma_pool *itd_pool; /* itd per iso urb */
117 struct dma_pool *sitd_pool; /* sitd per split iso urb */
119 struct timer_list iaa_watchdog;
120 struct timer_list watchdog;
121 unsigned long actions;
123 unsigned periodic_stamp;
124 unsigned random_frame;
125 unsigned long next_statechange;
126 ktime_t last_periodic_enable;
130 unsigned no_selective_suspend:1;
131 unsigned has_fsl_port_bug:1; /* FreeScale */
132 unsigned big_endian_mmio:1;
133 unsigned big_endian_desc:1;
134 unsigned big_endian_capbase:1;
135 unsigned has_amcc_usb23:1;
136 unsigned need_io_watchdog:1;
137 unsigned broken_periodic:1;
138 unsigned amd_pll_fix:1;
139 unsigned fs_i_thresh:1; /* Intel iso scheduling */
140 unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/
141 unsigned has_synopsys_hc_bug:1; /* Synopsys HC */
143 /* required for usb32 quirk */
144 #define OHCI_CTRL_HCFS (3 << 6)
145 #define OHCI_USB_OPER (2 << 6)
146 #define OHCI_USB_SUSPEND (3 << 6)
148 #define OHCI_HCCTRL_OFFSET 0x4
149 #define OHCI_HCCTRL_LEN 0x4
150 __hc32 *ohci_hcctrl_reg;
151 unsigned has_hostpc:1;
152 unsigned has_lpm:1; /* support link power management */
153 unsigned has_ppcd:1; /* support per-port change bits */
154 u8 sbrn; /* packed release number */
158 struct ehci_stats stats;
159 # define COUNT(x) do { (x)++; } while (0)
161 # define COUNT(x) do {} while (0)
166 struct dentry *debug_dir;
169 * OTG controllers and transceivers need software interaction
171 struct otg_transceiver *transceiver;
174 /* convert between an HCD pointer and the corresponding EHCI_HCD */
175 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
177 return (struct ehci_hcd *) (hcd->hcd_priv);
179 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
181 return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
186 iaa_watchdog_start(struct ehci_hcd *ehci)
188 WARN_ON(timer_pending(&ehci->iaa_watchdog));
189 mod_timer(&ehci->iaa_watchdog,
190 jiffies + msecs_to_jiffies(EHCI_IAA_MSECS));
193 static inline void iaa_watchdog_done(struct ehci_hcd *ehci)
195 del_timer(&ehci->iaa_watchdog);
198 enum ehci_timer_action {
205 timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
207 clear_bit (action, &ehci->actions);
210 static void free_cached_lists(struct ehci_hcd *ehci);
212 /*-------------------------------------------------------------------------*/
214 #include <linux/usb/ehci_def.h>
216 /*-------------------------------------------------------------------------*/
218 #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma)
221 * EHCI Specification 0.95 Section 3.5
222 * QTD: describe data transfer components (buffer, direction, ...)
223 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
225 * These are associated only with "QH" (Queue Head) structures,
226 * used with control, bulk, and interrupt transfers.
229 /* first part defined by EHCI spec */
230 __hc32 hw_next; /* see EHCI 3.5.1 */
231 __hc32 hw_alt_next; /* see EHCI 3.5.2 */
232 __hc32 hw_token; /* see EHCI 3.5.3 */
233 #define QTD_TOGGLE (1 << 31) /* data toggle */
234 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
235 #define QTD_IOC (1 << 15) /* interrupt on complete */
236 #define QTD_CERR(tok) (((tok)>>10) & 0x3)
237 #define QTD_PID(tok) (((tok)>>8) & 0x3)
238 #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
239 #define QTD_STS_HALT (1 << 6) /* halted on error */
240 #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
241 #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
242 #define QTD_STS_XACT (1 << 3) /* device gave illegal response */
243 #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
244 #define QTD_STS_STS (1 << 1) /* split transaction state */
245 #define QTD_STS_PING (1 << 0) /* issue PING? */
247 #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE)
248 #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT)
249 #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS)
251 __hc32 hw_buf [5]; /* see EHCI 3.5.4 */
252 __hc32 hw_buf_hi [5]; /* Appendix B */
254 /* the rest is HCD-private */
255 dma_addr_t qtd_dma; /* qtd address */
256 struct list_head qtd_list; /* sw qtd list */
257 struct urb *urb; /* qtd's urb */
258 size_t length; /* length of buffer */
259 } __attribute__ ((aligned (32)));
261 /* mask NakCnt+T in qh->hw_alt_next */
262 #define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f)
264 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
266 /*-------------------------------------------------------------------------*/
268 /* type tag from {qh,itd,sitd,fstn}->hw_next */
269 #define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1))
272 * Now the following defines are not converted using the
273 * cpu_to_le32() macro anymore, since we have to support
274 * "dynamic" switching between be and le support, so that the driver
275 * can be used on one system with SoC EHCI controller using big-endian
276 * descriptors as well as a normal little-endian PCI EHCI controller.
278 /* values for that type tag */
279 #define Q_TYPE_ITD (0 << 1)
280 #define Q_TYPE_QH (1 << 1)
281 #define Q_TYPE_SITD (2 << 1)
282 #define Q_TYPE_FSTN (3 << 1)
284 /* next async queue entry, or pointer to interrupt/periodic QH */
285 #define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH))
287 /* for periodic/async schedules and qtd lists, mark end of list */
288 #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
291 * Entries in periodic shadow table are pointers to one of four kinds
292 * of data structure. That's dictated by the hardware; a type tag is
293 * encoded in the low bits of the hardware's periodic schedule. Use
294 * Q_NEXT_TYPE to get the tag.
296 * For entries in the async schedule, the type tag always says "qh".
299 struct ehci_qh *qh; /* Q_TYPE_QH */
300 struct ehci_itd *itd; /* Q_TYPE_ITD */
301 struct ehci_sitd *sitd; /* Q_TYPE_SITD */
302 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */
303 __hc32 *hw_next; /* (all types) */
307 /*-------------------------------------------------------------------------*/
310 * EHCI Specification 0.95 Section 3.6
311 * QH: describes control/bulk/interrupt endpoints
312 * See Fig 3-7 "Queue Head Structure Layout".
314 * These appear in both the async and (for interrupt) periodic schedules.
317 /* first part defined by EHCI spec */
319 __hc32 hw_next; /* see EHCI 3.6.1 */
320 __hc32 hw_info1; /* see EHCI 3.6.2 */
321 #define QH_HEAD 0x00008000
322 __hc32 hw_info2; /* see EHCI 3.6.2 */
323 #define QH_SMASK 0x000000ff
324 #define QH_CMASK 0x0000ff00
325 #define QH_HUBADDR 0x007f0000
326 #define QH_HUBPORT 0x3f800000
327 #define QH_MULT 0xc0000000
328 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */
330 /* qtd overlay (hardware parts of a struct ehci_qtd) */
335 __hc32 hw_buf_hi [5];
336 } __attribute__ ((aligned(32)));
339 struct ehci_qh_hw *hw;
340 /* the rest is HCD-private */
341 dma_addr_t qh_dma; /* address of qh */
342 union ehci_shadow qh_next; /* ptr to qh; or periodic */
343 struct list_head qtd_list; /* sw qtd list */
344 struct ehci_qtd *dummy;
345 struct ehci_qh *reclaim; /* next to reclaim */
347 struct ehci_hcd *ehci;
350 * Do NOT use atomic operations for QH refcounting. On some CPUs
351 * (PPC7448 for example), atomic operations cannot be performed on
352 * memory that is cache-inhibited (i.e. being used for DMA).
353 * Spinlocks are used to protect all QH fields.
358 u8 needs_rescan; /* Dequeue during giveback */
360 #define QH_STATE_LINKED 1 /* HC sees this */
361 #define QH_STATE_UNLINK 2 /* HC may still see this */
362 #define QH_STATE_IDLE 3 /* HC doesn't see this */
363 #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */
364 #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
366 u8 xacterrs; /* XactErr retry counter */
367 #define QH_XACTERR_MAX 32 /* XactErr retry limit */
369 /* periodic schedule info */
370 u8 usecs; /* intr bandwidth */
371 u8 gap_uf; /* uframes split/csplit gap */
372 u8 c_usecs; /* ... split completion bw */
373 u16 tt_usecs; /* tt downstream bandwidth */
374 unsigned short period; /* polling interval */
375 unsigned short start; /* where polling starts */
376 #define NO_FRAME ((unsigned short)~0) /* pick new start */
378 struct usb_device *dev; /* access to TT */
379 unsigned clearing_tt:1; /* Clear-TT-Buf in progress */
382 /*-------------------------------------------------------------------------*/
384 /* description of one iso transaction (up to 3 KB data if highspeed) */
385 struct ehci_iso_packet {
386 /* These will be copied to iTD when scheduling */
387 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */
388 __hc32 transaction; /* itd->hw_transaction[i] |= */
389 u8 cross; /* buf crosses pages */
390 /* for full speed OUT splits */
394 /* temporary schedule data for packets from iso urbs (both speeds)
395 * each packet is one logical usb transaction to the device (not TT),
396 * beginning at stream->next_uframe
398 struct ehci_iso_sched {
399 struct list_head td_list;
401 struct ehci_iso_packet packet [0];
405 * ehci_iso_stream - groups all (s)itds for this endpoint.
406 * acts like a qh would, if EHCI had them for ISO.
408 struct ehci_iso_stream {
409 /* first field matches ehci_hq, but is NULL */
410 struct ehci_qh_hw *hw;
415 struct list_head td_list; /* queued itds/sitds */
416 struct list_head free_list; /* list of unused itds/sitds */
417 struct usb_device *udev;
418 struct usb_host_endpoint *ep;
420 /* output of (re)scheduling */
424 /* the rest is derived from the endpoint descriptor,
425 * trusting urb->interval == f(epdesc->bInterval) and
426 * including the extra info for hw_bufp[0..2]
435 /* This is used to initialize iTD's hw_bufp fields */
440 /* this is used to initialize sITD's tt info */
444 /*-------------------------------------------------------------------------*/
447 * EHCI Specification 0.95 Section 3.3
448 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
450 * Schedule records for high speed iso xfers
453 /* first part defined by EHCI spec */
454 __hc32 hw_next; /* see EHCI 3.3.1 */
455 __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */
456 #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
457 #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */
458 #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */
459 #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
460 #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
461 #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */
463 #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
465 __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */
466 __hc32 hw_bufp_hi [7]; /* Appendix B */
468 /* the rest is HCD-private */
469 dma_addr_t itd_dma; /* for this itd */
470 union ehci_shadow itd_next; /* ptr to periodic q entry */
473 struct ehci_iso_stream *stream; /* endpoint's queue */
474 struct list_head itd_list; /* list of stream's itds */
476 /* any/all hw_transactions here may be used by that urb */
477 unsigned frame; /* where scheduled */
479 unsigned index[8]; /* in urb->iso_frame_desc */
480 } __attribute__ ((aligned (32)));
482 /*-------------------------------------------------------------------------*/
485 * EHCI Specification 0.95 Section 3.4
486 * siTD, aka split-transaction isochronous Transfer Descriptor
487 * ... describe full speed iso xfers through TT in hubs
488 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
491 /* first part defined by EHCI spec */
493 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
494 __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */
495 __hc32 hw_uframe; /* EHCI table 3-10 */
496 __hc32 hw_results; /* EHCI table 3-11 */
497 #define SITD_IOC (1 << 31) /* interrupt on completion */
498 #define SITD_PAGE (1 << 30) /* buffer 0/1 */
499 #define SITD_LENGTH(x) (0x3ff & ((x)>>16))
500 #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */
501 #define SITD_STS_ERR (1 << 6) /* error from TT */
502 #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */
503 #define SITD_STS_BABBLE (1 << 4) /* device was babbling */
504 #define SITD_STS_XACT (1 << 3) /* illegal IN response */
505 #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */
506 #define SITD_STS_STS (1 << 1) /* split transaction state */
508 #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE)
510 __hc32 hw_buf [2]; /* EHCI table 3-12 */
511 __hc32 hw_backpointer; /* EHCI table 3-13 */
512 __hc32 hw_buf_hi [2]; /* Appendix B */
514 /* the rest is HCD-private */
516 union ehci_shadow sitd_next; /* ptr to periodic q entry */
519 struct ehci_iso_stream *stream; /* endpoint's queue */
520 struct list_head sitd_list; /* list of stream's sitds */
523 } __attribute__ ((aligned (32)));
525 /*-------------------------------------------------------------------------*/
528 * EHCI Specification 0.96 Section 3.7
529 * Periodic Frame Span Traversal Node (FSTN)
531 * Manages split interrupt transactions (using TT) that span frame boundaries
532 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN
533 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
534 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
537 __hc32 hw_next; /* any periodic q entry */
538 __hc32 hw_prev; /* qh or EHCI_LIST_END */
540 /* the rest is HCD-private */
542 union ehci_shadow fstn_next; /* ptr to periodic q entry */
543 } __attribute__ ((aligned (32)));
545 /*-------------------------------------------------------------------------*/
547 /* Prepare the PORTSC wakeup flags during controller suspend/resume */
549 #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \
550 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup);
552 #define ehci_prepare_ports_for_controller_resume(ehci) \
553 ehci_adjust_port_wakeup_flags(ehci, false, false);
555 /*-------------------------------------------------------------------------*/
557 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
560 * Some EHCI controllers have a Transaction Translator built into the
561 * root hub. This is a non-standard feature. Each controller will need
562 * to add code to the following inline functions, and call them as
563 * needed (mostly in root hub code).
566 #define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt)
568 /* Returns the speed of a device attached to a port on the root hub. */
569 static inline unsigned int
570 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
572 if (ehci_is_TDI(ehci)) {
573 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
577 return USB_PORT_STAT_LOW_SPEED;
580 return USB_PORT_STAT_HIGH_SPEED;
583 return USB_PORT_STAT_HIGH_SPEED;
588 #define ehci_is_TDI(e) (0)
590 #define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED
593 /*-------------------------------------------------------------------------*/
595 #ifdef CONFIG_PPC_83xx
596 /* Some Freescale processors have an erratum in which the TT
597 * port number in the queue head was 0..N-1 instead of 1..N.
599 #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug)
601 #define ehci_has_fsl_portno_bug(e) (0)
605 * While most USB host controllers implement their registers in
606 * little-endian format, a minority (celleb companion chip) implement
607 * them in big endian format.
609 * This attempts to support either format at compile time without a
610 * runtime penalty, or both formats with the additional overhead
611 * of checking a flag bit.
613 * ehci_big_endian_capbase is a special quirk for controllers that
614 * implement the HC capability registers as separate registers and not
615 * as fields of a 32-bit register.
618 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
619 #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio)
620 #define ehci_big_endian_capbase(e) ((e)->big_endian_capbase)
622 #define ehci_big_endian_mmio(e) 0
623 #define ehci_big_endian_capbase(e) 0
627 * Big-endian read/write functions are arch-specific.
628 * Other arches can be added if/when they're needed.
630 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
631 #define readl_be(addr) __raw_readl((__force unsigned *)addr)
632 #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr)
635 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
636 __u32 __iomem * regs)
638 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
639 return ehci_big_endian_mmio(ehci) ?
647 static inline void ehci_writel(const struct ehci_hcd *ehci,
648 const unsigned int val, __u32 __iomem *regs)
650 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
651 ehci_big_endian_mmio(ehci) ?
652 writel_be(val, regs) :
660 * On certain ppc-44x SoC there is a HW issue, that could only worked around with
661 * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch.
662 * Other common bits are dependent on has_amcc_usb23 quirk flag.
665 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
669 hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);
671 hc_control |= OHCI_USB_OPER;
673 hc_control |= OHCI_USB_SUSPEND;
675 writel_be(hc_control, ehci->ohci_hcctrl_reg);
676 (void) readl_be(ehci->ohci_hcctrl_reg);
679 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
683 /*-------------------------------------------------------------------------*/
686 * The AMCC 440EPx not only implements its EHCI registers in big-endian
687 * format, but also its DMA data structures (descriptors).
689 * EHCI controllers accessed through PCI work normally (little-endian
690 * everywhere), so we won't bother supporting a BE-only mode for now.
692 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
693 #define ehci_big_endian_desc(e) ((e)->big_endian_desc)
696 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
698 return ehci_big_endian_desc(ehci)
699 ? (__force __hc32)cpu_to_be32(x)
700 : (__force __hc32)cpu_to_le32(x);
704 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
706 return ehci_big_endian_desc(ehci)
707 ? be32_to_cpu((__force __be32)x)
708 : le32_to_cpu((__force __le32)x);
711 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
713 return ehci_big_endian_desc(ehci)
714 ? be32_to_cpup((__force __be32 *)x)
715 : le32_to_cpup((__force __le32 *)x);
721 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
723 return cpu_to_le32(x);
727 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
729 return le32_to_cpu(x);
732 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
734 return le32_to_cpup(x);
739 /*-------------------------------------------------------------------------*/
742 #define STUB_DEBUG_FILES
745 /*-------------------------------------------------------------------------*/
747 #endif /* __LINUX_EHCI_HCD_H */