2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
7 * based off of the old drivers/char/sh-sci.c by:
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
14 * Removed SH7300 support (Jul 2007).
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
26 #include <linux/module.h>
27 #include <linux/errno.h>
28 #include <linux/timer.h>
29 #include <linux/interrupt.h>
30 #include <linux/tty.h>
31 #include <linux/tty_flip.h>
32 #include <linux/serial.h>
33 #include <linux/major.h>
34 #include <linux/string.h>
35 #include <linux/sysrq.h>
36 #include <linux/ioport.h>
38 #include <linux/init.h>
39 #include <linux/delay.h>
40 #include <linux/console.h>
41 #include <linux/platform_device.h>
42 #include <linux/serial_sci.h>
43 #include <linux/pm_runtime.h>
44 #include <linux/cpufreq.h>
45 #include <linux/clk.h>
46 #include <linux/ctype.h>
47 #include <linux/err.h>
48 #include <linux/dmaengine.h>
49 #include <linux/dma-mapping.h>
50 #include <linux/scatterlist.h>
51 #include <linux/slab.h>
54 #include <asm/sh_bios.h>
60 struct uart_port port;
62 /* Platform configuration */
63 struct plat_sci_port *cfg;
66 struct timer_list break_timer;
74 char *irqstr[SCIx_NR_IRQS];
76 struct dma_chan *chan_tx;
77 struct dma_chan *chan_rx;
79 #ifdef CONFIG_SERIAL_SH_SCI_DMA
80 struct dma_async_tx_descriptor *desc_tx;
81 struct dma_async_tx_descriptor *desc_rx[2];
82 dma_cookie_t cookie_tx;
83 dma_cookie_t cookie_rx[2];
84 dma_cookie_t active_rx;
85 struct scatterlist sg_tx;
86 unsigned int sg_len_tx;
87 struct scatterlist sg_rx[2];
89 struct sh_dmae_slave param_tx;
90 struct sh_dmae_slave param_rx;
91 struct work_struct work_tx;
92 struct work_struct work_rx;
93 struct timer_list rx_timer;
94 unsigned int rx_timeout;
97 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
98 unsigned short saved_smr;
99 unsigned short saved_fcr;
100 unsigned char saved_brr;
104 /* Function prototypes */
105 static void sci_start_tx(struct uart_port *port);
106 static void sci_stop_tx(struct uart_port *port);
107 static void sci_start_rx(struct uart_port *port);
109 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
111 static struct sci_port sci_ports[SCI_NPORTS];
112 static struct uart_driver sci_uart_driver;
114 static inline struct sci_port *
115 to_sci_port(struct uart_port *uart)
117 return container_of(uart, struct sci_port, port);
120 struct plat_sci_reg {
124 /* Helper for invalidating specific entries of an inherited map. */
125 #define sci_reg_invalid { .offset = 0, .size = 0 }
127 static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
128 [SCIx_PROBE_REGTYPE] = {
129 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
133 * Common SCI definitions, dependent on the port's regshift
136 [SCIx_SCI_REGTYPE] = {
137 [SCSMR] = { 0x00, 8 },
138 [SCBRR] = { 0x01, 8 },
139 [SCSCR] = { 0x02, 8 },
140 [SCxTDR] = { 0x03, 8 },
141 [SCxSR] = { 0x04, 8 },
142 [SCxRDR] = { 0x05, 8 },
143 [SCFCR] = sci_reg_invalid,
144 [SCFDR] = sci_reg_invalid,
145 [SCTFDR] = sci_reg_invalid,
146 [SCRFDR] = sci_reg_invalid,
147 [SCSPTR] = sci_reg_invalid,
148 [SCLSR] = sci_reg_invalid,
152 * Common definitions for legacy IrDA ports, dependent on
155 [SCIx_IRDA_REGTYPE] = {
156 [SCSMR] = { 0x00, 8 },
157 [SCBRR] = { 0x01, 8 },
158 [SCSCR] = { 0x02, 8 },
159 [SCxTDR] = { 0x03, 8 },
160 [SCxSR] = { 0x04, 8 },
161 [SCxRDR] = { 0x05, 8 },
162 [SCFCR] = { 0x06, 8 },
163 [SCFDR] = { 0x07, 16 },
164 [SCTFDR] = sci_reg_invalid,
165 [SCRFDR] = sci_reg_invalid,
166 [SCSPTR] = sci_reg_invalid,
167 [SCLSR] = sci_reg_invalid,
171 * Common SCIFA definitions.
173 [SCIx_SCIFA_REGTYPE] = {
174 [SCSMR] = { 0x00, 16 },
175 [SCBRR] = { 0x04, 8 },
176 [SCSCR] = { 0x08, 16 },
177 [SCxTDR] = { 0x20, 8 },
178 [SCxSR] = { 0x14, 16 },
179 [SCxRDR] = { 0x24, 8 },
180 [SCFCR] = { 0x18, 16 },
181 [SCFDR] = { 0x1c, 16 },
182 [SCTFDR] = sci_reg_invalid,
183 [SCRFDR] = sci_reg_invalid,
184 [SCSPTR] = sci_reg_invalid,
185 [SCLSR] = sci_reg_invalid,
189 * Common SCIFB definitions.
191 [SCIx_SCIFB_REGTYPE] = {
192 [SCSMR] = { 0x00, 16 },
193 [SCBRR] = { 0x04, 8 },
194 [SCSCR] = { 0x08, 16 },
195 [SCxTDR] = { 0x40, 8 },
196 [SCxSR] = { 0x14, 16 },
197 [SCxRDR] = { 0x60, 8 },
198 [SCFCR] = { 0x18, 16 },
199 [SCFDR] = { 0x1c, 16 },
200 [SCTFDR] = sci_reg_invalid,
201 [SCRFDR] = sci_reg_invalid,
202 [SCSPTR] = sci_reg_invalid,
203 [SCLSR] = sci_reg_invalid,
207 * Common SH-2(A) SCIF definitions for ports with FIFO data
210 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
211 [SCSMR] = { 0x00, 16 },
212 [SCBRR] = { 0x04, 8 },
213 [SCSCR] = { 0x08, 16 },
214 [SCxTDR] = { 0x0c, 8 },
215 [SCxSR] = { 0x10, 16 },
216 [SCxRDR] = { 0x14, 8 },
217 [SCFCR] = { 0x18, 16 },
218 [SCFDR] = { 0x1c, 16 },
219 [SCTFDR] = sci_reg_invalid,
220 [SCRFDR] = sci_reg_invalid,
221 [SCSPTR] = { 0x20, 16 },
222 [SCLSR] = { 0x24, 16 },
226 * Common SH-3 SCIF definitions.
228 [SCIx_SH3_SCIF_REGTYPE] = {
229 [SCSMR] = { 0x00, 8 },
230 [SCBRR] = { 0x02, 8 },
231 [SCSCR] = { 0x04, 8 },
232 [SCxTDR] = { 0x06, 8 },
233 [SCxSR] = { 0x08, 16 },
234 [SCxRDR] = { 0x0a, 8 },
235 [SCFCR] = { 0x0c, 8 },
236 [SCFDR] = { 0x0e, 16 },
237 [SCTFDR] = sci_reg_invalid,
238 [SCRFDR] = sci_reg_invalid,
239 [SCSPTR] = sci_reg_invalid,
240 [SCLSR] = sci_reg_invalid,
244 * Common SH-4(A) SCIF(B) definitions.
246 [SCIx_SH4_SCIF_REGTYPE] = {
247 [SCSMR] = { 0x00, 16 },
248 [SCBRR] = { 0x04, 8 },
249 [SCSCR] = { 0x08, 16 },
250 [SCxTDR] = { 0x0c, 8 },
251 [SCxSR] = { 0x10, 16 },
252 [SCxRDR] = { 0x14, 8 },
253 [SCFCR] = { 0x18, 16 },
254 [SCFDR] = { 0x1c, 16 },
255 [SCTFDR] = sci_reg_invalid,
256 [SCRFDR] = sci_reg_invalid,
257 [SCSPTR] = { 0x20, 16 },
258 [SCLSR] = { 0x24, 16 },
262 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
265 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
266 [SCSMR] = { 0x00, 16 },
267 [SCBRR] = { 0x04, 8 },
268 [SCSCR] = { 0x08, 16 },
269 [SCxTDR] = { 0x0c, 8 },
270 [SCxSR] = { 0x10, 16 },
271 [SCxRDR] = { 0x14, 8 },
272 [SCFCR] = { 0x18, 16 },
273 [SCFDR] = { 0x1c, 16 },
274 [SCTFDR] = sci_reg_invalid,
275 [SCRFDR] = sci_reg_invalid,
276 [SCSPTR] = sci_reg_invalid,
277 [SCLSR] = { 0x24, 16 },
281 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
284 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
285 [SCSMR] = { 0x00, 16 },
286 [SCBRR] = { 0x04, 8 },
287 [SCSCR] = { 0x08, 16 },
288 [SCxTDR] = { 0x0c, 8 },
289 [SCxSR] = { 0x10, 16 },
290 [SCxRDR] = { 0x14, 8 },
291 [SCFCR] = { 0x18, 16 },
292 [SCFDR] = { 0x1c, 16 },
293 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
294 [SCRFDR] = { 0x20, 16 },
295 [SCSPTR] = { 0x24, 16 },
296 [SCLSR] = { 0x28, 16 },
300 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
303 [SCIx_SH7705_SCIF_REGTYPE] = {
304 [SCSMR] = { 0x00, 16 },
305 [SCBRR] = { 0x04, 8 },
306 [SCSCR] = { 0x08, 16 },
307 [SCxTDR] = { 0x20, 8 },
308 [SCxSR] = { 0x14, 16 },
309 [SCxRDR] = { 0x24, 8 },
310 [SCFCR] = { 0x18, 16 },
311 [SCFDR] = { 0x1c, 16 },
312 [SCTFDR] = sci_reg_invalid,
313 [SCRFDR] = sci_reg_invalid,
314 [SCSPTR] = sci_reg_invalid,
315 [SCLSR] = sci_reg_invalid,
319 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
322 * The "offset" here is rather misleading, in that it refers to an enum
323 * value relative to the port mapping rather than the fixed offset
324 * itself, which needs to be manually retrieved from the platform's
325 * register map for the given port.
327 static unsigned int sci_serial_in(struct uart_port *p, int offset)
329 struct plat_sci_reg *reg = sci_getreg(p, offset);
332 return ioread8(p->membase + (reg->offset << p->regshift));
333 else if (reg->size == 16)
334 return ioread16(p->membase + (reg->offset << p->regshift));
336 WARN(1, "Invalid register access\n");
341 static void sci_serial_out(struct uart_port *p, int offset, int value)
343 struct plat_sci_reg *reg = sci_getreg(p, offset);
346 iowrite8(value, p->membase + (reg->offset << p->regshift));
347 else if (reg->size == 16)
348 iowrite16(value, p->membase + (reg->offset << p->regshift));
350 WARN(1, "Invalid register access\n");
353 #define sci_in(up, offset) (up->serial_in(up, offset))
354 #define sci_out(up, offset, value) (up->serial_out(up, offset, value))
356 static int sci_probe_regmap(struct plat_sci_port *cfg)
360 cfg->regtype = SCIx_SCI_REGTYPE;
363 cfg->regtype = SCIx_IRDA_REGTYPE;
366 cfg->regtype = SCIx_SCIFA_REGTYPE;
369 cfg->regtype = SCIx_SCIFB_REGTYPE;
373 * The SH-4 is a bit of a misnomer here, although that's
374 * where this particular port layout originated. This
375 * configuration (or some slight variation thereof)
376 * remains the dominant model for all SCIFs.
378 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
381 printk(KERN_ERR "Can't probe register map for given port\n");
388 static void sci_port_enable(struct sci_port *sci_port)
390 if (!sci_port->port.dev)
393 pm_runtime_get_sync(sci_port->port.dev);
395 clk_enable(sci_port->iclk);
396 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
397 clk_enable(sci_port->fclk);
400 static void sci_port_disable(struct sci_port *sci_port)
402 if (!sci_port->port.dev)
405 clk_disable(sci_port->fclk);
406 clk_disable(sci_port->iclk);
408 pm_runtime_put_sync(sci_port->port.dev);
411 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
413 #ifdef CONFIG_CONSOLE_POLL
414 static int sci_poll_get_char(struct uart_port *port)
416 unsigned short status;
420 status = sci_in(port, SCxSR);
421 if (status & SCxSR_ERRORS(port)) {
422 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
428 if (!(status & SCxSR_RDxF(port)))
431 c = sci_in(port, SCxRDR);
435 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
441 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
443 unsigned short status;
446 status = sci_in(port, SCxSR);
447 } while (!(status & SCxSR_TDxE(port)));
449 sci_out(port, SCxTDR, c);
450 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
452 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
454 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
456 struct sci_port *s = to_sci_port(port);
457 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
460 * Use port-specific handler if provided.
462 if (s->cfg->ops && s->cfg->ops->init_pins) {
463 s->cfg->ops->init_pins(port, cflag);
468 * For the generic path SCSPTR is necessary. Bail out if that's
474 if (!(cflag & CRTSCTS))
475 sci_out(port, SCSPTR, 0x0080); /* Set RTS = 1 */
478 static int sci_txfill(struct uart_port *port)
480 struct plat_sci_reg *reg;
482 reg = sci_getreg(port, SCTFDR);
484 return sci_in(port, SCTFDR) & 0xff;
486 reg = sci_getreg(port, SCFDR);
488 return sci_in(port, SCFDR) >> 8;
490 return !(sci_in(port, SCxSR) & SCI_TDRE);
493 static int sci_txroom(struct uart_port *port)
495 return port->fifosize - sci_txfill(port);
498 static int sci_rxfill(struct uart_port *port)
500 struct plat_sci_reg *reg;
502 reg = sci_getreg(port, SCRFDR);
504 return sci_in(port, SCRFDR) & 0xff;
506 reg = sci_getreg(port, SCFDR);
508 return sci_in(port, SCFDR) & ((port->fifosize << 1) - 1);
510 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
514 * SCI helper for checking the state of the muxed port/RXD pins.
516 static inline int sci_rxd_in(struct uart_port *port)
518 struct sci_port *s = to_sci_port(port);
520 if (s->cfg->port_reg <= 0)
523 return !!__raw_readb(s->cfg->port_reg);
526 /* ********************************************************************** *
527 * the interrupt related routines *
528 * ********************************************************************** */
530 static void sci_transmit_chars(struct uart_port *port)
532 struct circ_buf *xmit = &port->state->xmit;
533 unsigned int stopped = uart_tx_stopped(port);
534 unsigned short status;
538 status = sci_in(port, SCxSR);
539 if (!(status & SCxSR_TDxE(port))) {
540 ctrl = sci_in(port, SCSCR);
541 if (uart_circ_empty(xmit))
545 sci_out(port, SCSCR, ctrl);
549 count = sci_txroom(port);
557 } else if (!uart_circ_empty(xmit) && !stopped) {
558 c = xmit->buf[xmit->tail];
559 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
564 sci_out(port, SCxTDR, c);
567 } while (--count > 0);
569 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
571 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
572 uart_write_wakeup(port);
573 if (uart_circ_empty(xmit)) {
576 ctrl = sci_in(port, SCSCR);
578 if (port->type != PORT_SCI) {
579 sci_in(port, SCxSR); /* Dummy read */
580 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
584 sci_out(port, SCSCR, ctrl);
588 /* On SH3, SCIF may read end-of-break as a space->mark char */
589 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
591 static void sci_receive_chars(struct uart_port *port)
593 struct sci_port *sci_port = to_sci_port(port);
594 struct tty_struct *tty = port->state->port.tty;
595 int i, count, copied = 0;
596 unsigned short status;
599 status = sci_in(port, SCxSR);
600 if (!(status & SCxSR_RDxF(port)))
604 /* Don't copy more bytes than there is room for in the buffer */
605 count = tty_buffer_request_room(tty, sci_rxfill(port));
607 /* If for any reason we can't copy more data, we're done! */
611 if (port->type == PORT_SCI) {
612 char c = sci_in(port, SCxRDR);
613 if (uart_handle_sysrq_char(port, c) ||
614 sci_port->break_flag)
617 tty_insert_flip_char(tty, c, TTY_NORMAL);
619 for (i = 0; i < count; i++) {
620 char c = sci_in(port, SCxRDR);
621 status = sci_in(port, SCxSR);
622 #if defined(CONFIG_CPU_SH3)
623 /* Skip "chars" during break */
624 if (sci_port->break_flag) {
626 (status & SCxSR_FER(port))) {
631 /* Nonzero => end-of-break */
632 dev_dbg(port->dev, "debounce<%02x>\n", c);
633 sci_port->break_flag = 0;
640 #endif /* CONFIG_CPU_SH3 */
641 if (uart_handle_sysrq_char(port, c)) {
646 /* Store data and status */
647 if (status & SCxSR_FER(port)) {
649 dev_notice(port->dev, "frame error\n");
650 } else if (status & SCxSR_PER(port)) {
652 dev_notice(port->dev, "parity error\n");
656 tty_insert_flip_char(tty, c, flag);
660 sci_in(port, SCxSR); /* dummy read */
661 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
664 port->icount.rx += count;
668 /* Tell the rest of the system the news. New characters! */
669 tty_flip_buffer_push(tty);
671 /* TTY buffers full; read from RX reg to prevent lockup */
672 sci_in(port, SCxRDR);
673 sci_in(port, SCxSR); /* dummy read */
674 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
678 #define SCI_BREAK_JIFFIES (HZ/20)
681 * The sci generates interrupts during the break,
682 * 1 per millisecond or so during the break period, for 9600 baud.
683 * So dont bother disabling interrupts.
684 * But dont want more than 1 break event.
685 * Use a kernel timer to periodically poll the rx line until
686 * the break is finished.
688 static inline void sci_schedule_break_timer(struct sci_port *port)
690 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
693 /* Ensure that two consecutive samples find the break over. */
694 static void sci_break_timer(unsigned long data)
696 struct sci_port *port = (struct sci_port *)data;
698 sci_port_enable(port);
700 if (sci_rxd_in(&port->port) == 0) {
701 port->break_flag = 1;
702 sci_schedule_break_timer(port);
703 } else if (port->break_flag == 1) {
705 port->break_flag = 2;
706 sci_schedule_break_timer(port);
708 port->break_flag = 0;
710 sci_port_disable(port);
713 static int sci_handle_errors(struct uart_port *port)
716 unsigned short status = sci_in(port, SCxSR);
717 struct tty_struct *tty = port->state->port.tty;
718 struct sci_port *s = to_sci_port(port);
721 * Handle overruns, if supported.
723 if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) {
724 if (status & (1 << s->cfg->overrun_bit)) {
726 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
729 dev_notice(port->dev, "overrun error");
733 if (status & SCxSR_FER(port)) {
734 if (sci_rxd_in(port) == 0) {
735 /* Notify of BREAK */
736 struct sci_port *sci_port = to_sci_port(port);
738 if (!sci_port->break_flag) {
739 sci_port->break_flag = 1;
740 sci_schedule_break_timer(sci_port);
742 /* Do sysrq handling. */
743 if (uart_handle_break(port))
746 dev_dbg(port->dev, "BREAK detected\n");
748 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
754 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
757 dev_notice(port->dev, "frame error\n");
761 if (status & SCxSR_PER(port)) {
763 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
766 dev_notice(port->dev, "parity error");
770 tty_flip_buffer_push(tty);
775 static int sci_handle_fifo_overrun(struct uart_port *port)
777 struct tty_struct *tty = port->state->port.tty;
778 struct sci_port *s = to_sci_port(port);
779 struct plat_sci_reg *reg;
782 reg = sci_getreg(port, SCLSR);
786 if ((sci_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) {
787 sci_out(port, SCLSR, 0);
789 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
790 tty_flip_buffer_push(tty);
792 dev_notice(port->dev, "overrun error\n");
799 static int sci_handle_breaks(struct uart_port *port)
802 unsigned short status = sci_in(port, SCxSR);
803 struct tty_struct *tty = port->state->port.tty;
804 struct sci_port *s = to_sci_port(port);
806 if (uart_handle_break(port))
809 if (!s->break_flag && status & SCxSR_BRK(port)) {
810 #if defined(CONFIG_CPU_SH3)
814 /* Notify of BREAK */
815 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
818 dev_dbg(port->dev, "BREAK detected\n");
822 tty_flip_buffer_push(tty);
824 copied += sci_handle_fifo_overrun(port);
829 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
831 #ifdef CONFIG_SERIAL_SH_SCI_DMA
832 struct uart_port *port = ptr;
833 struct sci_port *s = to_sci_port(port);
836 u16 scr = sci_in(port, SCSCR);
837 u16 ssr = sci_in(port, SCxSR);
839 /* Disable future Rx interrupts */
840 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
841 disable_irq_nosync(irq);
846 sci_out(port, SCSCR, scr);
847 /* Clear current interrupt */
848 sci_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
849 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
850 jiffies, s->rx_timeout);
851 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
857 /* I think sci_receive_chars has to be called irrespective
858 * of whether the I_IXOFF is set, otherwise, how is the interrupt
861 sci_receive_chars(ptr);
866 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
868 struct uart_port *port = ptr;
871 spin_lock_irqsave(&port->lock, flags);
872 sci_transmit_chars(port);
873 spin_unlock_irqrestore(&port->lock, flags);
878 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
880 struct uart_port *port = ptr;
883 if (port->type == PORT_SCI) {
884 if (sci_handle_errors(port)) {
885 /* discard character in rx buffer */
887 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
890 sci_handle_fifo_overrun(port);
891 sci_rx_interrupt(irq, ptr);
894 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
896 /* Kick the transmission */
897 sci_tx_interrupt(irq, ptr);
902 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
904 struct uart_port *port = ptr;
907 sci_handle_breaks(port);
908 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
913 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
916 * Not all ports (such as SCIFA) will support REIE. Rather than
917 * special-casing the port type, we check the port initialization
918 * IRQ enable mask to see whether the IRQ is desired at all. If
919 * it's unset, it's logically inferred that there's no point in
922 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
925 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
927 unsigned short ssr_status, scr_status, err_enabled;
928 struct uart_port *port = ptr;
929 struct sci_port *s = to_sci_port(port);
930 irqreturn_t ret = IRQ_NONE;
932 ssr_status = sci_in(port, SCxSR);
933 scr_status = sci_in(port, SCSCR);
934 err_enabled = scr_status & port_rx_irq_mask(port);
937 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
939 ret = sci_tx_interrupt(irq, ptr);
942 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
945 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
946 (scr_status & SCSCR_RIE))
947 ret = sci_rx_interrupt(irq, ptr);
949 /* Error Interrupt */
950 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
951 ret = sci_er_interrupt(irq, ptr);
953 /* Break Interrupt */
954 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
955 ret = sci_br_interrupt(irq, ptr);
960 static struct sci_irq_desc {
962 irq_handler_t handler;
965 * Split out handlers, the default case.
969 .handler = sci_er_interrupt,
974 .handler = sci_rx_interrupt,
979 .handler = sci_tx_interrupt,
984 .handler = sci_br_interrupt,
988 * Special muxed handler.
992 .handler = sci_mpxed_interrupt,
996 static int sci_request_irq(struct sci_port *port)
998 struct uart_port *up = &port->port;
1001 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1002 struct sci_irq_desc *desc;
1005 if (SCIx_IRQ_IS_MUXED(port)) {
1009 irq = port->cfg->irqs[i];
1011 desc = sci_irq_desc + i;
1012 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1013 dev_name(up->dev), desc->desc);
1014 if (!port->irqstr[j]) {
1015 dev_err(up->dev, "Failed to allocate %s IRQ string\n",
1020 ret = request_irq(irq, desc->handler, up->irqflags,
1021 port->irqstr[j], port);
1022 if (unlikely(ret)) {
1023 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1032 free_irq(port->cfg->irqs[i], port);
1036 kfree(port->irqstr[j]);
1041 static void sci_free_irq(struct sci_port *port)
1046 * Intentionally in reverse order so we iterate over the muxed
1049 for (i = 0; i < SCIx_NR_IRQS; i++) {
1050 free_irq(port->cfg->irqs[i], port);
1051 kfree(port->irqstr[i]);
1053 if (SCIx_IRQ_IS_MUXED(port)) {
1054 /* If there's only one IRQ, we're done. */
1060 static unsigned int sci_tx_empty(struct uart_port *port)
1062 unsigned short status = sci_in(port, SCxSR);
1063 unsigned short in_tx_fifo = sci_txfill(port);
1065 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1068 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1070 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
1071 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
1072 /* If you have signals for DTR and DCD, please implement here. */
1075 static unsigned int sci_get_mctrl(struct uart_port *port)
1077 /* This routine is used for getting signals of: DTR, DCD, DSR, RI,
1080 return TIOCM_DTR | TIOCM_RTS | TIOCM_CTS | TIOCM_DSR;
1083 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1084 static void sci_dma_tx_complete(void *arg)
1086 struct sci_port *s = arg;
1087 struct uart_port *port = &s->port;
1088 struct circ_buf *xmit = &port->state->xmit;
1089 unsigned long flags;
1091 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1093 spin_lock_irqsave(&port->lock, flags);
1095 xmit->tail += sg_dma_len(&s->sg_tx);
1096 xmit->tail &= UART_XMIT_SIZE - 1;
1098 port->icount.tx += sg_dma_len(&s->sg_tx);
1100 async_tx_ack(s->desc_tx);
1103 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1104 uart_write_wakeup(port);
1106 if (!uart_circ_empty(xmit)) {
1108 schedule_work(&s->work_tx);
1110 s->cookie_tx = -EINVAL;
1111 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1112 u16 ctrl = sci_in(port, SCSCR);
1113 sci_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1117 spin_unlock_irqrestore(&port->lock, flags);
1120 /* Locking: called with port lock held */
1121 static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty,
1124 struct uart_port *port = &s->port;
1125 int i, active, room;
1127 room = tty_buffer_request_room(tty, count);
1129 if (s->active_rx == s->cookie_rx[0]) {
1131 } else if (s->active_rx == s->cookie_rx[1]) {
1134 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1139 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
1144 for (i = 0; i < room; i++)
1145 tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
1148 port->icount.rx += room;
1153 static void sci_dma_rx_complete(void *arg)
1155 struct sci_port *s = arg;
1156 struct uart_port *port = &s->port;
1157 struct tty_struct *tty = port->state->port.tty;
1158 unsigned long flags;
1161 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
1163 spin_lock_irqsave(&port->lock, flags);
1165 count = sci_dma_rx_push(s, tty, s->buf_len_rx);
1167 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1169 spin_unlock_irqrestore(&port->lock, flags);
1172 tty_flip_buffer_push(tty);
1174 schedule_work(&s->work_rx);
1177 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1179 struct dma_chan *chan = s->chan_rx;
1180 struct uart_port *port = &s->port;
1183 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1184 dma_release_channel(chan);
1185 if (sg_dma_address(&s->sg_rx[0]))
1186 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1187 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
1192 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1194 struct dma_chan *chan = s->chan_tx;
1195 struct uart_port *port = &s->port;
1198 s->cookie_tx = -EINVAL;
1199 dma_release_channel(chan);
1204 static void sci_submit_rx(struct sci_port *s)
1206 struct dma_chan *chan = s->chan_rx;
1209 for (i = 0; i < 2; i++) {
1210 struct scatterlist *sg = &s->sg_rx[i];
1211 struct dma_async_tx_descriptor *desc;
1213 desc = chan->device->device_prep_slave_sg(chan,
1214 sg, 1, DMA_FROM_DEVICE, DMA_PREP_INTERRUPT);
1217 s->desc_rx[i] = desc;
1218 desc->callback = sci_dma_rx_complete;
1219 desc->callback_param = s;
1220 s->cookie_rx[i] = desc->tx_submit(desc);
1223 if (!desc || s->cookie_rx[i] < 0) {
1225 async_tx_ack(s->desc_rx[0]);
1226 s->cookie_rx[0] = -EINVAL;
1230 s->cookie_rx[i] = -EINVAL;
1232 dev_warn(s->port.dev,
1233 "failed to re-start DMA, using PIO\n");
1234 sci_rx_dma_release(s, true);
1237 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1238 s->cookie_rx[i], i);
1241 s->active_rx = s->cookie_rx[0];
1243 dma_async_issue_pending(chan);
1246 static void work_fn_rx(struct work_struct *work)
1248 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1249 struct uart_port *port = &s->port;
1250 struct dma_async_tx_descriptor *desc;
1253 if (s->active_rx == s->cookie_rx[0]) {
1255 } else if (s->active_rx == s->cookie_rx[1]) {
1258 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1261 desc = s->desc_rx[new];
1263 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1265 /* Handle incomplete DMA receive */
1266 struct tty_struct *tty = port->state->port.tty;
1267 struct dma_chan *chan = s->chan_rx;
1268 struct sh_desc *sh_desc = container_of(desc, struct sh_desc,
1270 unsigned long flags;
1273 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
1274 dev_dbg(port->dev, "Read %u bytes with cookie %d\n",
1275 sh_desc->partial, sh_desc->cookie);
1277 spin_lock_irqsave(&port->lock, flags);
1278 count = sci_dma_rx_push(s, tty, sh_desc->partial);
1279 spin_unlock_irqrestore(&port->lock, flags);
1282 tty_flip_buffer_push(tty);
1289 s->cookie_rx[new] = desc->tx_submit(desc);
1290 if (s->cookie_rx[new] < 0) {
1291 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1292 sci_rx_dma_release(s, true);
1296 s->active_rx = s->cookie_rx[!new];
1298 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
1299 s->cookie_rx[new], new, s->active_rx);
1302 static void work_fn_tx(struct work_struct *work)
1304 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1305 struct dma_async_tx_descriptor *desc;
1306 struct dma_chan *chan = s->chan_tx;
1307 struct uart_port *port = &s->port;
1308 struct circ_buf *xmit = &port->state->xmit;
1309 struct scatterlist *sg = &s->sg_tx;
1313 * Port xmit buffer is already mapped, and it is one page... Just adjust
1314 * offsets and lengths. Since it is a circular buffer, we have to
1315 * transmit till the end, and then the rest. Take the port lock to get a
1316 * consistent xmit buffer state.
1318 spin_lock_irq(&port->lock);
1319 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
1320 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
1322 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1323 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1324 spin_unlock_irq(&port->lock);
1326 BUG_ON(!sg_dma_len(sg));
1328 desc = chan->device->device_prep_slave_sg(chan,
1329 sg, s->sg_len_tx, DMA_TO_DEVICE,
1330 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1333 sci_tx_dma_release(s, true);
1337 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1339 spin_lock_irq(&port->lock);
1341 desc->callback = sci_dma_tx_complete;
1342 desc->callback_param = s;
1343 spin_unlock_irq(&port->lock);
1344 s->cookie_tx = desc->tx_submit(desc);
1345 if (s->cookie_tx < 0) {
1346 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1348 sci_tx_dma_release(s, true);
1352 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1353 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1355 dma_async_issue_pending(chan);
1359 static void sci_start_tx(struct uart_port *port)
1361 struct sci_port *s = to_sci_port(port);
1362 unsigned short ctrl;
1364 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1365 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1366 u16 new, scr = sci_in(port, SCSCR);
1370 new = scr & ~0x8000;
1372 sci_out(port, SCSCR, new);
1375 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
1378 schedule_work(&s->work_tx);
1382 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1383 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1384 ctrl = sci_in(port, SCSCR);
1385 sci_out(port, SCSCR, ctrl | SCSCR_TIE);
1389 static void sci_stop_tx(struct uart_port *port)
1391 unsigned short ctrl;
1393 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1394 ctrl = sci_in(port, SCSCR);
1396 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1401 sci_out(port, SCSCR, ctrl);
1404 static void sci_start_rx(struct uart_port *port)
1406 unsigned short ctrl;
1408 ctrl = sci_in(port, SCSCR) | port_rx_irq_mask(port);
1410 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1413 sci_out(port, SCSCR, ctrl);
1416 static void sci_stop_rx(struct uart_port *port)
1418 unsigned short ctrl;
1420 ctrl = sci_in(port, SCSCR);
1422 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1425 ctrl &= ~port_rx_irq_mask(port);
1427 sci_out(port, SCSCR, ctrl);
1430 static void sci_enable_ms(struct uart_port *port)
1432 /* Nothing here yet .. */
1435 static void sci_break_ctl(struct uart_port *port, int break_state)
1437 /* Nothing here yet .. */
1440 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1441 static bool filter(struct dma_chan *chan, void *slave)
1443 struct sh_dmae_slave *param = slave;
1445 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
1448 chan->private = param;
1452 static void rx_timer_fn(unsigned long arg)
1454 struct sci_port *s = (struct sci_port *)arg;
1455 struct uart_port *port = &s->port;
1456 u16 scr = sci_in(port, SCSCR);
1458 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1460 enable_irq(s->cfg->irqs[1]);
1462 sci_out(port, SCSCR, scr | SCSCR_RIE);
1463 dev_dbg(port->dev, "DMA Rx timed out\n");
1464 schedule_work(&s->work_rx);
1467 static void sci_request_dma(struct uart_port *port)
1469 struct sci_port *s = to_sci_port(port);
1470 struct sh_dmae_slave *param;
1471 struct dma_chan *chan;
1472 dma_cap_mask_t mask;
1475 dev_dbg(port->dev, "%s: port %d\n", __func__,
1478 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
1482 dma_cap_set(DMA_SLAVE, mask);
1484 param = &s->param_tx;
1486 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1487 param->slave_id = s->cfg->dma_slave_tx;
1489 s->cookie_tx = -EINVAL;
1490 chan = dma_request_channel(mask, filter, param);
1491 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1494 sg_init_table(&s->sg_tx, 1);
1495 /* UART circular tx buffer is an aligned page. */
1496 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
1497 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1498 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK);
1499 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1501 sci_tx_dma_release(s, false);
1503 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
1504 sg_dma_len(&s->sg_tx),
1505 port->state->xmit.buf, sg_dma_address(&s->sg_tx));
1507 s->sg_len_tx = nent;
1509 INIT_WORK(&s->work_tx, work_fn_tx);
1512 param = &s->param_rx;
1514 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1515 param->slave_id = s->cfg->dma_slave_rx;
1517 chan = dma_request_channel(mask, filter, param);
1518 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1526 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1527 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1528 &dma[0], GFP_KERNEL);
1532 "failed to allocate dma buffer, using PIO\n");
1533 sci_rx_dma_release(s, true);
1537 buf[1] = buf[0] + s->buf_len_rx;
1538 dma[1] = dma[0] + s->buf_len_rx;
1540 for (i = 0; i < 2; i++) {
1541 struct scatterlist *sg = &s->sg_rx[i];
1543 sg_init_table(sg, 1);
1544 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1545 (int)buf[i] & ~PAGE_MASK);
1546 sg_dma_address(sg) = dma[i];
1549 INIT_WORK(&s->work_rx, work_fn_rx);
1550 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1556 static void sci_free_dma(struct uart_port *port)
1558 struct sci_port *s = to_sci_port(port);
1561 sci_tx_dma_release(s, false);
1563 sci_rx_dma_release(s, false);
1566 static inline void sci_request_dma(struct uart_port *port)
1570 static inline void sci_free_dma(struct uart_port *port)
1575 static int sci_startup(struct uart_port *port)
1577 struct sci_port *s = to_sci_port(port);
1580 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1584 sci_request_dma(port);
1586 ret = sci_request_irq(s);
1587 if (unlikely(ret < 0)) {
1598 static void sci_shutdown(struct uart_port *port)
1600 struct sci_port *s = to_sci_port(port);
1602 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1610 sci_port_disable(s);
1613 static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
1618 return ((freq + 16 * bps) / (16 * bps) - 1);
1620 return ((freq + 16 * bps) / (32 * bps) - 1);
1622 return (((freq * 2) + 16 * bps) / (16 * bps) - 1);
1624 return (((freq * 2) + 16 * bps) / (32 * bps) - 1);
1626 return (((freq * 1000 / 32) / bps) - 1);
1629 /* Warn, but use a safe default */
1632 return ((freq + 16 * bps) / (32 * bps) - 1);
1635 static void sci_reset(struct uart_port *port)
1637 unsigned int status;
1640 status = sci_in(port, SCxSR);
1641 } while (!(status & SCxSR_TEND(port)));
1643 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1645 if (port->type != PORT_SCI)
1646 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1649 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1650 struct ktermios *old)
1652 struct sci_port *s = to_sci_port(port);
1653 unsigned int baud, smr_val, max_baud;
1658 * earlyprintk comes here early on with port->uartclk set to zero.
1659 * the clock framework is not up and running at this point so here
1660 * we assume that 115200 is the maximum baud rate. please note that
1661 * the baud rate is not programmed during earlyprintk - it is assumed
1662 * that the previous boot loader has enabled required clocks and
1663 * setup the baud rate generator hardware for us already.
1665 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1667 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1668 if (likely(baud && port->uartclk))
1669 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, port->uartclk);
1675 smr_val = sci_in(port, SCSMR) & 3;
1677 if ((termios->c_cflag & CSIZE) == CS7)
1679 if (termios->c_cflag & PARENB)
1681 if (termios->c_cflag & PARODD)
1683 if (termios->c_cflag & CSTOPB)
1686 uart_update_timeout(port, termios->c_cflag, baud);
1688 sci_out(port, SCSMR, smr_val);
1690 dev_dbg(port->dev, "%s: SMR %x, t %x, SCSCR %x\n", __func__, smr_val, t,
1695 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1698 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
1700 sci_out(port, SCBRR, t);
1701 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1704 sci_init_pins(port, termios->c_cflag);
1705 sci_out(port, SCFCR, scfcr | ((termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0));
1707 sci_out(port, SCSCR, s->cfg->scscr);
1709 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1711 * Calculate delay for 1.5 DMA buffers: see
1712 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1713 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1714 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1715 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1716 * sizes), but it has been found out experimentally, that this is not
1717 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1718 * as a minimum seem to work perfectly.
1721 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1724 "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1725 s->rx_timeout * 1000 / HZ, port->timeout);
1726 if (s->rx_timeout < msecs_to_jiffies(20))
1727 s->rx_timeout = msecs_to_jiffies(20);
1731 if ((termios->c_cflag & CREAD) != 0)
1734 sci_port_disable(s);
1737 static const char *sci_type(struct uart_port *port)
1739 switch (port->type) {
1755 static inline unsigned long sci_port_size(struct uart_port *port)
1758 * Pick an arbitrary size that encapsulates all of the base
1759 * registers by default. This can be optimized later, or derived
1760 * from platform resource data at such a time that ports begin to
1761 * behave more erratically.
1766 static int sci_remap_port(struct uart_port *port)
1768 unsigned long size = sci_port_size(port);
1771 * Nothing to do if there's already an established membase.
1776 if (port->flags & UPF_IOREMAP) {
1777 port->membase = ioremap_nocache(port->mapbase, size);
1778 if (unlikely(!port->membase)) {
1779 dev_err(port->dev, "can't remap port#%d\n", port->line);
1784 * For the simple (and majority of) cases where we don't
1785 * need to do any remapping, just cast the cookie
1788 port->membase = (void __iomem *)port->mapbase;
1794 static void sci_release_port(struct uart_port *port)
1796 if (port->flags & UPF_IOREMAP) {
1797 iounmap(port->membase);
1798 port->membase = NULL;
1801 release_mem_region(port->mapbase, sci_port_size(port));
1804 static int sci_request_port(struct uart_port *port)
1806 unsigned long size = sci_port_size(port);
1807 struct resource *res;
1810 res = request_mem_region(port->mapbase, size, dev_name(port->dev));
1811 if (unlikely(res == NULL))
1814 ret = sci_remap_port(port);
1815 if (unlikely(ret != 0)) {
1816 release_resource(res);
1823 static void sci_config_port(struct uart_port *port, int flags)
1825 if (flags & UART_CONFIG_TYPE) {
1826 struct sci_port *sport = to_sci_port(port);
1828 port->type = sport->cfg->type;
1829 sci_request_port(port);
1833 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1835 struct sci_port *s = to_sci_port(port);
1837 if (ser->irq != s->cfg->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1839 if (ser->baud_base < 2400)
1840 /* No paper tape reader for Mitch.. */
1846 static struct uart_ops sci_uart_ops = {
1847 .tx_empty = sci_tx_empty,
1848 .set_mctrl = sci_set_mctrl,
1849 .get_mctrl = sci_get_mctrl,
1850 .start_tx = sci_start_tx,
1851 .stop_tx = sci_stop_tx,
1852 .stop_rx = sci_stop_rx,
1853 .enable_ms = sci_enable_ms,
1854 .break_ctl = sci_break_ctl,
1855 .startup = sci_startup,
1856 .shutdown = sci_shutdown,
1857 .set_termios = sci_set_termios,
1859 .release_port = sci_release_port,
1860 .request_port = sci_request_port,
1861 .config_port = sci_config_port,
1862 .verify_port = sci_verify_port,
1863 #ifdef CONFIG_CONSOLE_POLL
1864 .poll_get_char = sci_poll_get_char,
1865 .poll_put_char = sci_poll_put_char,
1869 static int __devinit sci_init_single(struct platform_device *dev,
1870 struct sci_port *sci_port,
1872 struct plat_sci_port *p)
1874 struct uart_port *port = &sci_port->port;
1877 port->ops = &sci_uart_ops;
1878 port->iotype = UPIO_MEM;
1883 port->fifosize = 256;
1886 port->fifosize = 64;
1889 port->fifosize = 16;
1896 if (p->regtype == SCIx_PROBE_REGTYPE) {
1897 ret = sci_probe_regmap(p);
1903 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
1904 if (IS_ERR(sci_port->iclk)) {
1905 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
1906 if (IS_ERR(sci_port->iclk)) {
1907 dev_err(&dev->dev, "can't get iclk\n");
1908 return PTR_ERR(sci_port->iclk);
1913 * The function clock is optional, ignore it if we can't
1916 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
1917 if (IS_ERR(sci_port->fclk))
1918 sci_port->fclk = NULL;
1920 port->dev = &dev->dev;
1922 pm_runtime_irq_safe(&dev->dev);
1923 pm_runtime_enable(&dev->dev);
1926 sci_port->break_timer.data = (unsigned long)sci_port;
1927 sci_port->break_timer.function = sci_break_timer;
1928 init_timer(&sci_port->break_timer);
1931 * Establish some sensible defaults for the error detection.
1934 p->error_mask = (p->type == PORT_SCI) ?
1935 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
1938 * Establish sensible defaults for the overrun detection, unless
1939 * the part has explicitly disabled support for it.
1941 if (p->overrun_bit != SCIx_NOT_SUPPORTED) {
1942 if (p->type == PORT_SCI)
1944 else if (p->scbrr_algo_id == SCBRR_ALGO_4)
1950 * Make the error mask inclusive of overrun detection, if
1953 p->error_mask |= (1 << p->overrun_bit);
1958 port->mapbase = p->mapbase;
1959 port->type = p->type;
1960 port->flags = p->flags;
1961 port->regshift = p->regshift;
1964 * The UART port needs an IRQ value, so we peg this to the RX IRQ
1965 * for the multi-IRQ ports, which is where we are primarily
1966 * concerned with the shutdown path synchronization.
1968 * For the muxed case there's nothing more to do.
1970 port->irq = p->irqs[SCIx_RXI_IRQ];
1973 port->serial_in = sci_serial_in;
1974 port->serial_out = sci_serial_out;
1976 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
1977 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
1978 p->dma_slave_tx, p->dma_slave_rx);
1983 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1984 static void serial_console_putchar(struct uart_port *port, int ch)
1986 sci_poll_put_char(port, ch);
1990 * Print a string to the serial port trying not to disturb
1991 * any possible real use of the port...
1993 static void serial_console_write(struct console *co, const char *s,
1996 struct sci_port *sci_port = &sci_ports[co->index];
1997 struct uart_port *port = &sci_port->port;
1998 unsigned short bits;
2000 sci_port_enable(sci_port);
2002 uart_console_write(port, s, count, serial_console_putchar);
2004 /* wait until fifo is empty and last bit has been transmitted */
2005 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2006 while ((sci_in(port, SCxSR) & bits) != bits)
2009 sci_port_disable(sci_port);
2012 static int __devinit serial_console_setup(struct console *co, char *options)
2014 struct sci_port *sci_port;
2015 struct uart_port *port;
2023 * Refuse to handle any bogus ports.
2025 if (co->index < 0 || co->index >= SCI_NPORTS)
2028 sci_port = &sci_ports[co->index];
2029 port = &sci_port->port;
2032 * Refuse to handle uninitialized ports.
2037 ret = sci_remap_port(port);
2038 if (unlikely(ret != 0))
2041 sci_port_enable(sci_port);
2044 uart_parse_options(options, &baud, &parity, &bits, &flow);
2046 sci_port_disable(sci_port);
2048 return uart_set_options(port, co, baud, parity, bits, flow);
2051 static struct console serial_console = {
2053 .device = uart_console_device,
2054 .write = serial_console_write,
2055 .setup = serial_console_setup,
2056 .flags = CON_PRINTBUFFER,
2058 .data = &sci_uart_driver,
2061 static struct console early_serial_console = {
2062 .name = "early_ttySC",
2063 .write = serial_console_write,
2064 .flags = CON_PRINTBUFFER,
2068 static char early_serial_buf[32];
2070 static int __devinit sci_probe_earlyprintk(struct platform_device *pdev)
2072 struct plat_sci_port *cfg = pdev->dev.platform_data;
2074 if (early_serial_console.data)
2077 early_serial_console.index = pdev->id;
2079 sci_init_single(NULL, &sci_ports[pdev->id], pdev->id, cfg);
2081 serial_console_setup(&early_serial_console, early_serial_buf);
2083 if (!strstr(early_serial_buf, "keep"))
2084 early_serial_console.flags |= CON_BOOT;
2086 register_console(&early_serial_console);
2090 #define uart_console(port) ((port)->cons->index == (port)->line)
2092 static int sci_runtime_suspend(struct device *dev)
2094 struct sci_port *sci_port = dev_get_drvdata(dev);
2095 struct uart_port *port = &sci_port->port;
2097 if (uart_console(port)) {
2098 sci_port->saved_smr = sci_in(port, SCSMR);
2099 sci_port->saved_brr = sci_in(port, SCBRR);
2100 sci_port->saved_fcr = sci_in(port, SCFCR);
2105 static int sci_runtime_resume(struct device *dev)
2107 struct sci_port *sci_port = dev_get_drvdata(dev);
2108 struct uart_port *port = &sci_port->port;
2110 if (uart_console(port)) {
2112 sci_out(port, SCSMR, sci_port->saved_smr);
2113 sci_out(port, SCBRR, sci_port->saved_brr);
2114 sci_out(port, SCFCR, sci_port->saved_fcr);
2115 sci_out(port, SCSCR, sci_port->cfg->scscr);
2120 #define SCI_CONSOLE (&serial_console)
2123 static inline int __devinit sci_probe_earlyprintk(struct platform_device *pdev)
2128 #define SCI_CONSOLE NULL
2129 #define sci_runtime_suspend NULL
2130 #define sci_runtime_resume NULL
2132 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2134 static char banner[] __initdata =
2135 KERN_INFO "SuperH SCI(F) driver initialized\n";
2137 static struct uart_driver sci_uart_driver = {
2138 .owner = THIS_MODULE,
2139 .driver_name = "sci",
2140 .dev_name = "ttySC",
2142 .minor = SCI_MINOR_START,
2144 .cons = SCI_CONSOLE,
2147 static int sci_remove(struct platform_device *dev)
2149 struct sci_port *port = platform_get_drvdata(dev);
2151 uart_remove_one_port(&sci_uart_driver, &port->port);
2153 clk_put(port->iclk);
2154 clk_put(port->fclk);
2156 pm_runtime_disable(&dev->dev);
2160 static int __devinit sci_probe_single(struct platform_device *dev,
2162 struct plat_sci_port *p,
2163 struct sci_port *sciport)
2168 if (unlikely(index >= SCI_NPORTS)) {
2169 dev_notice(&dev->dev, "Attempting to register port "
2170 "%d when only %d are available.\n",
2171 index+1, SCI_NPORTS);
2172 dev_notice(&dev->dev, "Consider bumping "
2173 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2177 ret = sci_init_single(dev, sciport, index, p);
2181 return uart_add_one_port(&sci_uart_driver, &sciport->port);
2184 static int __devinit sci_probe(struct platform_device *dev)
2186 struct plat_sci_port *p = dev->dev.platform_data;
2187 struct sci_port *sp = &sci_ports[dev->id];
2191 * If we've come here via earlyprintk initialization, head off to
2192 * the special early probe. We don't have sufficient device state
2193 * to make it beyond this yet.
2195 if (is_early_platform_device(dev))
2196 return sci_probe_earlyprintk(dev);
2198 platform_set_drvdata(dev, sp);
2200 ret = sci_probe_single(dev, dev->id, p, sp);
2204 #ifdef CONFIG_SH_STANDARD_BIOS
2205 sh_bios_gdb_detach();
2215 static int sci_suspend(struct device *dev)
2217 struct sci_port *sport = dev_get_drvdata(dev);
2220 uart_suspend_port(&sci_uart_driver, &sport->port);
2225 static int sci_resume(struct device *dev)
2227 struct sci_port *sport = dev_get_drvdata(dev);
2230 uart_resume_port(&sci_uart_driver, &sport->port);
2235 static const struct dev_pm_ops sci_dev_pm_ops = {
2236 .runtime_suspend = sci_runtime_suspend,
2237 .runtime_resume = sci_runtime_resume,
2238 .suspend = sci_suspend,
2239 .resume = sci_resume,
2242 static struct platform_driver sci_driver = {
2244 .remove = sci_remove,
2247 .owner = THIS_MODULE,
2248 .pm = &sci_dev_pm_ops,
2252 static int __init sci_init(void)
2258 ret = uart_register_driver(&sci_uart_driver);
2259 if (likely(ret == 0)) {
2260 ret = platform_driver_register(&sci_driver);
2262 uart_unregister_driver(&sci_uart_driver);
2268 static void __exit sci_exit(void)
2270 platform_driver_unregister(&sci_driver);
2271 uart_unregister_driver(&sci_uart_driver);
2274 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2275 early_platform_init_buffer("earlyprintk", &sci_driver,
2276 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2278 module_init(sci_init);
2279 module_exit(sci_exit);
2281 MODULE_LICENSE("GPL");
2282 MODULE_ALIAS("platform:sh-sci");
2283 MODULE_AUTHOR("Paul Mundt");
2284 MODULE_DESCRIPTION("SuperH SCI(F) serial driver");