drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/kernel.h>
  21 #include <linux/debugfs.h>
  22 #include <linux/seq_file.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/delay.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/timer.h>
  28 #include <linux/clk.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/mmc/core.h>
  31 #include <linux/mmc/mmc.h>
  32 #include <linux/io.h>
  33 #include <linux/semaphore.h>
  34 #include <linux/gpio.h>
  35 #include <linux/regulator/consumer.h>
  36 #include <linux/pm_runtime.h>
  37 #include <plat/dma.h>
  38 #include <mach/hardware.h>
  39 #include <plat/board.h>
  40 #include <plat/mmc.h>
  41 #include <plat/cpu.h>
  42
  43 /* OMAP HSMMC Host Controller Registers */
  44 #define OMAP_HSMMC_SYSCONFIG    0x0010
  45 #define OMAP_HSMMC_SYSSTATUS    0x0014
  46 #define OMAP_HSMMC_CON          0x002C
  47 #define OMAP_HSMMC_BLK          0x0104
  48 #define OMAP_HSMMC_ARG          0x0108
  49 #define OMAP_HSMMC_CMD          0x010C
  50 #define OMAP_HSMMC_RSP10        0x0110
  51 #define OMAP_HSMMC_RSP32        0x0114
  52 #define OMAP_HSMMC_RSP54        0x0118
  53 #define OMAP_HSMMC_RSP76        0x011C
  54 #define OMAP_HSMMC_DATA         0x0120
  55 #define OMAP_HSMMC_HCTL         0x0128
  56 #define OMAP_HSMMC_SYSCTL       0x012C
  57 #define OMAP_HSMMC_STAT         0x0130
  58 #define OMAP_HSMMC_IE           0x0134
  59 #define OMAP_HSMMC_ISE          0x0138
  60 #define OMAP_HSMMC_CAPA         0x0140
  61
  62 #define VS18                    (1 << 26)
  63 #define VS30                    (1 << 25)
  64 #define SDVS18                  (0x5 << 9)
  65 #define SDVS30                  (0x6 << 9)
  66 #define SDVS33                  (0x7 << 9)
  67 #define SDVS_MASK               0x00000E00
  68 #define SDVSCLR                 0xFFFFF1FF
  69 #define SDVSDET                 0x00000400
  70 #define AUTOIDLE                0x1
  71 #define SDBP                    (1 << 8)
  72 #define DTO                     0xe
  73 #define ICE                     0x1
  74 #define ICS                     0x2
  75 #define CEN                     (1 << 2)
  76 #define CLKD_MASK               0x0000FFC0
  77 #define CLKD_SHIFT              6
  78 #define DTO_MASK                0x000F0000
  79 #define DTO_SHIFT               16
  80 #define INT_EN_MASK             0x307F0033
  81 #define BWR_ENABLE              (1 << 4)
  82 #define BRR_ENABLE              (1 << 5)
  83 #define DTO_ENABLE              (1 << 20)
  84 #define INIT_STREAM             (1 << 1)
  85 #define DP_SELECT               (1 << 21)
  86 #define DDIR                    (1 << 4)
  87 #define DMA_EN                  0x1
  88 #define MSBS                    (1 << 5)
  89 #define BCE                     (1 << 1)
  90 #define FOUR_BIT                (1 << 1)
  91 #define DW8                     (1 << 5)
  92 #define CC                      0x1
  93 #define TC                      0x02
  94 #define OD                      0x1
  95 #define ERR                     (1 << 15)
  96 #define CMD_TIMEOUT             (1 << 16)
  97 #define DATA_TIMEOUT            (1 << 20)
  98 #define CMD_CRC                 (1 << 17)
  99 #define DATA_CRC                (1 << 21)
 100 #define CARD_ERR                (1 << 28)
 101 #define STAT_CLEAR              0xFFFFFFFF
 102 #define INIT_STREAM_CMD         0x00000000
 103 #define DUAL_VOLT_OCR_BIT       7
 104 #define SRC                     (1 << 25)
 105 #define SRD                     (1 << 26)
 106 #define SOFTRESET               (1 << 1)
 107 #define RESETDONE               (1 << 0)
 108
 109 /*
 110  * FIXME: Most likely all the data using these _DEVID defines should come
 111  * from the platform_data, or implemented in controller and slot specific
 112  * functions.
 113  */
 114 #define OMAP_MMC1_DEVID         0
 115 #define OMAP_MMC2_DEVID         1
 116 #define OMAP_MMC3_DEVID         2
 117 #define OMAP_MMC4_DEVID         3
 118 #define OMAP_MMC5_DEVID         4
 119
 120 #define MMC_AUTOSUSPEND_DELAY   100
 121 #define MMC_TIMEOUT_MS          20
 122 #define OMAP_MMC_MASTER_CLOCK   96000000
 123 #define OMAP_MMC_MIN_CLOCK      400000
 124 #define OMAP_MMC_MAX_CLOCK      52000000
 125 #define DRIVER_NAME             "omap_hsmmc"
 126
 127 /*
 128  * One controller can have multiple slots, like on some omap boards using
 129  * omap.c controller driver. Luckily this is not currently done on any known
 130  * omap_hsmmc.c device.
 131  */
 132 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 133
 134 /*
 135  * MMC Host controller read/write API's
 136  */
 137 #define OMAP_HSMMC_READ(base, reg)      \
 138         __raw_readl((base) + OMAP_HSMMC_##reg)
 139
 140 #define OMAP_HSMMC_WRITE(base, reg, val) \
 141         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 142
 143 struct omap_hsmmc_next {
 144         unsigned int    dma_len;
 145         s32             cookie;
 146 };
 147
 148 struct omap_hsmmc_host {
 149         struct  device          *dev;
 150         struct  mmc_host        *mmc;
 151         struct  mmc_request     *mrq;
 152         struct  mmc_command     *cmd;
 153         struct  mmc_data        *data;
 154         struct  clk             *fclk;
 155         struct  clk             *dbclk;
 156         /*
 157          * vcc == configured supply
 158          * vcc_aux == optional
 159          *   -  MMC1, supply for DAT4..DAT7
 160          *   -  MMC2/MMC2, external level shifter voltage supply, for
 161          *      chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
 162          */
 163         struct  regulator       *vcc;
 164         struct  regulator       *vcc_aux;
 165         void    __iomem         *base;
 166         resource_size_t         mapbase;
 167         spinlock_t              irq_lock; /* Prevent races with irq handler */
 168         unsigned int            id;
 169         unsigned int            dma_len;
 170         unsigned int            dma_sg_idx;
 171         unsigned char           bus_mode;
 172         unsigned char           power_mode;
 173         u32                     *buffer;
 174         u32                     bytesleft;
 175         int                     suspended;
 176         int                     irq;
 177         int                     use_dma, dma_ch;
 178         int                     dma_line_tx, dma_line_rx;
 179         int                     slot_id;
 180         int                     got_dbclk;
 181         int                     response_busy;
 182         int                     context_loss;
 183         int                     dpm_state;
 184         int                     vdd;
 185         int                     protect_card;
 186         int                     reqs_blocked;
 187         int                     use_reg;
 188         int                     req_in_progress;
 189         struct omap_hsmmc_next  next_data;
 190
 191         struct  omap_mmc_platform_data  *pdata;
 192 };
 193
 194 static int omap_hsmmc_card_detect(struct device *dev, int slot)
 195 {
 196         struct omap_mmc_platform_data *mmc = dev->platform_data;
 197
 198         /* NOTE: assumes card detect signal is active-low */
 199         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
 200 }
 201
 202 static int omap_hsmmc_get_wp(struct device *dev, int slot)
 203 {
 204         struct omap_mmc_platform_data *mmc = dev->platform_data;
 205
 206         /* NOTE: assumes write protect signal is active-high */
 207         return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
 208 }
 209
 210 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
 211 {
 212         struct omap_mmc_platform_data *mmc = dev->platform_data;
 213
 214         /* NOTE: assumes card detect signal is active-low */
 215         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
 216 }
 217
 218 #ifdef CONFIG_PM
 219
 220 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
 221 {
 222         struct omap_mmc_platform_data *mmc = dev->platform_data;
 223
 224         disable_irq(mmc->slots[0].card_detect_irq);
 225         return 0;
 226 }
 227
 228 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
 229 {
 230         struct omap_mmc_platform_data *mmc = dev->platform_data;
 231
 232         enable_irq(mmc->slots[0].card_detect_irq);
 233         return 0;
 234 }
 235
 236 #else
 237
 238 #define omap_hsmmc_suspend_cdirq        NULL
 239 #define omap_hsmmc_resume_cdirq         NULL
 240
 241 #endif
 242
 243 #ifdef CONFIG_REGULATOR
 244
 245 static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
 246                                   int vdd)
 247 {
 248         struct omap_hsmmc_host *host =
 249                 platform_get_drvdata(to_platform_device(dev));
 250         int ret;
 251
 252         if (mmc_slot(host).before_set_reg)
 253                 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
 254
 255         if (power_on)
 256                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
 257         else
 258                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
 259
 260         if (mmc_slot(host).after_set_reg)
 261                 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
 262
 263         return ret;
 264 }
 265
 266 static int omap_hsmmc_235_set_power(struct device *dev, int slot, int power_on,
 267                                    int vdd)
 268 {
 269         struct omap_hsmmc_host *host =
 270                 platform_get_drvdata(to_platform_device(dev));
 271         int ret = 0;
 272
 273         /*
 274          * If we don't see a Vcc regulator, assume it's a fixed
 275          * voltage always-on regulator.
 276          */
 277         if (!host->vcc)
 278                 return 0;
 279
 280         if (mmc_slot(host).before_set_reg)
 281                 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
 282
 283         /*
 284          * Assume Vcc regulator is used only to power the card ... OMAP
 285          * VDDS is used to power the pins, optionally with a transceiver to
 286          * support cards using voltages other than VDDS (1.8V nominal).  When a
 287          * transceiver is used, DAT3..7 are muxed as transceiver control pins.
 288          *
 289          * In some cases this regulator won't support enable/disable;
 290          * e.g. it's a fixed rail for a WLAN chip.
 291          *
 292          * In other cases vcc_aux switches interface power.  Example, for
 293          * eMMC cards it represents VccQ.  Sometimes transceivers or SDIO
 294          * chips/cards need an interface voltage rail too.
 295          */
 296         if (power_on) {
 297                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
 298                 /* Enable interface voltage rail, if needed */
 299                 if (ret == 0 && host->vcc_aux) {
 300                         ret = regulator_enable(host->vcc_aux);
 301                         if (ret < 0)
 302                                 ret = mmc_regulator_set_ocr(host->mmc,
 303                                                         host->vcc, 0);
 304                 }
 305         } else {
 306                 /* Shut down the rail */
 307                 if (host->vcc_aux)
 308                         ret = regulator_disable(host->vcc_aux);
 309                 if (!ret) {
 310                         /* Then proceed to shut down the local regulator */
 311                         ret = mmc_regulator_set_ocr(host->mmc,
 312                                                 host->vcc, 0);
 313                 }
 314         }
 315
 316         if (mmc_slot(host).after_set_reg)
 317                 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
 318
 319         return ret;
 320 }
 321
 322 static int omap_hsmmc_4_set_power(struct device *dev, int slot, int power_on,
 323                                         int vdd)
 324 {
 325         return 0;
 326 }
 327
 328 static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
 329                                   int vdd, int cardsleep)
 330 {
 331         struct omap_hsmmc_host *host =
 332                 platform_get_drvdata(to_platform_device(dev));
 333         int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
 334
 335         return regulator_set_mode(host->vcc, mode);
 336 }
 337
 338 static int omap_hsmmc_235_set_sleep(struct device *dev, int slot, int sleep,
 339                                    int vdd, int cardsleep)
 340 {
 341         struct omap_hsmmc_host *host =
 342                 platform_get_drvdata(to_platform_device(dev));
 343         int err, mode;
 344
 345         /*
 346          * If we don't see a Vcc regulator, assume it's a fixed
 347          * voltage always-on regulator.
 348          */
 349         if (!host->vcc)
 350                 return 0;
 351
 352         mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
 353
 354         if (!host->vcc_aux)
 355                 return regulator_set_mode(host->vcc, mode);
 356
 357         if (cardsleep) {
 358                 /* VCC can be turned off if card is asleep */
 359                 if (sleep)
 360                         err = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
 361                 else
 362                         err = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
 363         } else
 364                 err = regulator_set_mode(host->vcc, mode);
 365         if (err)
 366                 return err;
 367
 368         if (!mmc_slot(host).vcc_aux_disable_is_sleep)
 369                 return regulator_set_mode(host->vcc_aux, mode);
 370
 371         if (sleep)
 372                 return regulator_disable(host->vcc_aux);
 373         else
 374                 return regulator_enable(host->vcc_aux);
 375 }
 376
 377 static int omap_hsmmc_4_set_sleep(struct device *dev, int slot, int sleep,
 378                                         int vdd, int cardsleep)
 379 {
 380         return 0;
 381 }
 382
 383 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 384 {
 385         struct regulator *reg;
 386         int ret = 0;
 387         int ocr_value = 0;
 388
 389         switch (host->id) {
 390         case OMAP_MMC1_DEVID:
 391                 /* On-chip level shifting via PBIAS0/PBIAS1 */
 392                 mmc_slot(host).set_power = omap_hsmmc_1_set_power;
 393                 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep;
 394                 break;
 395         case OMAP_MMC2_DEVID:
 396         case OMAP_MMC3_DEVID:
 397         case OMAP_MMC5_DEVID:
 398                 /* Off-chip level shifting, or none */
 399                 mmc_slot(host).set_power = omap_hsmmc_235_set_power;
 400                 mmc_slot(host).set_sleep = omap_hsmmc_235_set_sleep;
 401                 break;
 402         case OMAP_MMC4_DEVID:
 403                 mmc_slot(host).set_power = omap_hsmmc_4_set_power;
 404                 mmc_slot(host).set_sleep = omap_hsmmc_4_set_sleep;
 405         default:
 406                 pr_err("MMC%d configuration not supported!\n", host->id);
 407                 return -EINVAL;
 408         }
 409
 410         reg = regulator_get(host->dev, "vmmc");
 411         if (IS_ERR(reg)) {
 412                 dev_dbg(host->dev, "vmmc regulator missing\n");
 413                 /*
 414                 * HACK: until fixed.c regulator is usable,
 415                 * we don't require a main regulator
 416                 * for MMC2 or MMC3
 417                 */
 418                 if (host->id == OMAP_MMC1_DEVID) {
 419                         ret = PTR_ERR(reg);
 420                         goto err;
 421                 }
 422         } else {
 423                 host->vcc = reg;
 424                 ocr_value = mmc_regulator_get_ocrmask(reg);
 425                 if (!mmc_slot(host).ocr_mask) {
 426                         mmc_slot(host).ocr_mask = ocr_value;
 427                 } else {
 428                         if (!(mmc_slot(host).ocr_mask & ocr_value)) {
 429                                 pr_err("MMC%d ocrmask %x is not supported\n",
 430                                         host->id, mmc_slot(host).ocr_mask);
 431                                 mmc_slot(host).ocr_mask = 0;
 432                                 return -EINVAL;
 433                         }
 434                 }
 435
 436                 /* Allow an aux regulator */
 437                 reg = regulator_get(host->dev, "vmmc_aux");
 438                 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
 439
 440                 /* For eMMC do not power off when not in sleep state */
 441                 if (mmc_slot(host).no_regulator_off_init)
 442                         return 0;
 443                 /*
 444                 * UGLY HACK:  workaround regulator framework bugs.
 445                 * When the bootloader leaves a supply active, it's
 446                 * initialized with zero usecount ... and we can't
 447                 * disable it without first enabling it.  Until the
 448                 * framework is fixed, we need a workaround like this
 449                 * (which is safe for MMC, but not in general).
 450                 */
 451                 if (regulator_is_enabled(host->vcc) > 0 ||
 452                     (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
 453                         int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
 454
 455                         mmc_slot(host).set_power(host->dev, host->slot_id,
 456                                                  1, vdd);
 457                         mmc_slot(host).set_power(host->dev, host->slot_id,
 458                                                  0, 0);
 459                 }
 460         }
 461
 462         return 0;
 463
 464 err:
 465         mmc_slot(host).set_power = NULL;
 466         mmc_slot(host).set_sleep = NULL;
 467         return ret;
 468 }
 469
 470 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 471 {
 472         regulator_put(host->vcc);
 473         regulator_put(host->vcc_aux);
 474         mmc_slot(host).set_power = NULL;
 475         mmc_slot(host).set_sleep = NULL;
 476 }
 477
 478 static inline int omap_hsmmc_have_reg(void)
 479 {
 480         return 1;
 481 }
 482
 483 #else
 484
 485 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 486 {
 487         return -EINVAL;
 488 }
 489
 490 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 491 {
 492 }
 493
 494 static inline int omap_hsmmc_have_reg(void)
 495 {
 496         return 0;
 497 }
 498
 499 #endif
 500
 501 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
 502 {
 503         int ret;
 504
 505         if (gpio_is_valid(pdata->slots[0].switch_pin)) {
 506                 if (pdata->slots[0].cover)
 507                         pdata->slots[0].get_cover_state =
 508                                         omap_hsmmc_get_cover_state;
 509                 else
 510                         pdata->slots[0].card_detect = omap_hsmmc_card_detect;
 511                 pdata->slots[0].card_detect_irq =
 512                                 gpio_to_irq(pdata->slots[0].switch_pin);
 513                 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
 514                 if (ret)
 515                         return ret;
 516                 ret = gpio_direction_input(pdata->slots[0].switch_pin);
 517                 if (ret)
 518                         goto err_free_sp;
 519         } else
 520                 pdata->slots[0].switch_pin = -EINVAL;
 521
 522         if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
 523                 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
 524                 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
 525                 if (ret)
 526                         goto err_free_cd;
 527                 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
 528                 if (ret)
 529                         goto err_free_wp;
 530         } else
 531                 pdata->slots[0].gpio_wp = -EINVAL;
 532
 533         return 0;
 534
 535 err_free_wp:
 536         gpio_free(pdata->slots[0].gpio_wp);
 537 err_free_cd:
 538         if (gpio_is_valid(pdata->slots[0].switch_pin))
 539 err_free_sp:
 540                 gpio_free(pdata->slots[0].switch_pin);
 541         return ret;
 542 }
 543
 544 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
 545 {
 546         if (gpio_is_valid(pdata->slots[0].gpio_wp))
 547                 gpio_free(pdata->slots[0].gpio_wp);
 548         if (gpio_is_valid(pdata->slots[0].switch_pin))
 549                 gpio_free(pdata->slots[0].switch_pin);
 550 }
 551
 552 /*
 553  * Start clock to the card
 554  */
 555 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
 556 {
 557         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 558                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 559 }
 560
 561 /*
 562  * Stop clock to the card
 563  */
 564 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
 565 {
 566         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 567                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 568         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 569                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 570 }
 571
 572 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
 573                                   struct mmc_command *cmd)
 574 {
 575         unsigned int irq_mask;
 576
 577         if (host->use_dma)
 578                 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
 579         else
 580                 irq_mask = INT_EN_MASK;
 581
 582         /* Disable timeout for erases */
 583         if (cmd->opcode == MMC_ERASE)
 584                 irq_mask &= ~DTO_ENABLE;
 585
 586         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 587         OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
 588         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
 589 }
 590
 591 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
 592 {
 593         OMAP_HSMMC_WRITE(host->base, ISE, 0);
 594         OMAP_HSMMC_WRITE(host->base, IE, 0);
 595         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 596 }
 597
 598 /* Calculate divisor for the given clock frequency */
 599 static u16 calc_divisor(struct mmc_ios *ios)
 600 {
 601         u16 dsor = 0;
 602
 603         if (ios->clock) {
 604                 dsor = DIV_ROUND_UP(OMAP_MMC_MASTER_CLOCK, ios->clock);
 605                 if (dsor > 250)
 606                         dsor = 250;
 607         }
 608
 609         return dsor;
 610 }
 611
 612 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
 613 {
 614         struct mmc_ios *ios = &host->mmc->ios;
 615         unsigned long regval;
 616         unsigned long timeout;
 617
 618         dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
 619
 620         omap_hsmmc_stop_clock(host);
 621
 622         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 623         regval = regval & ~(CLKD_MASK | DTO_MASK);
 624         regval = regval | (calc_divisor(ios) << 6) | (DTO << 16);
 625         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 626         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 627                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 628
 629         /* Wait till the ICS bit is set */
 630         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 631         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
 632                 && time_before(jiffies, timeout))
 633                 cpu_relax();
 634
 635         omap_hsmmc_start_clock(host);
 636 }
 637
 638 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
 639 {
 640         struct mmc_ios *ios = &host->mmc->ios;
 641         u32 con;
 642
 643         con = OMAP_HSMMC_READ(host->base, CON);
 644         switch (ios->bus_width) {
 645         case MMC_BUS_WIDTH_8:
 646                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
 647                 break;
 648         case MMC_BUS_WIDTH_4:
 649                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 650                 OMAP_HSMMC_WRITE(host->base, HCTL,
 651                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 652                 break;
 653         case MMC_BUS_WIDTH_1:
 654                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 655                 OMAP_HSMMC_WRITE(host->base, HCTL,
 656                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 657                 break;
 658         }
 659 }
 660
 661 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
 662 {
 663         struct mmc_ios *ios = &host->mmc->ios;
 664         u32 con;
 665
 666         con = OMAP_HSMMC_READ(host->base, CON);
 667         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 668                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
 669         else
 670                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
 671 }
 672
 673 #ifdef CONFIG_PM
 674
 675 /*
 676  * Restore the MMC host context, if it was lost as result of a
 677  * power state change.
 678  */
 679 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 680 {
 681         struct mmc_ios *ios = &host->mmc->ios;
 682         struct omap_mmc_platform_data *pdata = host->pdata;
 683         int context_loss = 0;
 684         u32 hctl, capa;
 685         unsigned long timeout;
 686
 687         if (pdata->get_context_loss_count) {
 688                 context_loss = pdata->get_context_loss_count(host->dev);
 689                 if (context_loss < 0)
 690                         return 1;
 691         }
 692
 693         dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
 694                 context_loss == host->context_loss ? "not " : "");
 695         if (host->context_loss == context_loss)
 696                 return 1;
 697
 698         /* Wait for hardware reset */
 699         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 700         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
 701                 && time_before(jiffies, timeout))
 702                 ;
 703
 704         /* Do software reset */
 705         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
 706         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 707         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
 708                 && time_before(jiffies, timeout))
 709                 ;
 710
 711         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
 712                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
 713
 714         if (host->id == OMAP_MMC1_DEVID) {
 715                 if (host->power_mode != MMC_POWER_OFF &&
 716                     (1 << ios->vdd) <= MMC_VDD_23_24)
 717                         hctl = SDVS18;
 718                 else
 719                         hctl = SDVS30;
 720                 capa = VS30 | VS18;
 721         } else {
 722                 hctl = SDVS18;
 723                 capa = VS18;
 724         }
 725
 726         OMAP_HSMMC_WRITE(host->base, HCTL,
 727                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
 728
 729         OMAP_HSMMC_WRITE(host->base, CAPA,
 730                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
 731
 732         OMAP_HSMMC_WRITE(host->base, HCTL,
 733                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 734
 735         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 736         while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
 737                 && time_before(jiffies, timeout))
 738                 ;
 739
 740         omap_hsmmc_disable_irq(host);
 741
 742         /* Do not initialize card-specific things if the power is off */
 743         if (host->power_mode == MMC_POWER_OFF)
 744                 goto out;
 745
 746         omap_hsmmc_set_bus_width(host);
 747
 748         omap_hsmmc_set_clock(host);
 749
 750         omap_hsmmc_set_bus_mode(host);
 751
 752 out:
 753         host->context_loss = context_loss;
 754
 755         dev_dbg(mmc_dev(host->mmc), "context is restored\n");
 756         return 0;
 757 }
 758
 759 /*
 760  * Save the MMC host context (store the number of power state changes so far).
 761  */
 762 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 763 {
 764         struct omap_mmc_platform_data *pdata = host->pdata;
 765         int context_loss;
 766
 767         if (pdata->get_context_loss_count) {
 768                 context_loss = pdata->get_context_loss_count(host->dev);
 769                 if (context_loss < 0)
 770                         return;
 771                 host->context_loss = context_loss;
 772         }
 773 }
 774
 775 #else
 776
 777 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 778 {
 779         return 0;
 780 }
 781
 782 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 783 {
 784 }
 785
 786 #endif
 787
 788 /*
 789  * Send init stream sequence to card
 790  * before sending IDLE command
 791  */
 792 static void send_init_stream(struct omap_hsmmc_host *host)
 793 {
 794         int reg = 0;
 795         unsigned long timeout;
 796
 797         if (host->protect_card)
 798                 return;
 799
 800         disable_irq(host->irq);
 801
 802         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 803         OMAP_HSMMC_WRITE(host->base, CON,
 804                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 805         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 806
 807         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 808         while ((reg != CC) && time_before(jiffies, timeout))
 809                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 810
 811         OMAP_HSMMC_WRITE(host->base, CON,
 812                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 813
 814         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 815         OMAP_HSMMC_READ(host->base, STAT);
 816
 817         enable_irq(host->irq);
 818 }
 819
 820 static inline
 821 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
 822 {
 823         int r = 1;
 824
 825         if (mmc_slot(host).get_cover_state)
 826                 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
 827         return r;
 828 }
 829
 830 static ssize_t
 831 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
 832                            char *buf)
 833 {
 834         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 835         struct omap_hsmmc_host *host = mmc_priv(mmc);
 836
 837         return sprintf(buf, "%s\n",
 838                         omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
 839 }
 840
 841 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
 842
 843 static ssize_t
 844 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
 845                         char *buf)
 846 {
 847         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 848         struct omap_hsmmc_host *host = mmc_priv(mmc);
 849
 850         return sprintf(buf, "%s\n", mmc_slot(host).name);
 851 }
 852
 853 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
 854
 855 /*
 856  * Configure the response type and send the cmd.
 857  */
 858 static void
 859 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
 860         struct mmc_data *data)
 861 {
 862         int cmdreg = 0, resptype = 0, cmdtype = 0;
 863
 864         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 865                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 866         host->cmd = cmd;
 867
 868         omap_hsmmc_enable_irq(host, cmd);
 869
 870         host->response_busy = 0;
 871         if (cmd->flags & MMC_RSP_PRESENT) {
 872                 if (cmd->flags & MMC_RSP_136)
 873                         resptype = 1;
 874                 else if (cmd->flags & MMC_RSP_BUSY) {
 875                         resptype = 3;
 876                         host->response_busy = 1;
 877                 } else
 878                         resptype = 2;
 879         }
 880
 881         /*
 882          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 883          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
 884          * a val of 0x3, rest 0x0.
 885          */
 886         if (cmd == host->mrq->stop)
 887                 cmdtype = 0x3;
 888
 889         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 890
 891         if (data) {
 892                 cmdreg |= DP_SELECT | MSBS | BCE;
 893                 if (data->flags & MMC_DATA_READ)
 894                         cmdreg |= DDIR;
 895                 else
 896                         cmdreg &= ~(DDIR);
 897         }
 898
 899         if (host->use_dma)
 900                 cmdreg |= DMA_EN;
 901
 902         host->req_in_progress = 1;
 903
 904         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 905         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 906 }
 907
 908 static int
 909 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
 910 {
 911         if (data->flags & MMC_DATA_WRITE)
 912                 return DMA_TO_DEVICE;
 913         else
 914                 return DMA_FROM_DEVICE;
 915 }
 916
 917 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
 918 {
 919         int dma_ch;
 920
 921         spin_lock(&host->irq_lock);
 922         host->req_in_progress = 0;
 923         dma_ch = host->dma_ch;
 924         spin_unlock(&host->irq_lock);
 925
 926         omap_hsmmc_disable_irq(host);
 927         /* Do not complete the request if DMA is still in progress */
 928         if (mrq->data && host->use_dma && dma_ch != -1)
 929                 return;
 930         host->mrq = NULL;
 931         mmc_request_done(host->mmc, mrq);
 932 }
 933
 934 /*
 935  * Notify the transfer complete to MMC core
 936  */
 937 static void
 938 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
 939 {
 940         if (!data) {
 941                 struct mmc_request *mrq = host->mrq;
 942
 943                 /* TC before CC from CMD6 - don't know why, but it happens */
 944                 if (host->cmd && host->cmd->opcode == 6 &&
 945                     host->response_busy) {
 946                         host->response_busy = 0;
 947                         return;
 948                 }
 949
 950                 omap_hsmmc_request_done(host, mrq);
 951                 return;
 952         }
 953
 954         host->data = NULL;
 955
 956         if (!data->error)
 957                 data->bytes_xfered += data->blocks * (data->blksz);
 958         else
 959                 data->bytes_xfered = 0;
 960
 961         if (!data->stop) {
 962                 omap_hsmmc_request_done(host, data->mrq);
 963                 return;
 964         }
 965         omap_hsmmc_start_command(host, data->stop, NULL);
 966 }
 967
 968 /*
 969  * Notify the core about command completion
 970  */
 971 static void
 972 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
 973 {
 974         host->cmd = NULL;
 975
 976         if (cmd->flags & MMC_RSP_PRESENT) {
 977                 if (cmd->flags & MMC_RSP_136) {
 978                         /* response type 2 */
 979                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 980                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 981                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 982                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 983                 } else {
 984                         /* response types 1, 1b, 3, 4, 5, 6 */
 985                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 986                 }
 987         }
 988         if ((host->data == NULL && !host->response_busy) || cmd->error)
 989                 omap_hsmmc_request_done(host, cmd->mrq);
 990 }
 991
 992 /*
 993  * DMA clean up for command errors
 994  */
 995 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
 996 {
 997         int dma_ch;
 998
 999         host->data->error = errno;
1000
1001         spin_lock(&host->irq_lock);
1002         dma_ch = host->dma_ch;
1003         host->dma_ch = -1;
1004         spin_unlock(&host->irq_lock);
1005
1006         if (host->use_dma && dma_ch != -1) {
1007                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg,
1008                         host->data->sg_len,
1009                         omap_hsmmc_get_dma_dir(host, host->data));
1010                 omap_free_dma(dma_ch);
1011                 host->data->host_cookie = 0;
1012         }
1013         host->data = NULL;
1014 }
1015
1016 /*
1017  * Readable error output
1018  */
1019 #ifdef CONFIG_MMC_DEBUG
1020 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
1021 {
1022         /* --- means reserved bit without definition at documentation */
1023         static const char *omap_hsmmc_status_bits[] = {
1024                 "CC"  , "TC"  , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
1025                 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
1026                 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
1027                 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
1028         };
1029         char res[256];
1030         char *buf = res;
1031         int len, i;
1032
1033         len = sprintf(buf, "MMC IRQ 0x%x :", status);
1034         buf += len;
1035
1036         for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
1037                 if (status & (1 << i)) {
1038                         len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
1039                         buf += len;
1040                 }
1041
1042         dev_dbg(mmc_dev(host->mmc), "%s\n", res);
1043 }
1044 #else
1045 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
1046                                              u32 status)
1047 {
1048 }
1049 #endif  /* CONFIG_MMC_DEBUG */
1050
1051 /*
1052  * MMC controller internal state machines reset
1053  *
1054  * Used to reset command or data internal state machines, using respectively
1055  *  SRC or SRD bit of SYSCTL register
1056  * Can be called from interrupt context
1057  */
1058 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1059                                                    unsigned long bit)
1060 {
1061         unsigned long i = 0;
1062         unsigned long limit = (loops_per_jiffy *
1063                                 msecs_to_jiffies(MMC_TIMEOUT_MS));
1064
1065         OMAP_HSMMC_WRITE(host->base, SYSCTL,
1066                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1067
1068         /*
1069          * OMAP4 ES2 and greater has an updated reset logic.
1070          * Monitor a 0->1 transition first
1071          */
1072         if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
1073                 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1074                                         && (i++ < limit))
1075                         cpu_relax();
1076         }
1077         i = 0;
1078
1079         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1080                 (i++ < limit))
1081                 cpu_relax();
1082
1083         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1084                 dev_err(mmc_dev(host->mmc),
1085                         "Timeout waiting on controller reset in %s\n",
1086                         __func__);
1087 }
1088
1089 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1090 {
1091         struct mmc_data *data;
1092         int end_cmd = 0, end_trans = 0;
1093
1094         if (!host->req_in_progress) {
1095                 do {
1096                         OMAP_HSMMC_WRITE(host->base, STAT, status);
1097                         /* Flush posted write */
1098                         status = OMAP_HSMMC_READ(host->base, STAT);
1099                 } while (status & INT_EN_MASK);
1100                 return;
1101         }
1102
1103         data = host->data;
1104         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1105
1106         if (status & ERR) {
1107                 omap_hsmmc_dbg_report_irq(host, status);
1108                 if ((status & CMD_TIMEOUT) ||
1109                         (status & CMD_CRC)) {
1110                         if (host->cmd) {
1111                                 if (status & CMD_TIMEOUT) {
1112                                         omap_hsmmc_reset_controller_fsm(host,
1113                                                                         SRC);
1114                                         host->cmd->error = -ETIMEDOUT;
1115                                 } else {
1116                                         host->cmd->error = -EILSEQ;
1117                                 }
1118                                 end_cmd = 1;
1119                         }
1120                         if (host->data || host->response_busy) {
1121                                 if (host->data)
1122                                         omap_hsmmc_dma_cleanup(host,
1123                                                                 -ETIMEDOUT);
1124                                 host->response_busy = 0;
1125                                 omap_hsmmc_reset_controller_fsm(host, SRD);
1126                         }
1127                 }
1128                 if ((status & DATA_TIMEOUT) ||
1129                         (status & DATA_CRC)) {
1130                         if (host->data || host->response_busy) {
1131                                 int err = (status & DATA_TIMEOUT) ?
1132                                                 -ETIMEDOUT : -EILSEQ;
1133
1134                                 if (host->data)
1135                                         omap_hsmmc_dma_cleanup(host, err);
1136                                 else
1137                                         host->mrq->cmd->error = err;
1138                                 host->response_busy = 0;
1139                                 omap_hsmmc_reset_controller_fsm(host, SRD);
1140                                 end_trans = 1;
1141                         }
1142                 }
1143                 if (status & CARD_ERR) {
1144                         dev_dbg(mmc_dev(host->mmc),
1145                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
1146                         if (host->cmd)
1147                                 end_cmd = 1;
1148                         if (host->data)
1149                                 end_trans = 1;
1150                 }
1151         }
1152
1153         OMAP_HSMMC_WRITE(host->base, STAT, status);
1154
1155         if (end_cmd || ((status & CC) && host->cmd))
1156                 omap_hsmmc_cmd_done(host, host->cmd);
1157         if ((end_trans || (status & TC)) && host->mrq)
1158                 omap_hsmmc_xfer_done(host, data);
1159 }
1160
1161 /*
1162  * MMC controller IRQ handler
1163  */
1164 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1165 {
1166         struct omap_hsmmc_host *host = dev_id;
1167         int status;
1168
1169         status = OMAP_HSMMC_READ(host->base, STAT);
1170         do {
1171                 omap_hsmmc_do_irq(host, status);
1172                 /* Flush posted write */
1173                 status = OMAP_HSMMC_READ(host->base, STAT);
1174         } while (status & INT_EN_MASK);
1175
1176         return IRQ_HANDLED;
1177 }
1178
1179 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1180 {
1181         unsigned long i;
1182
1183         OMAP_HSMMC_WRITE(host->base, HCTL,
1184                          OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1185         for (i = 0; i < loops_per_jiffy; i++) {
1186                 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1187                         break;
1188                 cpu_relax();
1189         }
1190 }
1191
1192 /*
1193  * Switch MMC interface voltage ... only relevant for MMC1.
1194  *
1195  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1196  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1197  * Some chips, like eMMC ones, use internal transceivers.
1198  */
1199 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1200 {
1201         u32 reg_val = 0;
1202         int ret;
1203
1204         /* Disable the clocks */
1205         pm_runtime_put_sync(host->dev);
1206         if (host->got_dbclk)
1207                 clk_disable(host->dbclk);
1208
1209         /* Turn the power off */
1210         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1211
1212         /* Turn the power ON with given VDD 1.8 or 3.0v */
1213         if (!ret)
1214                 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1215                                                vdd);
1216         pm_runtime_get_sync(host->dev);
1217         if (host->got_dbclk)
1218                 clk_enable(host->dbclk);
1219
1220         if (ret != 0)
1221                 goto err;
1222
1223         OMAP_HSMMC_WRITE(host->base, HCTL,
1224                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1225         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1226
1227         /*
1228          * If a MMC dual voltage card is detected, the set_ios fn calls
1229          * this fn with VDD bit set for 1.8V. Upon card removal from the
1230          * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1231          *
1232          * Cope with a bit of slop in the range ... per data sheets:
1233          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1234          *    but recommended values are 1.71V to 1.89V
1235          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1236          *    but recommended values are 2.7V to 3.3V
1237          *
1238          * Board setup code shouldn't permit anything very out-of-range.
1239          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1240          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1241          */
1242         if ((1 << vdd) <= MMC_VDD_23_24)
1243                 reg_val |= SDVS18;
1244         else
1245                 reg_val |= SDVS30;
1246
1247         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1248         set_sd_bus_power(host);
1249
1250         return 0;
1251 err:
1252         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1253         return ret;
1254 }
1255
1256 /* Protect the card while the cover is open */
1257 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1258 {
1259         if (!mmc_slot(host).get_cover_state)
1260                 return;
1261
1262         host->reqs_blocked = 0;
1263         if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1264                 if (host->protect_card) {
1265                         pr_info("%s: cover is closed, "
1266                                          "card is now accessible\n",
1267                                          mmc_hostname(host->mmc));
1268                         host->protect_card = 0;
1269                 }
1270         } else {
1271                 if (!host->protect_card) {
1272                         pr_info("%s: cover is open, "
1273                                          "card is now inaccessible\n",
1274                                          mmc_hostname(host->mmc));
1275                         host->protect_card = 1;
1276                 }
1277         }
1278 }
1279
1280 /*
1281  * irq handler to notify the core about card insertion/removal
1282  */
1283 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
1284 {
1285         struct omap_hsmmc_host *host = dev_id;
1286         struct omap_mmc_slot_data *slot = &mmc_slot(host);
1287         int carddetect;
1288
1289         if (host->suspended)
1290                 return IRQ_HANDLED;
1291
1292         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1293
1294         if (slot->card_detect)
1295                 carddetect = slot->card_detect(host->dev, host->slot_id);
1296         else {
1297                 omap_hsmmc_protect_card(host);
1298                 carddetect = -ENOSYS;
1299         }
1300
1301         if (carddetect)
1302                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1303         else
1304                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1305         return IRQ_HANDLED;
1306 }
1307
1308 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
1309                                      struct mmc_data *data)
1310 {
1311         int sync_dev;
1312
1313         if (data->flags & MMC_DATA_WRITE)
1314                 sync_dev = host->dma_line_tx;
1315         else
1316                 sync_dev = host->dma_line_rx;
1317         return sync_dev;
1318 }
1319
1320 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
1321                                        struct mmc_data *data,
1322                                        struct scatterlist *sgl)
1323 {
1324         int blksz, nblk, dma_ch;
1325
1326         dma_ch = host->dma_ch;
1327         if (data->flags & MMC_DATA_WRITE) {
1328                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1329                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1330                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1331                         sg_dma_address(sgl), 0, 0);
1332         } else {
1333                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1334                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1335                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1336                         sg_dma_address(sgl), 0, 0);
1337         }
1338
1339         blksz = host->data->blksz;
1340         nblk = sg_dma_len(sgl) / blksz;
1341
1342         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1343                         blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
1344                         omap_hsmmc_get_dma_sync_dev(host, data),
1345                         !(data->flags & MMC_DATA_WRITE));
1346
1347         omap_start_dma(dma_ch);
1348 }
1349
1350 /*
1351  * DMA call back function
1352  */
1353 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
1354 {
1355         struct omap_hsmmc_host *host = cb_data;
1356         struct mmc_data *data;
1357         int dma_ch, req_in_progress;
1358
1359         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1360                 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1361                         ch_status);
1362                 return;
1363         }
1364
1365         spin_lock(&host->irq_lock);
1366         if (host->dma_ch < 0) {
1367                 spin_unlock(&host->irq_lock);
1368                 return;
1369         }
1370
1371         data = host->mrq->data;
1372         host->dma_sg_idx++;
1373         if (host->dma_sg_idx < host->dma_len) {
1374                 /* Fire up the next transfer. */
1375                 omap_hsmmc_config_dma_params(host, data,
1376                                            data->sg + host->dma_sg_idx);
1377                 spin_unlock(&host->irq_lock);
1378                 return;
1379         }
1380
1381         if (!data->host_cookie)
1382                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1383                              omap_hsmmc_get_dma_dir(host, data));
1384
1385         req_in_progress = host->req_in_progress;
1386         dma_ch = host->dma_ch;
1387         host->dma_ch = -1;
1388         spin_unlock(&host->irq_lock);
1389
1390         omap_free_dma(dma_ch);
1391
1392         /* If DMA has finished after TC, complete the request */
1393         if (!req_in_progress) {
1394                 struct mmc_request *mrq = host->mrq;
1395
1396                 host->mrq = NULL;
1397                 mmc_request_done(host->mmc, mrq);
1398         }
1399 }
1400
1401 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1402                                        struct mmc_data *data,
1403                                        struct omap_hsmmc_next *next)
1404 {
1405         int dma_len;
1406
1407         if (!next && data->host_cookie &&
1408             data->host_cookie != host->next_data.cookie) {
1409                 pr_warning("[%s] invalid cookie: data->host_cookie %d"
1410                        " host->next_data.cookie %d\n",
1411                        __func__, data->host_cookie, host->next_data.cookie);
1412                 data->host_cookie = 0;
1413         }
1414
1415         /* Check if next job is already prepared */
1416         if (next ||
1417             (!next && data->host_cookie != host->next_data.cookie)) {
1418                 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1419                                      data->sg_len,
1420                                      omap_hsmmc_get_dma_dir(host, data));
1421
1422         } else {
1423                 dma_len = host->next_data.dma_len;
1424                 host->next_data.dma_len = 0;
1425         }
1426
1427
1428         if (dma_len == 0)
1429                 return -EINVAL;
1430
1431         if (next) {
1432                 next->dma_len = dma_len;
1433                 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1434         } else
1435                 host->dma_len = dma_len;
1436
1437         return 0;
1438 }
1439
1440 /*
1441  * Routine to configure and start DMA for the MMC card
1442  */
1443 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1444                                         struct mmc_request *req)
1445 {
1446         int dma_ch = 0, ret = 0, i;
1447         struct mmc_data *data = req->data;
1448
1449         /* Sanity check: all the SG entries must be aligned by block size. */
1450         for (i = 0; i < data->sg_len; i++) {
1451                 struct scatterlist *sgl;
1452
1453                 sgl = data->sg + i;
1454                 if (sgl->length % data->blksz)
1455                         return -EINVAL;
1456         }
1457         if ((data->blksz % 4) != 0)
1458                 /* REVISIT: The MMC buffer increments only when MSB is written.
1459                  * Return error for blksz which is non multiple of four.
1460                  */
1461                 return -EINVAL;
1462
1463         BUG_ON(host->dma_ch != -1);
1464
1465         ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1466                                "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
1467         if (ret != 0) {
1468                 dev_err(mmc_dev(host->mmc),
1469                         "%s: omap_request_dma() failed with %d\n",
1470                         mmc_hostname(host->mmc), ret);
1471                 return ret;
1472         }
1473         ret = omap_hsmmc_pre_dma_transfer(host, data, NULL);
1474         if (ret)
1475                 return ret;
1476
1477         host->dma_ch = dma_ch;
1478         host->dma_sg_idx = 0;
1479
1480         omap_hsmmc_config_dma_params(host, data, data->sg);
1481
1482         return 0;
1483 }
1484
1485 static void set_data_timeout(struct omap_hsmmc_host *host,
1486                              unsigned int timeout_ns,
1487                              unsigned int timeout_clks)
1488 {
1489         unsigned int timeout, cycle_ns;
1490         uint32_t reg, clkd, dto = 0;
1491
1492         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1493         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1494         if (clkd == 0)
1495                 clkd = 1;
1496
1497         cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1498         timeout = timeout_ns / cycle_ns;
1499         timeout += timeout_clks;
1500         if (timeout) {
1501                 while ((timeout & 0x80000000) == 0) {
1502                         dto += 1;
1503                         timeout <<= 1;
1504                 }
1505                 dto = 31 - dto;
1506                 timeout <<= 1;
1507                 if (timeout && dto)
1508                         dto += 1;
1509                 if (dto >= 13)
1510                         dto -= 13;
1511                 else
1512                         dto = 0;
1513                 if (dto > 14)
1514                         dto = 14;
1515         }
1516
1517         reg &= ~DTO_MASK;
1518         reg |= dto << DTO_SHIFT;
1519         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1520 }
1521
1522 /*
1523  * Configure block length for MMC/SD cards and initiate the transfer.
1524  */
1525 static int
1526 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1527 {
1528         int ret;
1529         host->data = req->data;
1530
1531         if (req->data == NULL) {
1532                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1533                 /*
1534                  * Set an arbitrary 100ms data timeout for commands with
1535                  * busy signal.
1536                  */
1537                 if (req->cmd->flags & MMC_RSP_BUSY)
1538                         set_data_timeout(host, 100000000U, 0);
1539                 return 0;
1540         }
1541
1542         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1543                                         | (req->data->blocks << 16));
1544         set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1545
1546         if (host->use_dma) {
1547                 ret = omap_hsmmc_start_dma_transfer(host, req);
1548                 if (ret != 0) {
1549                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1550                         return ret;
1551                 }
1552         }
1553         return 0;
1554 }
1555
1556 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1557                                 int err)
1558 {
1559         struct omap_hsmmc_host *host = mmc_priv(mmc);
1560         struct mmc_data *data = mrq->data;
1561
1562         if (host->use_dma) {
1563                 if (data->host_cookie)
1564                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
1565                                      data->sg_len,
1566                                      omap_hsmmc_get_dma_dir(host, data));
1567                 data->host_cookie = 0;
1568         }
1569 }
1570
1571 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1572                                bool is_first_req)
1573 {
1574         struct omap_hsmmc_host *host = mmc_priv(mmc);
1575
1576         if (mrq->data->host_cookie) {
1577                 mrq->data->host_cookie = 0;
1578                 return ;
1579         }
1580
1581         if (host->use_dma)
1582                 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1583                                                 &host->next_data))
1584                         mrq->data->host_cookie = 0;
1585 }
1586
1587 /*
1588  * Request function. for read/write operation
1589  */
1590 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1591 {
1592         struct omap_hsmmc_host *host = mmc_priv(mmc);
1593         int err;
1594
1595         BUG_ON(host->req_in_progress);
1596         BUG_ON(host->dma_ch != -1);
1597         if (host->protect_card) {
1598                 if (host->reqs_blocked < 3) {
1599                         /*
1600                          * Ensure the controller is left in a consistent
1601                          * state by resetting the command and data state
1602                          * machines.
1603                          */
1604                         omap_hsmmc_reset_controller_fsm(host, SRD);
1605                         omap_hsmmc_reset_controller_fsm(host, SRC);
1606                         host->reqs_blocked += 1;
1607                 }
1608                 req->cmd->error = -EBADF;
1609                 if (req->data)
1610                         req->data->error = -EBADF;
1611                 req->cmd->retries = 0;
1612                 mmc_request_done(mmc, req);
1613                 return;
1614         } else if (host->reqs_blocked)
1615                 host->reqs_blocked = 0;
1616         WARN_ON(host->mrq != NULL);
1617         host->mrq = req;
1618         err = omap_hsmmc_prepare_data(host, req);
1619         if (err) {
1620                 req->cmd->error = err;
1621                 if (req->data)
1622                         req->data->error = err;
1623                 host->mrq = NULL;
1624                 mmc_request_done(mmc, req);
1625                 return;
1626         }
1627
1628         omap_hsmmc_start_command(host, req->cmd, req->data);
1629 }
1630
1631 /* Routine to configure clock values. Exposed API to core */
1632 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1633 {
1634         struct omap_hsmmc_host *host = mmc_priv(mmc);
1635         int do_send_init_stream = 0;
1636
1637         pm_runtime_get_sync(host->dev);
1638
1639         if (ios->power_mode != host->power_mode) {
1640                 switch (ios->power_mode) {
1641                 case MMC_POWER_OFF:
1642                         mmc_slot(host).set_power(host->dev, host->slot_id,
1643                                                  0, 0);
1644                         host->vdd = 0;
1645                         break;
1646                 case MMC_POWER_UP:
1647                         mmc_slot(host).set_power(host->dev, host->slot_id,
1648                                                  1, ios->vdd);
1649                         host->vdd = ios->vdd;
1650                         break;
1651                 case MMC_POWER_ON:
1652                         do_send_init_stream = 1;
1653                         break;
1654                 }
1655                 host->power_mode = ios->power_mode;
1656         }
1657
1658         /* FIXME: set registers based only on changes to ios */
1659
1660         omap_hsmmc_set_bus_width(host);
1661
1662         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1663                 /* Only MMC1 can interface at 3V without some flavor
1664                  * of external transceiver; but they all handle 1.8V.
1665                  */
1666                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1667                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1668                                 /*
1669                                  * The mmc_select_voltage fn of the core does
1670                                  * not seem to set the power_mode to
1671                                  * MMC_POWER_UP upon recalculating the voltage.
1672                                  * vdd 1.8v.
1673                                  */
1674                         if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1675                                 dev_dbg(mmc_dev(host->mmc),
1676                                                 "Switch operation failed\n");
1677                 }
1678         }
1679
1680         omap_hsmmc_set_clock(host);
1681
1682         if (do_send_init_stream)
1683                 send_init_stream(host);
1684
1685         omap_hsmmc_set_bus_mode(host);
1686
1687         pm_runtime_put_autosuspend(host->dev);
1688 }
1689
1690 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1691 {
1692         struct omap_hsmmc_host *host = mmc_priv(mmc);
1693
1694         if (!mmc_slot(host).card_detect)
1695                 return -ENOSYS;
1696         return mmc_slot(host).card_detect(host->dev, host->slot_id);
1697 }
1698
1699 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1700 {
1701         struct omap_hsmmc_host *host = mmc_priv(mmc);
1702
1703         if (!mmc_slot(host).get_ro)
1704                 return -ENOSYS;
1705         return mmc_slot(host).get_ro(host->dev, 0);
1706 }
1707
1708 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1709 {
1710         struct omap_hsmmc_host *host = mmc_priv(mmc);
1711
1712         if (mmc_slot(host).init_card)
1713                 mmc_slot(host).init_card(card);
1714 }
1715
1716 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1717 {
1718         u32 hctl, capa, value;
1719
1720         /* Only MMC1 supports 3.0V */
1721         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1722                 hctl = SDVS30;
1723                 capa = VS30 | VS18;
1724         } else {
1725                 hctl = SDVS18;
1726                 capa = VS18;
1727         }
1728
1729         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1730         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1731
1732         value = OMAP_HSMMC_READ(host->base, CAPA);
1733         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1734
1735         /* Set the controller to AUTO IDLE mode */
1736         value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1737         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1738
1739         /* Set SD bus power bit */
1740         set_sd_bus_power(host);
1741 }
1742
1743 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1744 {
1745         struct omap_hsmmc_host *host = mmc_priv(mmc);
1746
1747         pm_runtime_get_sync(host->dev);
1748
1749         return 0;
1750 }
1751
1752 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
1753 {
1754         struct omap_hsmmc_host *host = mmc_priv(mmc);
1755
1756         pm_runtime_mark_last_busy(host->dev);
1757         pm_runtime_put_autosuspend(host->dev);
1758
1759         return 0;
1760 }
1761
1762 static const struct mmc_host_ops omap_hsmmc_ops = {
1763         .enable = omap_hsmmc_enable_fclk,
1764         .disable = omap_hsmmc_disable_fclk,
1765         .post_req = omap_hsmmc_post_req,
1766         .pre_req = omap_hsmmc_pre_req,
1767         .request = omap_hsmmc_request,
1768         .set_ios = omap_hsmmc_set_ios,
1769         .get_cd = omap_hsmmc_get_cd,
1770         .get_ro = omap_hsmmc_get_ro,
1771         .init_card = omap_hsmmc_init_card,
1772         /* NYET -- enable_sdio_irq */
1773 };
1774
1775 #ifdef CONFIG_DEBUG_FS
1776
1777 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1778 {
1779         struct mmc_host *mmc = s->private;
1780         struct omap_hsmmc_host *host = mmc_priv(mmc);
1781         int context_loss = 0;
1782
1783         if (host->pdata->get_context_loss_count)
1784                 context_loss = host->pdata->get_context_loss_count(host->dev);
1785
1786         seq_printf(s, "mmc%d:\n"
1787                         " enabled:\t%d\n"
1788                         " dpm_state:\t%d\n"
1789                         " nesting_cnt:\t%d\n"
1790                         " ctx_loss:\t%d:%d\n"
1791                         "\nregs:\n",
1792                         mmc->index, mmc->enabled ? 1 : 0,
1793                         host->dpm_state, mmc->nesting_cnt,
1794                         host->context_loss, context_loss);
1795
1796         if (host->suspended) {
1797                 seq_printf(s, "host suspended, can't read registers\n");
1798                 return 0;
1799         }
1800
1801         pm_runtime_get_sync(host->dev);
1802
1803         seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1804                         OMAP_HSMMC_READ(host->base, SYSCONFIG));
1805         seq_printf(s, "CON:\t\t0x%08x\n",
1806                         OMAP_HSMMC_READ(host->base, CON));
1807         seq_printf(s, "HCTL:\t\t0x%08x\n",
1808                         OMAP_HSMMC_READ(host->base, HCTL));
1809         seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1810                         OMAP_HSMMC_READ(host->base, SYSCTL));
1811         seq_printf(s, "IE:\t\t0x%08x\n",
1812                         OMAP_HSMMC_READ(host->base, IE));
1813         seq_printf(s, "ISE:\t\t0x%08x\n",
1814                         OMAP_HSMMC_READ(host->base, ISE));
1815         seq_printf(s, "CAPA:\t\t0x%08x\n",
1816                         OMAP_HSMMC_READ(host->base, CAPA));
1817
1818         pm_runtime_mark_last_busy(host->dev);
1819         pm_runtime_put_autosuspend(host->dev);
1820
1821         return 0;
1822 }
1823
1824 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1825 {
1826         return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1827 }
1828
1829 static const struct file_operations mmc_regs_fops = {
1830         .open           = omap_hsmmc_regs_open,
1831         .read           = seq_read,
1832         .llseek         = seq_lseek,
1833         .release        = single_release,
1834 };
1835
1836 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1837 {
1838         if (mmc->debugfs_root)
1839                 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1840                         mmc, &mmc_regs_fops);
1841 }
1842
1843 #else
1844
1845 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1846 {
1847 }
1848
1849 #endif
1850
1851 static int __init omap_hsmmc_probe(struct platform_device *pdev)
1852 {
1853         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1854         struct mmc_host *mmc;
1855         struct omap_hsmmc_host *host = NULL;
1856         struct resource *res;
1857         int ret, irq;
1858
1859         if (pdata == NULL) {
1860                 dev_err(&pdev->dev, "Platform Data is missing\n");
1861                 return -ENXIO;
1862         }
1863
1864         if (pdata->nr_slots == 0) {
1865                 dev_err(&pdev->dev, "No Slots\n");
1866                 return -ENXIO;
1867         }
1868
1869         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1870         irq = platform_get_irq(pdev, 0);
1871         if (res == NULL || irq < 0)
1872                 return -ENXIO;
1873
1874         res->start += pdata->reg_offset;
1875         res->end += pdata->reg_offset;
1876         res = request_mem_region(res->start, resource_size(res), pdev->name);
1877         if (res == NULL)
1878                 return -EBUSY;
1879
1880         ret = omap_hsmmc_gpio_init(pdata);
1881         if (ret)
1882                 goto err;
1883
1884         mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1885         if (!mmc) {
1886                 ret = -ENOMEM;
1887                 goto err_alloc;
1888         }
1889
1890         host            = mmc_priv(mmc);
1891         host->mmc       = mmc;
1892         host->pdata     = pdata;
1893         host->dev       = &pdev->dev;
1894         host->use_dma   = 1;
1895         host->dev->dma_mask = &pdata->dma_mask;
1896         host->dma_ch    = -1;
1897         host->irq       = irq;
1898         host->id        = pdev->id;
1899         host->slot_id   = 0;
1900         host->mapbase   = res->start;
1901         host->base      = ioremap(host->mapbase, SZ_4K);
1902         host->power_mode = MMC_POWER_OFF;
1903         host->next_data.cookie = 1;
1904
1905         platform_set_drvdata(pdev, host);
1906
1907         mmc->ops        = &omap_hsmmc_ops;
1908
1909         /*
1910          * If regulator_disable can only put vcc_aux to sleep then there is
1911          * no off state.
1912          */
1913         if (mmc_slot(host).vcc_aux_disable_is_sleep)
1914                 mmc_slot(host).no_off = 1;
1915
1916         mmc->f_min      = OMAP_MMC_MIN_CLOCK;
1917         mmc->f_max      = OMAP_MMC_MAX_CLOCK;
1918
1919         spin_lock_init(&host->irq_lock);
1920
1921         host->fclk = clk_get(&pdev->dev, "fck");
1922         if (IS_ERR(host->fclk)) {
1923                 ret = PTR_ERR(host->fclk);
1924                 host->fclk = NULL;
1925                 goto err1;
1926         }
1927
1928         omap_hsmmc_context_save(host);
1929
1930         mmc->caps |= MMC_CAP_DISABLE;
1931         if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1932                 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1933                 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
1934         }
1935
1936         pm_runtime_enable(host->dev);
1937         pm_runtime_get_sync(host->dev);
1938         pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1939         pm_runtime_use_autosuspend(host->dev);
1940
1941         if (cpu_is_omap2430()) {
1942                 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1943                 /*
1944                  * MMC can still work without debounce clock.
1945                  */
1946                 if (IS_ERR(host->dbclk))
1947                         dev_warn(mmc_dev(host->mmc),
1948                                 "Failed to get debounce clock\n");
1949                 else
1950                         host->got_dbclk = 1;
1951
1952                 if (host->got_dbclk)
1953                         if (clk_enable(host->dbclk) != 0)
1954                                 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1955                                                         " clk failed\n");
1956         }
1957
1958         /* Since we do only SG emulation, we can have as many segs
1959          * as we want. */
1960         mmc->max_segs = 1024;
1961
1962         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
1963         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
1964         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1965         mmc->max_seg_size = mmc->max_req_size;
1966
1967         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1968                      MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
1969
1970         mmc->caps |= mmc_slot(host).caps;
1971         if (mmc->caps & MMC_CAP_8_BIT_DATA)
1972                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1973
1974         if (mmc_slot(host).nonremovable)
1975                 mmc->caps |= MMC_CAP_NONREMOVABLE;
1976
1977         omap_hsmmc_conf_bus_power(host);
1978
1979         /* Select DMA lines */
1980         switch (host->id) {
1981         case OMAP_MMC1_DEVID:
1982                 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
1983                 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
1984                 break;
1985         case OMAP_MMC2_DEVID:
1986                 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
1987                 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
1988                 break;
1989         case OMAP_MMC3_DEVID:
1990                 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
1991                 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
1992                 break;
1993         case OMAP_MMC4_DEVID:
1994                 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
1995                 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
1996                 break;
1997         case OMAP_MMC5_DEVID:
1998                 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
1999                 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
2000                 break;
2001         default:
2002                 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
2003                 goto err_irq;
2004         }
2005
2006         /* Request IRQ for MMC operations */
2007         ret = request_irq(host->irq, omap_hsmmc_irq, 0,
2008                         mmc_hostname(mmc), host);
2009         if (ret) {
2010                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2011                 goto err_irq;
2012         }
2013
2014         if (pdata->init != NULL) {
2015                 if (pdata->init(&pdev->dev) != 0) {
2016                         dev_dbg(mmc_dev(host->mmc),
2017                                 "Unable to configure MMC IRQs\n");
2018                         goto err_irq_cd_init;
2019                 }
2020         }
2021
2022         if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
2023                 ret = omap_hsmmc_reg_get(host);
2024                 if (ret)
2025                         goto err_reg;
2026                 host->use_reg = 1;
2027         }
2028
2029         mmc->ocr_avail = mmc_slot(host).ocr_mask;
2030
2031         /* Request IRQ for card detect */
2032         if ((mmc_slot(host).card_detect_irq)) {
2033                 ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
2034                                            NULL,
2035                                            omap_hsmmc_detect,
2036                                            IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
2037                                            mmc_hostname(mmc), host);
2038                 if (ret) {
2039                         dev_dbg(mmc_dev(host->mmc),
2040                                 "Unable to grab MMC CD IRQ\n");
2041                         goto err_irq_cd;
2042                 }
2043                 pdata->suspend = omap_hsmmc_suspend_cdirq;
2044                 pdata->resume = omap_hsmmc_resume_cdirq;
2045         }
2046
2047         omap_hsmmc_disable_irq(host);
2048
2049         omap_hsmmc_protect_card(host);
2050
2051         mmc_add_host(mmc);
2052
2053         if (mmc_slot(host).name != NULL) {
2054                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2055                 if (ret < 0)
2056                         goto err_slot_name;
2057         }
2058         if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
2059                 ret = device_create_file(&mmc->class_dev,
2060                                         &dev_attr_cover_switch);
2061                 if (ret < 0)
2062                         goto err_slot_name;
2063         }
2064
2065         omap_hsmmc_debugfs(mmc);
2066         pm_runtime_mark_last_busy(host->dev);
2067         pm_runtime_put_autosuspend(host->dev);
2068
2069         return 0;
2070
2071 err_slot_name:
2072         mmc_remove_host(mmc);
2073         free_irq(mmc_slot(host).card_detect_irq, host);
2074 err_irq_cd:
2075         if (host->use_reg)
2076                 omap_hsmmc_reg_put(host);
2077 err_reg:
2078         if (host->pdata->cleanup)
2079                 host->pdata->cleanup(&pdev->dev);
2080 err_irq_cd_init:
2081         free_irq(host->irq, host);
2082 err_irq:
2083         pm_runtime_mark_last_busy(host->dev);
2084         pm_runtime_put_autosuspend(host->dev);
2085         clk_put(host->fclk);
2086         if (host->got_dbclk) {
2087                 clk_disable(host->dbclk);
2088                 clk_put(host->dbclk);
2089         }
2090 err1:
2091         iounmap(host->base);
2092         platform_set_drvdata(pdev, NULL);
2093         mmc_free_host(mmc);
2094 err_alloc:
2095         omap_hsmmc_gpio_free(pdata);
2096 err:
2097         release_mem_region(res->start, resource_size(res));
2098         return ret;
2099 }
2100
2101 static int omap_hsmmc_remove(struct platform_device *pdev)
2102 {
2103         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2104         struct resource *res;
2105
2106         if (host) {
2107                 pm_runtime_get_sync(host->dev);
2108                 mmc_remove_host(host->mmc);
2109                 if (host->use_reg)
2110                         omap_hsmmc_reg_put(host);
2111                 if (host->pdata->cleanup)
2112                         host->pdata->cleanup(&pdev->dev);
2113                 free_irq(host->irq, host);
2114                 if (mmc_slot(host).card_detect_irq)
2115                         free_irq(mmc_slot(host).card_detect_irq, host);
2116
2117                 pm_runtime_put_sync(host->dev);
2118                 pm_runtime_disable(host->dev);
2119                 clk_put(host->fclk);
2120                 if (host->got_dbclk) {
2121                         clk_disable(host->dbclk);
2122                         clk_put(host->dbclk);
2123                 }
2124
2125                 mmc_free_host(host->mmc);
2126                 iounmap(host->base);
2127                 omap_hsmmc_gpio_free(pdev->dev.platform_data);
2128         }
2129
2130         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2131         if (res)
2132                 release_mem_region(res->start, resource_size(res));
2133         platform_set_drvdata(pdev, NULL);
2134
2135         return 0;
2136 }
2137
2138 #ifdef CONFIG_PM
2139 static int omap_hsmmc_suspend(struct device *dev)
2140 {
2141         int ret = 0;
2142         struct platform_device *pdev = to_platform_device(dev);
2143         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2144
2145         if (host && host->suspended)
2146                 return 0;
2147
2148         if (host) {
2149                 pm_runtime_get_sync(host->dev);
2150                 host->suspended = 1;
2151                 if (host->pdata->suspend) {
2152                         ret = host->pdata->suspend(&pdev->dev,
2153                                                         host->slot_id);
2154                         if (ret) {
2155                                 dev_dbg(mmc_dev(host->mmc),
2156                                         "Unable to handle MMC board"
2157                                         " level suspend\n");
2158                                 host->suspended = 0;
2159                                 return ret;
2160                         }
2161                 }
2162                 ret = mmc_suspend_host(host->mmc);
2163
2164                 if (ret == 0) {
2165                         omap_hsmmc_disable_irq(host);
2166                         OMAP_HSMMC_WRITE(host->base, HCTL,
2167                                 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2168                         if (host->got_dbclk)
2169                                 clk_disable(host->dbclk);
2170                 } else {
2171                         host->suspended = 0;
2172                         if (host->pdata->resume) {
2173                                 ret = host->pdata->resume(&pdev->dev,
2174                                                           host->slot_id);
2175                                 if (ret)
2176                                         dev_dbg(mmc_dev(host->mmc),
2177                                                 "Unmask interrupt failed\n");
2178                         }
2179                 }
2180                 pm_runtime_put_sync(host->dev);
2181         }
2182         return ret;
2183 }
2184
2185 /* Routine to resume the MMC device */
2186 static int omap_hsmmc_resume(struct device *dev)
2187 {
2188         int ret = 0;
2189         struct platform_device *pdev = to_platform_device(dev);
2190         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2191
2192         if (host && !host->suspended)
2193                 return 0;
2194
2195         if (host) {
2196                 pm_runtime_get_sync(host->dev);
2197
2198                 if (host->got_dbclk)
2199                         clk_enable(host->dbclk);
2200
2201                 omap_hsmmc_conf_bus_power(host);
2202
2203                 if (host->pdata->resume) {
2204                         ret = host->pdata->resume(&pdev->dev, host->slot_id);
2205                         if (ret)
2206                                 dev_dbg(mmc_dev(host->mmc),
2207                                         "Unmask interrupt failed\n");
2208                 }
2209
2210                 omap_hsmmc_protect_card(host);
2211
2212                 /* Notify the core to resume the host */
2213                 ret = mmc_resume_host(host->mmc);
2214                 if (ret == 0)
2215                         host->suspended = 0;
2216
2217                 pm_runtime_mark_last_busy(host->dev);
2218                 pm_runtime_put_autosuspend(host->dev);
2219         }
2220
2221         return ret;
2222
2223 }
2224
2225 #else
2226 #define omap_hsmmc_suspend      NULL
2227 #define omap_hsmmc_resume               NULL
2228 #endif
2229
2230 static int omap_hsmmc_runtime_suspend(struct device *dev)
2231 {
2232         struct omap_hsmmc_host *host;
2233
2234         host = platform_get_drvdata(to_platform_device(dev));
2235         omap_hsmmc_context_save(host);
2236         dev_dbg(mmc_dev(host->mmc), "disabled\n");
2237
2238         return 0;
2239 }
2240
2241 static int omap_hsmmc_runtime_resume(struct device *dev)
2242 {
2243         struct omap_hsmmc_host *host;
2244
2245         host = platform_get_drvdata(to_platform_device(dev));
2246         omap_hsmmc_context_restore(host);
2247         dev_dbg(mmc_dev(host->mmc), "enabled\n");
2248
2249         return 0;
2250 }
2251
2252 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2253         .suspend        = omap_hsmmc_suspend,
2254         .resume         = omap_hsmmc_resume,
2255         .runtime_suspend = omap_hsmmc_runtime_suspend,
2256         .runtime_resume = omap_hsmmc_runtime_resume,
2257 };
2258
2259 static struct platform_driver omap_hsmmc_driver = {
2260         .remove         = omap_hsmmc_remove,
2261         .driver         = {
2262                 .name = DRIVER_NAME,
2263                 .owner = THIS_MODULE,
2264                 .pm = &omap_hsmmc_dev_pm_ops,
2265         },
2266 };
2267
2268 static int __init omap_hsmmc_init(void)
2269 {
2270         /* Register the MMC driver */
2271         return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
2272 }
2273
2274 static void __exit omap_hsmmc_cleanup(void)
2275 {
2276         /* Unregister MMC driver */
2277         platform_driver_unregister(&omap_hsmmc_driver);
2278 }
2279
2280 module_init(omap_hsmmc_init);
2281 module_exit(omap_hsmmc_cleanup);
2282
2283 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2284 MODULE_LICENSE("GPL");
2285 MODULE_ALIAS("platform:" DRIVER_NAME);
2286 MODULE_AUTHOR("Texas Instruments Inc");