2 * twl4030_usb - TWL4030 USB transceiver, talking to OMAP OTG controller
4 * Copyright (C) 2004-2007 Texas Instruments
5 * Copyright (C) 2008 Nokia Corporation
6 * Contact: Felipe Balbi <felipe.balbi@nokia.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * - HS USB ULPI mode works.
24 * - 3-pin mode support may be added in future.
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/platform_device.h>
31 #include <linux/spinlock.h>
32 #include <linux/workqueue.h>
34 #include <linux/delay.h>
35 #include <linux/usb/otg.h>
36 #include <linux/i2c/twl4030.h>
39 /* Register defines */
41 #define VENDOR_ID_LO 0x00
42 #define VENDOR_ID_HI 0x01
43 #define PRODUCT_ID_LO 0x02
44 #define PRODUCT_ID_HI 0x03
46 #define FUNC_CTRL 0x04
47 #define FUNC_CTRL_SET 0x05
48 #define FUNC_CTRL_CLR 0x06
49 #define FUNC_CTRL_SUSPENDM (1 << 6)
50 #define FUNC_CTRL_RESET (1 << 5)
51 #define FUNC_CTRL_OPMODE_MASK (3 << 3) /* bits 3 and 4 */
52 #define FUNC_CTRL_OPMODE_NORMAL (0 << 3)
53 #define FUNC_CTRL_OPMODE_NONDRIVING (1 << 3)
54 #define FUNC_CTRL_OPMODE_DISABLE_BIT_NRZI (2 << 3)
55 #define FUNC_CTRL_TERMSELECT (1 << 2)
56 #define FUNC_CTRL_XCVRSELECT_MASK (3 << 0) /* bits 0 and 1 */
57 #define FUNC_CTRL_XCVRSELECT_HS (0 << 0)
58 #define FUNC_CTRL_XCVRSELECT_FS (1 << 0)
59 #define FUNC_CTRL_XCVRSELECT_LS (2 << 0)
60 #define FUNC_CTRL_XCVRSELECT_FS4LS (3 << 0)
63 #define IFC_CTRL_SET 0x08
64 #define IFC_CTRL_CLR 0x09
65 #define IFC_CTRL_INTERFACE_PROTECT_DISABLE (1 << 7)
66 #define IFC_CTRL_AUTORESUME (1 << 4)
67 #define IFC_CTRL_CLOCKSUSPENDM (1 << 3)
68 #define IFC_CTRL_CARKITMODE (1 << 2)
69 #define IFC_CTRL_FSLSSERIALMODE_3PIN (1 << 1)
71 #define TWL4030_OTG_CTRL 0x0A
72 #define TWL4030_OTG_CTRL_SET 0x0B
73 #define TWL4030_OTG_CTRL_CLR 0x0C
74 #define TWL4030_OTG_CTRL_DRVVBUS (1 << 5)
75 #define TWL4030_OTG_CTRL_CHRGVBUS (1 << 4)
76 #define TWL4030_OTG_CTRL_DISCHRGVBUS (1 << 3)
77 #define TWL4030_OTG_CTRL_DMPULLDOWN (1 << 2)
78 #define TWL4030_OTG_CTRL_DPPULLDOWN (1 << 1)
79 #define TWL4030_OTG_CTRL_IDPULLUP (1 << 0)
81 #define USB_INT_EN_RISE 0x0D
82 #define USB_INT_EN_RISE_SET 0x0E
83 #define USB_INT_EN_RISE_CLR 0x0F
84 #define USB_INT_EN_FALL 0x10
85 #define USB_INT_EN_FALL_SET 0x11
86 #define USB_INT_EN_FALL_CLR 0x12
87 #define USB_INT_STS 0x13
88 #define USB_INT_LATCH 0x14
89 #define USB_INT_IDGND (1 << 4)
90 #define USB_INT_SESSEND (1 << 3)
91 #define USB_INT_SESSVALID (1 << 2)
92 #define USB_INT_VBUSVALID (1 << 1)
93 #define USB_INT_HOSTDISCONNECT (1 << 0)
95 #define CARKIT_CTRL 0x19
96 #define CARKIT_CTRL_SET 0x1A
97 #define CARKIT_CTRL_CLR 0x1B
98 #define CARKIT_CTRL_MICEN (1 << 6)
99 #define CARKIT_CTRL_SPKRIGHTEN (1 << 5)
100 #define CARKIT_CTRL_SPKLEFTEN (1 << 4)
101 #define CARKIT_CTRL_RXDEN (1 << 3)
102 #define CARKIT_CTRL_TXDEN (1 << 2)
103 #define CARKIT_CTRL_IDGNDDRV (1 << 1)
104 #define CARKIT_CTRL_CARKITPWR (1 << 0)
105 #define CARKIT_PLS_CTRL 0x22
106 #define CARKIT_PLS_CTRL_SET 0x23
107 #define CARKIT_PLS_CTRL_CLR 0x24
108 #define CARKIT_PLS_CTRL_SPKRRIGHT_BIASEN (1 << 3)
109 #define CARKIT_PLS_CTRL_SPKRLEFT_BIASEN (1 << 2)
110 #define CARKIT_PLS_CTRL_RXPLSEN (1 << 1)
111 #define CARKIT_PLS_CTRL_TXPLSEN (1 << 0)
113 #define MCPC_CTRL 0x30
114 #define MCPC_CTRL_SET 0x31
115 #define MCPC_CTRL_CLR 0x32
116 #define MCPC_CTRL_RTSOL (1 << 7)
117 #define MCPC_CTRL_EXTSWR (1 << 6)
118 #define MCPC_CTRL_EXTSWC (1 << 5)
119 #define MCPC_CTRL_VOICESW (1 << 4)
120 #define MCPC_CTRL_OUT64K (1 << 3)
121 #define MCPC_CTRL_RTSCTSSW (1 << 2)
122 #define MCPC_CTRL_HS_UART (1 << 0)
124 #define MCPC_IO_CTRL 0x33
125 #define MCPC_IO_CTRL_SET 0x34
126 #define MCPC_IO_CTRL_CLR 0x35
127 #define MCPC_IO_CTRL_MICBIASEN (1 << 5)
128 #define MCPC_IO_CTRL_CTS_NPU (1 << 4)
129 #define MCPC_IO_CTRL_RXD_PU (1 << 3)
130 #define MCPC_IO_CTRL_TXDTYP (1 << 2)
131 #define MCPC_IO_CTRL_CTSTYP (1 << 1)
132 #define MCPC_IO_CTRL_RTSTYP (1 << 0)
134 #define MCPC_CTRL2 0x36
135 #define MCPC_CTRL2_SET 0x37
136 #define MCPC_CTRL2_CLR 0x38
137 #define MCPC_CTRL2_MCPC_CK_EN (1 << 0)
139 #define OTHER_FUNC_CTRL 0x80
140 #define OTHER_FUNC_CTRL_SET 0x81
141 #define OTHER_FUNC_CTRL_CLR 0x82
142 #define OTHER_FUNC_CTRL_BDIS_ACON_EN (1 << 4)
143 #define OTHER_FUNC_CTRL_FIVEWIRE_MODE (1 << 2)
145 #define OTHER_IFC_CTRL 0x83
146 #define OTHER_IFC_CTRL_SET 0x84
147 #define OTHER_IFC_CTRL_CLR 0x85
148 #define OTHER_IFC_CTRL_OE_INT_EN (1 << 6)
149 #define OTHER_IFC_CTRL_CEA2011_MODE (1 << 5)
150 #define OTHER_IFC_CTRL_FSLSSERIALMODE_4PIN (1 << 4)
151 #define OTHER_IFC_CTRL_HIZ_ULPI_60MHZ_OUT (1 << 3)
152 #define OTHER_IFC_CTRL_HIZ_ULPI (1 << 2)
153 #define OTHER_IFC_CTRL_ALT_INT_REROUTE (1 << 0)
155 #define OTHER_INT_EN_RISE 0x86
156 #define OTHER_INT_EN_RISE_SET 0x87
157 #define OTHER_INT_EN_RISE_CLR 0x88
158 #define OTHER_INT_EN_FALL 0x89
159 #define OTHER_INT_EN_FALL_SET 0x8A
160 #define OTHER_INT_EN_FALL_CLR 0x8B
161 #define OTHER_INT_STS 0x8C
162 #define OTHER_INT_LATCH 0x8D
163 #define OTHER_INT_VB_SESS_VLD (1 << 7)
164 #define OTHER_INT_DM_HI (1 << 6) /* not valid for "latch" reg */
165 #define OTHER_INT_DP_HI (1 << 5) /* not valid for "latch" reg */
166 #define OTHER_INT_BDIS_ACON (1 << 3) /* not valid for "fall" regs */
167 #define OTHER_INT_MANU (1 << 1)
168 #define OTHER_INT_ABNORMAL_STRESS (1 << 0)
170 #define ID_STATUS 0x96
171 #define ID_RES_FLOAT (1 << 4)
172 #define ID_RES_440K (1 << 3)
173 #define ID_RES_200K (1 << 2)
174 #define ID_RES_102K (1 << 1)
175 #define ID_RES_GND (1 << 0)
177 #define POWER_CTRL 0xAC
178 #define POWER_CTRL_SET 0xAD
179 #define POWER_CTRL_CLR 0xAE
180 #define POWER_CTRL_OTG_ENAB (1 << 5)
182 #define OTHER_IFC_CTRL2 0xAF
183 #define OTHER_IFC_CTRL2_SET 0xB0
184 #define OTHER_IFC_CTRL2_CLR 0xB1
185 #define OTHER_IFC_CTRL2_ULPI_STP_LOW (1 << 4)
186 #define OTHER_IFC_CTRL2_ULPI_TXEN_POL (1 << 3)
187 #define OTHER_IFC_CTRL2_ULPI_4PIN_2430 (1 << 2)
188 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_MASK (3 << 0) /* bits 0 and 1 */
189 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT1N (0 << 0)
190 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT2N (1 << 0)
192 #define REG_CTRL_EN 0xB2
193 #define REG_CTRL_EN_SET 0xB3
194 #define REG_CTRL_EN_CLR 0xB4
195 #define REG_CTRL_ERROR 0xB5
196 #define ULPI_I2C_CONFLICT_INTEN (1 << 0)
198 #define OTHER_FUNC_CTRL2 0xB8
199 #define OTHER_FUNC_CTRL2_SET 0xB9
200 #define OTHER_FUNC_CTRL2_CLR 0xBA
201 #define OTHER_FUNC_CTRL2_VBAT_TIMER_EN (1 << 0)
203 /* following registers do not have separate _clr and _set registers */
204 #define VBUS_DEBOUNCE 0xC0
205 #define ID_DEBOUNCE 0xC1
206 #define VBAT_TIMER 0xD3
207 #define PHY_PWR_CTRL 0xFD
208 #define PHY_PWR_PHYPWD (1 << 0)
209 #define PHY_CLK_CTRL 0xFE
210 #define PHY_CLK_CTRL_CLOCKGATING_EN (1 << 2)
211 #define PHY_CLK_CTRL_CLK32K_EN (1 << 1)
212 #define REQ_PHY_DPLL_CLK (1 << 0)
213 #define PHY_CLK_CTRL_STS 0xFF
214 #define PHY_DPLL_CLK (1 << 0)
216 /* In module TWL4030_MODULE_PM_MASTER */
217 #define PROTECT_KEY 0x0E
219 /* In module TWL4030_MODULE_PM_RECEIVER */
220 #define VUSB_DEDICATED1 0x7D
221 #define VUSB_DEDICATED2 0x7E
222 #define VUSB1V5_DEV_GRP 0x71
223 #define VUSB1V5_TYPE 0x72
224 #define VUSB1V5_REMAP 0x73
225 #define VUSB1V8_DEV_GRP 0x74
226 #define VUSB1V8_TYPE 0x75
227 #define VUSB1V8_REMAP 0x76
228 #define VUSB3V1_DEV_GRP 0x77
229 #define VUSB3V1_TYPE 0x78
230 #define VUSB3V1_REMAP 0x79
232 /* In module TWL4030_MODULE_INTBR */
234 #define GPIO_USB_4PIN_ULPI_2430C (3 << 0)
237 /* bits in OTG_CTRL */
238 #define OTG_XCEIV_OUTPUTS \
239 (OTG_ASESSVLD|OTG_BSESSEND|OTG_BSESSVLD|OTG_VBUSVLD|OTG_ID)
240 #define OTG_XCEIV_INPUTS \
241 (OTG_PULLDOWN|OTG_PULLUP|OTG_DRV_VBUS|OTG_PD_VBUS|OTG_PU_VBUS|OTG_PU_ID)
242 #define OTG_CTRL_BITS \
243 (OTG_A_BUSREQ|OTG_A_SETB_HNPEN|OTG_B_BUSREQ|OTG_B_HNPEN|OTG_BUSDROP)
244 /* and OTG_PULLUP is sometimes written */
246 #define OTG_CTRL_MASK (OTG_DRIVER_SEL| \
247 OTG_XCEIV_OUTPUTS|OTG_XCEIV_INPUTS| \
252 USB_LINK_UNKNOWN = 0,
259 struct otg_transceiver otg;
262 /* for vbus reporting with irqs disabled */
265 /* pin configuration */
266 enum twl4030_usb_mode usb_mode;
274 /* internal define on top of container_of */
275 #define xceiv_to_twl(x) container_of((x), struct twl4030_usb, otg);
277 /*-------------------------------------------------------------------------*/
279 static int twl4030_i2c_write_u8_verify(struct twl4030_usb *twl,
280 u8 module, u8 data, u8 address)
284 if ((twl4030_i2c_write_u8(module, data, address) >= 0) &&
285 (twl4030_i2c_read_u8(module, &check, address) >= 0) &&
288 /* Failed once: Try again */
289 if ((twl4030_i2c_write_u8(module, data, address) >= 0) &&
290 (twl4030_i2c_read_u8(module, &check, address) >= 0) &&
293 /* Failed again: Return error */
298 #define twl4030_usb_write_verify(twl, address, data) \
299 twl4030_i2c_write_u8_verify(twl, TWL4030_MODULE_USB, (data), (address))
301 static inline int twl4030_usb_write(struct twl4030_usb *twl,
306 ret = twl4030_i2c_write_u8(TWL4030_MODULE_USB, data, address);
310 if (twl4030_i2c_read_u8(TWL4030_MODULE_USB, &data1,
312 dev_err(twl->dev, "re-read failed\n");
315 "Write %s wrote %x read %x from reg %x\n",
316 (data1 == data) ? "succeed" : "mismatch",
317 data, data1, address);
321 "TWL4030:USB:Write[0x%x] Error %d\n", address, ret);
327 static inline int twl4030_readb(struct twl4030_usb *twl, u8 module, u8 address)
332 ret = twl4030_i2c_read_u8(module, &data, address);
337 "TWL4030:readb[0x%x,0x%x] Error %d\n",
338 module, address, ret);
343 static inline int twl4030_usb_read(struct twl4030_usb *twl, u8 address)
345 return twl4030_readb(twl, TWL4030_MODULE_USB, address);
348 /*-------------------------------------------------------------------------*/
351 twl4030_usb_set_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
353 return twl4030_usb_write(twl, reg + 1, bits);
357 twl4030_usb_clear_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
359 return twl4030_usb_write(twl, reg + 2, bits);
362 /*-------------------------------------------------------------------------*/
364 static enum linkstat twl4030_usb_linkstat(struct twl4030_usb *twl)
367 int linkstat = USB_LINK_UNKNOWN;
369 /* STS_HW_CONDITIONS */
370 status = twl4030_readb(twl, TWL4030_MODULE_PM_MASTER, 0x0f);
372 dev_err(twl->dev, "USB link status err %d\n", status);
373 else if (status & BIT(7))
374 linkstat = USB_LINK_VBUS;
375 else if (status & BIT(2))
376 linkstat = USB_LINK_ID;
378 linkstat = USB_LINK_NONE;
380 dev_dbg(twl->dev, "HW_CONDITIONS 0x%02x/%d; link %d\n",
381 status, status, linkstat);
383 spin_lock_irq(&twl->lock);
384 twl->linkstat = linkstat;
385 if (linkstat == USB_LINK_ID) {
386 twl->otg.default_a = true;
387 twl->otg.state = OTG_STATE_A_IDLE;
389 twl->otg.default_a = false;
390 twl->otg.state = OTG_STATE_B_IDLE;
392 spin_unlock_irq(&twl->lock);
397 static void twl4030_usb_set_mode(struct twl4030_usb *twl, int mode)
399 twl->usb_mode = mode;
402 case T2_USB_MODE_ULPI:
403 twl4030_usb_clear_bits(twl, IFC_CTRL, IFC_CTRL_CARKITMODE);
404 twl4030_usb_set_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
405 twl4030_usb_clear_bits(twl, FUNC_CTRL,
406 FUNC_CTRL_XCVRSELECT_MASK |
407 FUNC_CTRL_OPMODE_MASK);
410 case T2_USB_MODE_CEA2011_3PIN:
411 twl4030_cea2011_3_pin_FS_setup(twl);
415 /* FIXME: power on defaults */
420 static void twl4030_i2c_access(struct twl4030_usb *twl, int on)
422 unsigned long timeout;
423 int val = twl4030_usb_read(twl, PHY_CLK_CTRL);
427 /* enable DPLL to access PHY registers over I2C */
428 val |= REQ_PHY_DPLL_CLK;
429 WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
432 timeout = jiffies + HZ;
433 while (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
435 && time_before(jiffies, timeout))
437 if (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
439 dev_err(twl->dev, "Timeout setting T2 HSUSB "
442 /* let ULPI control the DPLL clock */
443 val &= ~REQ_PHY_DPLL_CLK;
444 WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
450 static void twl4030_phy_power(struct twl4030_usb *twl, int on)
454 pwr = twl4030_usb_read(twl, PHY_PWR_CTRL);
456 pwr &= ~PHY_PWR_PHYPWD;
457 WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0);
458 twl4030_usb_write(twl, PHY_CLK_CTRL,
459 twl4030_usb_read(twl, PHY_CLK_CTRL) |
460 (PHY_CLK_CTRL_CLOCKGATING_EN |
461 PHY_CLK_CTRL_CLK32K_EN));
463 pwr |= PHY_PWR_PHYPWD;
464 WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0);
468 static void twl4030_phy_suspend(struct twl4030_usb *twl, int controller_off)
473 twl4030_phy_power(twl, 0);
477 static void twl4030_phy_resume(struct twl4030_usb *twl)
482 twl4030_phy_power(twl, 1);
483 twl4030_i2c_access(twl, 1);
484 twl4030_usb_set_mode(twl, twl->usb_mode);
485 if (twl->usb_mode == T2_USB_MODE_ULPI)
486 twl4030_i2c_access(twl, 0);
490 static void twl4030_usb_ldo_init(struct twl4030_usb *twl)
492 /* Enable writing to power configuration registers */
493 twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0xC0, PROTECT_KEY);
494 twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x0C, PROTECT_KEY);
496 /* put VUSB3V1 LDO in active state */
497 twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);
499 /* input to VUSB3V1 LDO is from VBAT, not VBUS */
500 twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x14, VUSB_DEDICATED1);
502 /* turn on 3.1V regulator */
503 twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x20, VUSB3V1_DEV_GRP);
504 twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB3V1_TYPE);
506 /* turn on 1.5V regulator */
507 twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x20, VUSB1V5_DEV_GRP);
508 twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB1V5_TYPE);
510 /* turn on 1.8V regulator */
511 twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x20, VUSB1V8_DEV_GRP);
512 twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB1V8_TYPE);
514 /* disable access to power configuration registers */
515 twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0, PROTECT_KEY);
518 static ssize_t twl4030_usb_vbus_show(struct device *dev,
519 struct device_attribute *attr, char *buf)
521 struct twl4030_usb *twl = dev_get_drvdata(dev);
525 spin_lock_irqsave(&twl->lock, flags);
526 ret = sprintf(buf, "%s\n",
527 (twl->linkstat == USB_LINK_VBUS) ? "on" : "off");
528 spin_unlock_irqrestore(&twl->lock, flags);
532 static DEVICE_ATTR(vbus, 0444, twl4030_usb_vbus_show, NULL);
534 static irqreturn_t twl4030_usb_irq(int irq, void *_twl)
536 struct twl4030_usb *twl = _twl;
539 #ifdef CONFIG_LOCKDEP
540 /* WORKAROUND for lockdep forcing IRQF_DISABLED on us, which
541 * we don't want and can't tolerate. Although it might be
542 * friendlier not to borrow this thread context...
547 status = twl4030_usb_linkstat(twl);
548 if (status != USB_LINK_UNKNOWN) {
550 /* FIXME add a set_power() method so that B-devices can
551 * configure the charger appropriately. It's not always
552 * correct to consume VBUS power, and how much current to
553 * consume is a function of the USB configuration chosen
556 * REVISIT usb_gadget_vbus_connect(...) as needed, ditto
557 * its disconnect() sibling, when changing to/from the
558 * USB_LINK_VBUS state. musb_hdrc won't care until it
559 * starts to handle softconnect right.
561 twl4030charger_usb_en(status == USB_LINK_VBUS);
563 if (status == USB_LINK_NONE)
564 twl4030_phy_suspend(twl, 0);
566 twl4030_phy_resume(twl);
568 sysfs_notify(&twl->dev->kobj, NULL, "vbus");
573 static int twl4030_set_suspend(struct otg_transceiver *x, int suspend)
575 struct twl4030_usb *twl = xceiv_to_twl(x);
578 twl4030_phy_suspend(twl, 1);
580 twl4030_phy_resume(twl);
585 static int twl4030_set_peripheral(struct otg_transceiver *x,
586 struct usb_gadget *gadget)
588 struct twl4030_usb *twl;
593 twl = xceiv_to_twl(x);
594 twl->otg.gadget = gadget;
599 static int twl4030_set_host(struct otg_transceiver *x, struct usb_bus *host)
601 struct twl4030_usb *twl;
606 twl = xceiv_to_twl(x);
607 twl->otg.host = host;
612 static int __init twl4030_usb_probe(struct platform_device *pdev)
614 struct twl4030_usb_data *pdata = pdev->dev.platform_data;
615 struct twl4030_usb *twl;
618 twl = kzalloc(sizeof *twl, GFP_KERNEL);
623 dev_info(&pdev->dev, "platform_data not available\n");
627 twl->dev = &pdev->dev;
628 twl->irq = platform_get_irq(pdev, 0);
629 twl->otg.dev = twl->dev;
630 twl->otg.label = "twl4030";
631 twl->otg.set_host = twl4030_set_host;
632 twl->otg.set_peripheral = twl4030_set_peripheral;
633 twl->otg.set_suspend = twl4030_set_suspend;
634 twl->usb_mode = pdata->usb_mode;
637 /* init spinlock for workqueue */
638 spin_lock_init(&twl->lock);
640 twl4030_usb_ldo_init(twl);
641 otg_set_transceiver(&twl->otg);
643 platform_set_drvdata(pdev, twl);
644 if (device_create_file(&pdev->dev, &dev_attr_vbus))
645 dev_warn(&pdev->dev, "could not create sysfs file\n");
647 /* Our job is to use irqs and status from the power module
648 * to keep the transceiver disabled when nothing's connected.
650 * FIXME we actually shouldn't start enabling it until the
651 * USB controller drivers have said they're ready, by calling
652 * set_host() and/or set_peripheral() ... OTG_capable boards
653 * need both handles, otherwise just one suffices.
655 twl->irq_enabled = true;
656 status = request_irq(twl->irq, twl4030_usb_irq,
657 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
660 dev_dbg(&pdev->dev, "can't get IRQ %d, err %d\n",
666 /* The IRQ handler just handles changes from the previous states
667 * of the ID and VBUS pins ... in probe() we must initialize that
668 * previous state. The easy way: fake an IRQ.
670 * REVISIT: a real IRQ might have happened already, if PREEMPT is
671 * enabled. Else the IRQ may not yet be configured or enabled,
672 * because of scheduling delays.
674 twl4030_usb_irq(twl->irq, twl);
676 dev_info(&pdev->dev, "Initialized TWL4030 USB module\n");
680 static int __exit twl4030_usb_remove(struct platform_device *pdev)
682 struct twl4030_usb *twl = platform_get_drvdata(pdev);
685 free_irq(twl->irq, twl);
686 device_remove_file(twl->dev, &dev_attr_vbus);
688 /* set transceiver mode to power on defaults */
689 twl4030_usb_set_mode(twl, -1);
691 /* autogate 60MHz ULPI clock,
692 * clear dpll clock request for i2c access,
695 val = twl4030_usb_read(twl, PHY_CLK_CTRL);
697 val |= PHY_CLK_CTRL_CLOCKGATING_EN;
698 val &= ~(PHY_CLK_CTRL_CLK32K_EN | REQ_PHY_DPLL_CLK);
699 twl4030_usb_write(twl, PHY_CLK_CTRL, (u8)val);
702 /* disable complete OTG block */
703 twl4030_usb_clear_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
705 twl4030_phy_power(twl, 0);
712 static struct platform_driver twl4030_usb_driver = {
713 .probe = twl4030_usb_probe,
714 .remove = __exit_p(twl4030_remove),
716 .name = "twl4030_usb",
717 .owner = THIS_MODULE,
721 static int __init twl4030_usb_init(void)
723 return platform_driver_register(&twl4030_usb_driver);
725 subsys_initcall(twl4030_usb_init);
727 static void __exit twl4030_usb_exit(void)
729 platform_driver_unregister(&twl4030_usb_driver);
731 module_exit(twl4030_usb_exit);
733 MODULE_ALIAS("platform:twl4030_usb");
734 MODULE_AUTHOR("Texas Instruments, Inc, Nokia Corporation");
735 MODULE_DESCRIPTION("TWL4030 USB transceiver driver");
736 MODULE_LICENSE("GPL");