drivers/gpu/drm/radeon/radeon_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include "atom-bits.h"
  32
  33 /* from radeon_encoder.c */
  34 extern uint32_t
  35 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
  36                         uint8_t dac);
  37 extern void radeon_link_encoder_connector(struct drm_device *dev);
  38 extern void
  39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
  40                         uint32_t supported_device, u16 caps);
  41
  42 /* from radeon_connector.c */
  43 extern void
  44 radeon_add_atom_connector(struct drm_device *dev,
  45                           uint32_t connector_id,
  46                           uint32_t supported_device,
  47                           int connector_type,
  48                           struct radeon_i2c_bus_rec *i2c_bus,
  49                           uint32_t igp_lane_info,
  50                           uint16_t connector_object_id,
  51                           struct radeon_hpd *hpd,
  52                           struct radeon_router *router);
  53
  54 /* from radeon_legacy_encoder.c */
  55 extern void
  56 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
  57                           uint32_t supported_device);
  58
  59 union atom_supported_devices {
  60         struct _ATOM_SUPPORTED_DEVICES_INFO info;
  61         struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
  62         struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
  63 };
  64
  65 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
  66                                           ATOM_GPIO_I2C_ASSIGMENT *gpio,
  67                                           u8 index)
  68 {
  69         /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
  70         if ((rdev->family == CHIP_R420) ||
  71             (rdev->family == CHIP_R423) ||
  72             (rdev->family == CHIP_RV410)) {
  73                 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
  74                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
  75                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
  76                         gpio->ucClkMaskShift = 0x19;
  77                         gpio->ucDataMaskShift = 0x18;
  78                 }
  79         }
  80
  81         /* some evergreen boards have bad data for this entry */
  82         if (ASIC_IS_DCE4(rdev)) {
  83                 if ((index == 7) &&
  84                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
  85                     (gpio->sucI2cId.ucAccess == 0)) {
  86                         gpio->sucI2cId.ucAccess = 0x97;
  87                         gpio->ucDataMaskShift = 8;
  88                         gpio->ucDataEnShift = 8;
  89                         gpio->ucDataY_Shift = 8;
  90                         gpio->ucDataA_Shift = 8;
  91                 }
  92         }
  93
  94         /* some DCE3 boards have bad data for this entry */
  95         if (ASIC_IS_DCE3(rdev)) {
  96                 if ((index == 4) &&
  97                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
  98                     (gpio->sucI2cId.ucAccess == 0x94))
  99                         gpio->sucI2cId.ucAccess = 0x14;
 100         }
 101 }
 102
 103 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
 104 {
 105         struct radeon_i2c_bus_rec i2c;
 106
 107         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
 108
 109         i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
 110         i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
 111         i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
 112         i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
 113         i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
 114         i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
 115         i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
 116         i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
 117         i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
 118         i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
 119         i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
 120         i2c.en_data_mask = (1 << gpio->ucDataEnShift);
 121         i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
 122         i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
 123         i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
 124         i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
 125
 126         if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
 127                 i2c.hw_capable = true;
 128         else
 129                 i2c.hw_capable = false;
 130
 131         if (gpio->sucI2cId.ucAccess == 0xa0)
 132                 i2c.mm_i2c = true;
 133         else
 134                 i2c.mm_i2c = false;
 135
 136         i2c.i2c_id = gpio->sucI2cId.ucAccess;
 137
 138         if (i2c.mask_clk_reg)
 139                 i2c.valid = true;
 140         else
 141                 i2c.valid = false;
 142
 143         return i2c;
 144 }
 145
 146 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
 147                                                                uint8_t id)
 148 {
 149         struct atom_context *ctx = rdev->mode_info.atom_context;
 150         ATOM_GPIO_I2C_ASSIGMENT *gpio;
 151         struct radeon_i2c_bus_rec i2c;
 152         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 153         struct _ATOM_GPIO_I2C_INFO *i2c_info;
 154         uint16_t data_offset, size;
 155         int i, num_indices;
 156
 157         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
 158         i2c.valid = false;
 159
 160         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 161                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 162
 163                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 164                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 165
 166                 for (i = 0; i < num_indices; i++) {
 167                         gpio = &i2c_info->asGPIO_Info[i];
 168
 169                         radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
 170
 171                         if (gpio->sucI2cId.ucAccess == id) {
 172                                 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
 173                                 break;
 174                         }
 175                 }
 176         }
 177
 178         return i2c;
 179 }
 180
 181 void radeon_atombios_i2c_init(struct radeon_device *rdev)
 182 {
 183         struct atom_context *ctx = rdev->mode_info.atom_context;
 184         ATOM_GPIO_I2C_ASSIGMENT *gpio;
 185         struct radeon_i2c_bus_rec i2c;
 186         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 187         struct _ATOM_GPIO_I2C_INFO *i2c_info;
 188         uint16_t data_offset, size;
 189         int i, num_indices;
 190         char stmp[32];
 191
 192         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 193                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 194
 195                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 196                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 197
 198                 for (i = 0; i < num_indices; i++) {
 199                         gpio = &i2c_info->asGPIO_Info[i];
 200
 201                         radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
 202
 203                         i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
 204
 205                         if (i2c.valid) {
 206                                 sprintf(stmp, "0x%x", i2c.i2c_id);
 207                                 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
 208                         }
 209                 }
 210         }
 211 }
 212
 213 static struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
 214                                                         u8 id)
 215 {
 216         struct atom_context *ctx = rdev->mode_info.atom_context;
 217         struct radeon_gpio_rec gpio;
 218         int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
 219         struct _ATOM_GPIO_PIN_LUT *gpio_info;
 220         ATOM_GPIO_PIN_ASSIGNMENT *pin;
 221         u16 data_offset, size;
 222         int i, num_indices;
 223
 224         memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
 225         gpio.valid = false;
 226
 227         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 228                 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
 229
 230                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 231                         sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 232
 233                 for (i = 0; i < num_indices; i++) {
 234                         pin = &gpio_info->asGPIO_Pin[i];
 235                         if (id == pin->ucGPIO_ID) {
 236                                 gpio.id = pin->ucGPIO_ID;
 237                                 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
 238                                 gpio.mask = (1 << pin->ucGpioPinBitShift);
 239                                 gpio.valid = true;
 240                                 break;
 241                         }
 242                 }
 243         }
 244
 245         return gpio;
 246 }
 247
 248 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
 249                                                             struct radeon_gpio_rec *gpio)
 250 {
 251         struct radeon_hpd hpd;
 252         u32 reg;
 253
 254         memset(&hpd, 0, sizeof(struct radeon_hpd));
 255
 256         if (ASIC_IS_DCE4(rdev))
 257                 reg = EVERGREEN_DC_GPIO_HPD_A;
 258         else
 259                 reg = AVIVO_DC_GPIO_HPD_A;
 260
 261         hpd.gpio = *gpio;
 262         if (gpio->reg == reg) {
 263                 switch(gpio->mask) {
 264                 case (1 << 0):
 265                         hpd.hpd = RADEON_HPD_1;
 266                         break;
 267                 case (1 << 8):
 268                         hpd.hpd = RADEON_HPD_2;
 269                         break;
 270                 case (1 << 16):
 271                         hpd.hpd = RADEON_HPD_3;
 272                         break;
 273                 case (1 << 24):
 274                         hpd.hpd = RADEON_HPD_4;
 275                         break;
 276                 case (1 << 26):
 277                         hpd.hpd = RADEON_HPD_5;
 278                         break;
 279                 case (1 << 28):
 280                         hpd.hpd = RADEON_HPD_6;
 281                         break;
 282                 default:
 283                         hpd.hpd = RADEON_HPD_NONE;
 284                         break;
 285                 }
 286         } else
 287                 hpd.hpd = RADEON_HPD_NONE;
 288         return hpd;
 289 }
 290
 291 static bool radeon_atom_apply_quirks(struct drm_device *dev,
 292                                      uint32_t supported_device,
 293                                      int *connector_type,
 294                                      struct radeon_i2c_bus_rec *i2c_bus,
 295                                      uint16_t *line_mux,
 296                                      struct radeon_hpd *hpd)
 297 {
 298
 299         /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
 300         if ((dev->pdev->device == 0x791e) &&
 301             (dev->pdev->subsystem_vendor == 0x1043) &&
 302             (dev->pdev->subsystem_device == 0x826d)) {
 303                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 304                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 305                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 306         }
 307
 308         /* Asrock RS600 board lists the DVI port as HDMI */
 309         if ((dev->pdev->device == 0x7941) &&
 310             (dev->pdev->subsystem_vendor == 0x1849) &&
 311             (dev->pdev->subsystem_device == 0x7941)) {
 312                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 313                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 314                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 315         }
 316
 317         /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
 318         if ((dev->pdev->device == 0x796e) &&
 319             (dev->pdev->subsystem_vendor == 0x1462) &&
 320             (dev->pdev->subsystem_device == 0x7302)) {
 321                 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
 322                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 323                         return false;
 324         }
 325
 326         /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
 327         if ((dev->pdev->device == 0x7941) &&
 328             (dev->pdev->subsystem_vendor == 0x147b) &&
 329             (dev->pdev->subsystem_device == 0x2412)) {
 330                 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
 331                         return false;
 332         }
 333
 334         /* Falcon NW laptop lists vga ddc line for LVDS */
 335         if ((dev->pdev->device == 0x5653) &&
 336             (dev->pdev->subsystem_vendor == 0x1462) &&
 337             (dev->pdev->subsystem_device == 0x0291)) {
 338                 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
 339                         i2c_bus->valid = false;
 340                         *line_mux = 53;
 341                 }
 342         }
 343
 344         /* HIS X1300 is DVI+VGA, not DVI+DVI */
 345         if ((dev->pdev->device == 0x7146) &&
 346             (dev->pdev->subsystem_vendor == 0x17af) &&
 347             (dev->pdev->subsystem_device == 0x2058)) {
 348                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 349                         return false;
 350         }
 351
 352         /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
 353         if ((dev->pdev->device == 0x7142) &&
 354             (dev->pdev->subsystem_vendor == 0x1458) &&
 355             (dev->pdev->subsystem_device == 0x2134)) {
 356                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 357                         return false;
 358         }
 359
 360
 361         /* Funky macbooks */
 362         if ((dev->pdev->device == 0x71C5) &&
 363             (dev->pdev->subsystem_vendor == 0x106b) &&
 364             (dev->pdev->subsystem_device == 0x0080)) {
 365                 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
 366                     (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
 367                         return false;
 368                 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
 369                         *line_mux = 0x90;
 370         }
 371
 372         /* mac rv630, rv730, others */
 373         if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
 374             (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
 375                 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
 376                 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
 377         }
 378
 379         /* ASUS HD 3600 XT board lists the DVI port as HDMI */
 380         if ((dev->pdev->device == 0x9598) &&
 381             (dev->pdev->subsystem_vendor == 0x1043) &&
 382             (dev->pdev->subsystem_device == 0x01da)) {
 383                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 384                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 385                 }
 386         }
 387
 388         /* ASUS HD 3600 board lists the DVI port as HDMI */
 389         if ((dev->pdev->device == 0x9598) &&
 390             (dev->pdev->subsystem_vendor == 0x1043) &&
 391             (dev->pdev->subsystem_device == 0x01e4)) {
 392                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 393                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 394                 }
 395         }
 396
 397         /* ASUS HD 3450 board lists the DVI port as HDMI */
 398         if ((dev->pdev->device == 0x95C5) &&
 399             (dev->pdev->subsystem_vendor == 0x1043) &&
 400             (dev->pdev->subsystem_device == 0x01e2)) {
 401                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 402                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 403                 }
 404         }
 405
 406         /* some BIOSes seem to report DAC on HDMI - usually this is a board with
 407          * HDMI + VGA reporting as HDMI
 408          */
 409         if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 410                 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
 411                         *connector_type = DRM_MODE_CONNECTOR_VGA;
 412                         *line_mux = 0;
 413                 }
 414         }
 415
 416         /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
 417          * on the laptop and a DVI port on the docking station and
 418          * both share the same encoder, hpd pin, and ddc line.
 419          * So while the bios table is technically correct,
 420          * we drop the DVI port here since xrandr has no concept of
 421          * encoders and will try and drive both connectors
 422          * with different crtcs which isn't possible on the hardware
 423          * side and leaves no crtcs for LVDS or VGA.
 424          */
 425         if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) &&
 426             (dev->pdev->subsystem_vendor == 0x1025) &&
 427             (dev->pdev->subsystem_device == 0x013c)) {
 428                 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
 429                     (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
 430                         /* actually it's a DVI-D port not DVI-I */
 431                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 432                         return false;
 433                 }
 434         }
 435
 436         /* XFX Pine Group device rv730 reports no VGA DDC lines
 437          * even though they are wired up to record 0x93
 438          */
 439         if ((dev->pdev->device == 0x9498) &&
 440             (dev->pdev->subsystem_vendor == 0x1682) &&
 441             (dev->pdev->subsystem_device == 0x2452) &&
 442             (i2c_bus->valid == false) &&
 443             !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
 444                 struct radeon_device *rdev = dev->dev_private;
 445                 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
 446         }
 447
 448         /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
 449         if (((dev->pdev->device == 0x9802) || (dev->pdev->device == 0x9806)) &&
 450             (dev->pdev->subsystem_vendor == 0x1734) &&
 451             (dev->pdev->subsystem_device == 0x11bd)) {
 452                 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
 453                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 454                         *line_mux = 0x3103;
 455                 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
 456                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 457                 }
 458         }
 459
 460
 461         return true;
 462 }
 463
 464 const int supported_devices_connector_convert[] = {
 465         DRM_MODE_CONNECTOR_Unknown,
 466         DRM_MODE_CONNECTOR_VGA,
 467         DRM_MODE_CONNECTOR_DVII,
 468         DRM_MODE_CONNECTOR_DVID,
 469         DRM_MODE_CONNECTOR_DVIA,
 470         DRM_MODE_CONNECTOR_SVIDEO,
 471         DRM_MODE_CONNECTOR_Composite,
 472         DRM_MODE_CONNECTOR_LVDS,
 473         DRM_MODE_CONNECTOR_Unknown,
 474         DRM_MODE_CONNECTOR_Unknown,
 475         DRM_MODE_CONNECTOR_HDMIA,
 476         DRM_MODE_CONNECTOR_HDMIB,
 477         DRM_MODE_CONNECTOR_Unknown,
 478         DRM_MODE_CONNECTOR_Unknown,
 479         DRM_MODE_CONNECTOR_9PinDIN,
 480         DRM_MODE_CONNECTOR_DisplayPort
 481 };
 482
 483 const uint16_t supported_devices_connector_object_id_convert[] = {
 484         CONNECTOR_OBJECT_ID_NONE,
 485         CONNECTOR_OBJECT_ID_VGA,
 486         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
 487         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
 488         CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
 489         CONNECTOR_OBJECT_ID_COMPOSITE,
 490         CONNECTOR_OBJECT_ID_SVIDEO,
 491         CONNECTOR_OBJECT_ID_LVDS,
 492         CONNECTOR_OBJECT_ID_9PIN_DIN,
 493         CONNECTOR_OBJECT_ID_9PIN_DIN,
 494         CONNECTOR_OBJECT_ID_DISPLAYPORT,
 495         CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
 496         CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
 497         CONNECTOR_OBJECT_ID_SVIDEO
 498 };
 499
 500 const int object_connector_convert[] = {
 501         DRM_MODE_CONNECTOR_Unknown,
 502         DRM_MODE_CONNECTOR_DVII,
 503         DRM_MODE_CONNECTOR_DVII,
 504         DRM_MODE_CONNECTOR_DVID,
 505         DRM_MODE_CONNECTOR_DVID,
 506         DRM_MODE_CONNECTOR_VGA,
 507         DRM_MODE_CONNECTOR_Composite,
 508         DRM_MODE_CONNECTOR_SVIDEO,
 509         DRM_MODE_CONNECTOR_Unknown,
 510         DRM_MODE_CONNECTOR_Unknown,
 511         DRM_MODE_CONNECTOR_9PinDIN,
 512         DRM_MODE_CONNECTOR_Unknown,
 513         DRM_MODE_CONNECTOR_HDMIA,
 514         DRM_MODE_CONNECTOR_HDMIB,
 515         DRM_MODE_CONNECTOR_LVDS,
 516         DRM_MODE_CONNECTOR_9PinDIN,
 517         DRM_MODE_CONNECTOR_Unknown,
 518         DRM_MODE_CONNECTOR_Unknown,
 519         DRM_MODE_CONNECTOR_Unknown,
 520         DRM_MODE_CONNECTOR_DisplayPort,
 521         DRM_MODE_CONNECTOR_eDP,
 522         DRM_MODE_CONNECTOR_Unknown
 523 };
 524
 525 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
 526 {
 527         struct radeon_device *rdev = dev->dev_private;
 528         struct radeon_mode_info *mode_info = &rdev->mode_info;
 529         struct atom_context *ctx = mode_info->atom_context;
 530         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 531         u16 size, data_offset;
 532         u8 frev, crev;
 533         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 534         ATOM_ENCODER_OBJECT_TABLE *enc_obj;
 535         ATOM_OBJECT_TABLE *router_obj;
 536         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 537         ATOM_OBJECT_HEADER *obj_header;
 538         int i, j, k, path_size, device_support;
 539         int connector_type;
 540         u16 igp_lane_info, conn_id, connector_object_id;
 541         struct radeon_i2c_bus_rec ddc_bus;
 542         struct radeon_router router;
 543         struct radeon_gpio_rec gpio;
 544         struct radeon_hpd hpd;
 545
 546         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 547                 return false;
 548
 549         if (crev < 2)
 550                 return false;
 551
 552         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 553         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 554             (ctx->bios + data_offset +
 555              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 556         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 557             (ctx->bios + data_offset +
 558              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 559         enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
 560             (ctx->bios + data_offset +
 561              le16_to_cpu(obj_header->usEncoderObjectTableOffset));
 562         router_obj = (ATOM_OBJECT_TABLE *)
 563                 (ctx->bios + data_offset +
 564                  le16_to_cpu(obj_header->usRouterObjectTableOffset));
 565         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 566
 567         path_size = 0;
 568         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 569                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 570                 ATOM_DISPLAY_OBJECT_PATH *path;
 571                 addr += path_size;
 572                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 573                 path_size += le16_to_cpu(path->usSize);
 574
 575                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 576                         uint8_t con_obj_id, con_obj_num, con_obj_type;
 577
 578                         con_obj_id =
 579                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 580                             >> OBJECT_ID_SHIFT;
 581                         con_obj_num =
 582                             (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 583                             >> ENUM_ID_SHIFT;
 584                         con_obj_type =
 585                             (le16_to_cpu(path->usConnObjectId) &
 586                              OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 587
 588                         /* TODO CV support */
 589                         if (le16_to_cpu(path->usDeviceTag) ==
 590                                 ATOM_DEVICE_CV_SUPPORT)
 591                                 continue;
 592
 593                         /* IGP chips */
 594                         if ((rdev->flags & RADEON_IS_IGP) &&
 595                             (con_obj_id ==
 596                              CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
 597                                 uint16_t igp_offset = 0;
 598                                 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
 599
 600                                 index =
 601                                     GetIndexIntoMasterTable(DATA,
 602                                                             IntegratedSystemInfo);
 603
 604                                 if (atom_parse_data_header(ctx, index, &size, &frev,
 605                                                            &crev, &igp_offset)) {
 606
 607                                         if (crev >= 2) {
 608                                                 igp_obj =
 609                                                         (ATOM_INTEGRATED_SYSTEM_INFO_V2
 610                                                          *) (ctx->bios + igp_offset);
 611
 612                                                 if (igp_obj) {
 613                                                         uint32_t slot_config, ct;
 614
 615                                                         if (con_obj_num == 1)
 616                                                                 slot_config =
 617                                                                         igp_obj->
 618                                                                         ulDDISlot1Config;
 619                                                         else
 620                                                                 slot_config =
 621                                                                         igp_obj->
 622                                                                         ulDDISlot2Config;
 623
 624                                                         ct = (slot_config >> 16) & 0xff;
 625                                                         connector_type =
 626                                                                 object_connector_convert
 627                                                                 [ct];
 628                                                         connector_object_id = ct;
 629                                                         igp_lane_info =
 630                                                                 slot_config & 0xffff;
 631                                                 } else
 632                                                         continue;
 633                                         } else
 634                                                 continue;
 635                                 } else {
 636                                         igp_lane_info = 0;
 637                                         connector_type =
 638                                                 object_connector_convert[con_obj_id];
 639                                         connector_object_id = con_obj_id;
 640                                 }
 641                         } else {
 642                                 igp_lane_info = 0;
 643                                 connector_type =
 644                                     object_connector_convert[con_obj_id];
 645                                 connector_object_id = con_obj_id;
 646                         }
 647
 648                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 649                                 continue;
 650
 651                         router.ddc_valid = false;
 652                         router.cd_valid = false;
 653                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
 654                                 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
 655
 656                                 grph_obj_id =
 657                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 658                                      OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 659                                 grph_obj_num =
 660                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 661                                      ENUM_ID_MASK) >> ENUM_ID_SHIFT;
 662                                 grph_obj_type =
 663                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 664                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 665
 666                                 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 667                                         for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
 668                                                 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
 669                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
 670                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 671                                                                 (ctx->bios + data_offset +
 672                                                                  le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
 673                                                         ATOM_ENCODER_CAP_RECORD *cap_record;
 674                                                         u16 caps = 0;
 675
 676                                                         while (record->ucRecordSize > 0 &&
 677                                                                record->ucRecordType > 0 &&
 678                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 679                                                                 switch (record->ucRecordType) {
 680                                                                 case ATOM_ENCODER_CAP_RECORD_TYPE:
 681                                                                         cap_record =(ATOM_ENCODER_CAP_RECORD *)
 682                                                                                 record;
 683                                                                         caps = le16_to_cpu(cap_record->usEncoderCap);
 684                                                                         break;
 685                                                                 }
 686                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 687                                                                         ((char *)record + record->ucRecordSize);
 688                                                         }
 689                                                         radeon_add_atom_encoder(dev,
 690                                                                                 encoder_obj,
 691                                                                                 le16_to_cpu
 692                                                                                 (path->
 693                                                                                  usDeviceTag),
 694                                                                                 caps);
 695                                                 }
 696                                         }
 697                                 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
 698                                         for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
 699                                                 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
 700                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
 701                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 702                                                                 (ctx->bios + data_offset +
 703                                                                  le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
 704                                                         ATOM_I2C_RECORD *i2c_record;
 705                                                         ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 706                                                         ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
 707                                                         ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
 708                                                         ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
 709                                                                 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
 710                                                                 (ctx->bios + data_offset +
 711                                                                  le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
 712                                                         int enum_id;
 713
 714                                                         router.router_id = router_obj_id;
 715                                                         for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
 716                                                              enum_id++) {
 717                                                                 if (le16_to_cpu(path->usConnObjectId) ==
 718                                                                     le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
 719                                                                         break;
 720                                                         }
 721
 722                                                         while (record->ucRecordSize > 0 &&
 723                                                                record->ucRecordType > 0 &&
 724                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 725                                                                 switch (record->ucRecordType) {
 726                                                                 case ATOM_I2C_RECORD_TYPE:
 727                                                                         i2c_record =
 728                                                                                 (ATOM_I2C_RECORD *)
 729                                                                                 record;
 730                                                                         i2c_config =
 731                                                                                 (ATOM_I2C_ID_CONFIG_ACCESS *)
 732                                                                                 &i2c_record->sucI2cId;
 733                                                                         router.i2c_info =
 734                                                                                 radeon_lookup_i2c_gpio(rdev,
 735                                                                                                        i2c_config->
 736                                                                                                        ucAccess);
 737                                                                         router.i2c_addr = i2c_record->ucI2CAddr >> 1;
 738                                                                         break;
 739                                                                 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
 740                                                                         ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
 741                                                                                 record;
 742                                                                         router.ddc_valid = true;
 743                                                                         router.ddc_mux_type = ddc_path->ucMuxType;
 744                                                                         router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
 745                                                                         router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
 746                                                                         break;
 747                                                                 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
 748                                                                         cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
 749                                                                                 record;
 750                                                                         router.cd_valid = true;
 751                                                                         router.cd_mux_type = cd_path->ucMuxType;
 752                                                                         router.cd_mux_control_pin = cd_path->ucMuxControlPin;
 753                                                                         router.cd_mux_state = cd_path->ucMuxState[enum_id];
 754                                                                         break;
 755                                                                 }
 756                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 757                                                                         ((char *)record + record->ucRecordSize);
 758                                                         }
 759                                                 }
 760                                         }
 761                                 }
 762                         }
 763
 764                         /* look up gpio for ddc, hpd */
 765                         ddc_bus.valid = false;
 766                         hpd.hpd = RADEON_HPD_NONE;
 767                         if ((le16_to_cpu(path->usDeviceTag) &
 768                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
 769                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 770                                         if (le16_to_cpu(path->usConnObjectId) ==
 771                                             le16_to_cpu(con_obj->asObjects[j].
 772                                                         usObjectID)) {
 773                                                 ATOM_COMMON_RECORD_HEADER
 774                                                     *record =
 775                                                     (ATOM_COMMON_RECORD_HEADER
 776                                                      *)
 777                                                     (ctx->bios + data_offset +
 778                                                      le16_to_cpu(con_obj->
 779                                                                  asObjects[j].
 780                                                                  usRecordOffset));
 781                                                 ATOM_I2C_RECORD *i2c_record;
 782                                                 ATOM_HPD_INT_RECORD *hpd_record;
 783                                                 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 784
 785                                                 while (record->ucRecordSize > 0 &&
 786                                                        record->ucRecordType > 0 &&
 787                                                        record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 788                                                         switch (record->ucRecordType) {
 789                                                         case ATOM_I2C_RECORD_TYPE:
 790                                                                 i2c_record =
 791                                                                     (ATOM_I2C_RECORD *)
 792                                                                         record;
 793                                                                 i2c_config =
 794                                                                         (ATOM_I2C_ID_CONFIG_ACCESS *)
 795                                                                         &i2c_record->sucI2cId;
 796                                                                 ddc_bus = radeon_lookup_i2c_gpio(rdev,
 797                                                                                                  i2c_config->
 798                                                                                                  ucAccess);
 799                                                                 break;
 800                                                         case ATOM_HPD_INT_RECORD_TYPE:
 801                                                                 hpd_record =
 802                                                                         (ATOM_HPD_INT_RECORD *)
 803                                                                         record;
 804                                                                 gpio = radeon_lookup_gpio(rdev,
 805                                                                                           hpd_record->ucHPDIntGPIOID);
 806                                                                 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
 807                                                                 hpd.plugged_state = hpd_record->ucPlugged_PinState;
 808                                                                 break;
 809                                                         }
 810                                                         record =
 811                                                             (ATOM_COMMON_RECORD_HEADER
 812                                                              *) ((char *)record
 813                                                                  +
 814                                                                  record->
 815                                                                  ucRecordSize);
 816                                                 }
 817                                                 break;
 818                                         }
 819                                 }
 820                         }
 821
 822                         /* needed for aux chan transactions */
 823                         ddc_bus.hpd = hpd.hpd;
 824
 825                         conn_id = le16_to_cpu(path->usConnObjectId);
 826
 827                         if (!radeon_atom_apply_quirks
 828                             (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
 829                              &ddc_bus, &conn_id, &hpd))
 830                                 continue;
 831
 832                         radeon_add_atom_connector(dev,
 833                                                   conn_id,
 834                                                   le16_to_cpu(path->
 835                                                               usDeviceTag),
 836                                                   connector_type, &ddc_bus,
 837                                                   igp_lane_info,
 838                                                   connector_object_id,
 839                                                   &hpd,
 840                                                   &router);
 841
 842                 }
 843         }
 844
 845         radeon_link_encoder_connector(dev);
 846
 847         return true;
 848 }
 849
 850 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
 851                                                  int connector_type,
 852                                                  uint16_t devices)
 853 {
 854         struct radeon_device *rdev = dev->dev_private;
 855
 856         if (rdev->flags & RADEON_IS_IGP) {
 857                 return supported_devices_connector_object_id_convert
 858                         [connector_type];
 859         } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
 860                     (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
 861                    (devices & ATOM_DEVICE_DFP2_SUPPORT))  {
 862                 struct radeon_mode_info *mode_info = &rdev->mode_info;
 863                 struct atom_context *ctx = mode_info->atom_context;
 864                 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
 865                 uint16_t size, data_offset;
 866                 uint8_t frev, crev;
 867                 ATOM_XTMDS_INFO *xtmds;
 868
 869                 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
 870                         xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
 871
 872                         if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
 873                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 874                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
 875                                 else
 876                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
 877                         } else {
 878                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 879                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
 880                                 else
 881                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
 882                         }
 883                 } else
 884                         return supported_devices_connector_object_id_convert
 885                                 [connector_type];
 886         } else {
 887                 return supported_devices_connector_object_id_convert
 888                         [connector_type];
 889         }
 890 }
 891
 892 struct bios_connector {
 893         bool valid;
 894         uint16_t line_mux;
 895         uint16_t devices;
 896         int connector_type;
 897         struct radeon_i2c_bus_rec ddc_bus;
 898         struct radeon_hpd hpd;
 899 };
 900
 901 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
 902                                                                  drm_device
 903                                                                  *dev)
 904 {
 905         struct radeon_device *rdev = dev->dev_private;
 906         struct radeon_mode_info *mode_info = &rdev->mode_info;
 907         struct atom_context *ctx = mode_info->atom_context;
 908         int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
 909         uint16_t size, data_offset;
 910         uint8_t frev, crev;
 911         uint16_t device_support;
 912         uint8_t dac;
 913         union atom_supported_devices *supported_devices;
 914         int i, j, max_device;
 915         struct bios_connector *bios_connectors;
 916         size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
 917         struct radeon_router router;
 918
 919         router.ddc_valid = false;
 920         router.cd_valid = false;
 921
 922         bios_connectors = kzalloc(bc_size, GFP_KERNEL);
 923         if (!bios_connectors)
 924                 return false;
 925
 926         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
 927                                     &data_offset)) {
 928                 kfree(bios_connectors);
 929                 return false;
 930         }
 931
 932         supported_devices =
 933             (union atom_supported_devices *)(ctx->bios + data_offset);
 934
 935         device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
 936
 937         if (frev > 1)
 938                 max_device = ATOM_MAX_SUPPORTED_DEVICE;
 939         else
 940                 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
 941
 942         for (i = 0; i < max_device; i++) {
 943                 ATOM_CONNECTOR_INFO_I2C ci =
 944                     supported_devices->info.asConnInfo[i];
 945
 946                 bios_connectors[i].valid = false;
 947
 948                 if (!(device_support & (1 << i))) {
 949                         continue;
 950                 }
 951
 952                 if (i == ATOM_DEVICE_CV_INDEX) {
 953                         DRM_DEBUG_KMS("Skipping Component Video\n");
 954                         continue;
 955                 }
 956
 957                 bios_connectors[i].connector_type =
 958                     supported_devices_connector_convert[ci.sucConnectorInfo.
 959                                                         sbfAccess.
 960                                                         bfConnectorType];
 961
 962                 if (bios_connectors[i].connector_type ==
 963                     DRM_MODE_CONNECTOR_Unknown)
 964                         continue;
 965
 966                 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
 967
 968                 bios_connectors[i].line_mux =
 969                         ci.sucI2cId.ucAccess;
 970
 971                 /* give tv unique connector ids */
 972                 if (i == ATOM_DEVICE_TV1_INDEX) {
 973                         bios_connectors[i].ddc_bus.valid = false;
 974                         bios_connectors[i].line_mux = 50;
 975                 } else if (i == ATOM_DEVICE_TV2_INDEX) {
 976                         bios_connectors[i].ddc_bus.valid = false;
 977                         bios_connectors[i].line_mux = 51;
 978                 } else if (i == ATOM_DEVICE_CV_INDEX) {
 979                         bios_connectors[i].ddc_bus.valid = false;
 980                         bios_connectors[i].line_mux = 52;
 981                 } else
 982                         bios_connectors[i].ddc_bus =
 983                             radeon_lookup_i2c_gpio(rdev,
 984                                                    bios_connectors[i].line_mux);
 985
 986                 if ((crev > 1) && (frev > 1)) {
 987                         u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
 988                         switch (isb) {
 989                         case 0x4:
 990                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 991                                 break;
 992                         case 0xa:
 993                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 994                                 break;
 995                         default:
 996                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 997                                 break;
 998                         }
 999                 } else {
1000                         if (i == ATOM_DEVICE_DFP1_INDEX)
1001                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
1002                         else if (i == ATOM_DEVICE_DFP2_INDEX)
1003                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1004                         else
1005                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1006                 }
1007
1008                 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1009                  * shared with a DVI port, we'll pick up the DVI connector when we
1010                  * merge the outputs.  Some bioses incorrectly list VGA ports as DVI.
1011                  */
1012                 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1013                         bios_connectors[i].connector_type =
1014                             DRM_MODE_CONNECTOR_VGA;
1015
1016                 if (!radeon_atom_apply_quirks
1017                     (dev, (1 << i), &bios_connectors[i].connector_type,
1018                      &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1019                      &bios_connectors[i].hpd))
1020                         continue;
1021
1022                 bios_connectors[i].valid = true;
1023                 bios_connectors[i].devices = (1 << i);
1024
1025                 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1026                         radeon_add_atom_encoder(dev,
1027                                                 radeon_get_encoder_enum(dev,
1028                                                                       (1 << i),
1029                                                                       dac),
1030                                                 (1 << i),
1031                                                 0);
1032                 else
1033                         radeon_add_legacy_encoder(dev,
1034                                                   radeon_get_encoder_enum(dev,
1035                                                                         (1 << i),
1036                                                                         dac),
1037                                                   (1 << i));
1038         }
1039
1040         /* combine shared connectors */
1041         for (i = 0; i < max_device; i++) {
1042                 if (bios_connectors[i].valid) {
1043                         for (j = 0; j < max_device; j++) {
1044                                 if (bios_connectors[j].valid && (i != j)) {
1045                                         if (bios_connectors[i].line_mux ==
1046                                             bios_connectors[j].line_mux) {
1047                                                 /* make sure not to combine LVDS */
1048                                                 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1049                                                         bios_connectors[i].line_mux = 53;
1050                                                         bios_connectors[i].ddc_bus.valid = false;
1051                                                         continue;
1052                                                 }
1053                                                 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1054                                                         bios_connectors[j].line_mux = 53;
1055                                                         bios_connectors[j].ddc_bus.valid = false;
1056                                                         continue;
1057                                                 }
1058                                                 /* combine analog and digital for DVI-I */
1059                                                 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1060                                                      (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1061                                                     ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1062                                                      (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1063                                                         bios_connectors[i].devices |=
1064                                                                 bios_connectors[j].devices;
1065                                                         bios_connectors[i].connector_type =
1066                                                                 DRM_MODE_CONNECTOR_DVII;
1067                                                         if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1068                                                                 bios_connectors[i].hpd =
1069                                                                         bios_connectors[j].hpd;
1070                                                         bios_connectors[j].valid = false;
1071                                                 }
1072                                         }
1073                                 }
1074                         }
1075                 }
1076         }
1077
1078         /* add the connectors */
1079         for (i = 0; i < max_device; i++) {
1080                 if (bios_connectors[i].valid) {
1081                         uint16_t connector_object_id =
1082                                 atombios_get_connector_object_id(dev,
1083                                                       bios_connectors[i].connector_type,
1084                                                       bios_connectors[i].devices);
1085                         radeon_add_atom_connector(dev,
1086                                                   bios_connectors[i].line_mux,
1087                                                   bios_connectors[i].devices,
1088                                                   bios_connectors[i].
1089                                                   connector_type,
1090                                                   &bios_connectors[i].ddc_bus,
1091                                                   0,
1092                                                   connector_object_id,
1093                                                   &bios_connectors[i].hpd,
1094                                                   &router);
1095                 }
1096         }
1097
1098         radeon_link_encoder_connector(dev);
1099
1100         kfree(bios_connectors);
1101         return true;
1102 }
1103
1104 union firmware_info {
1105         ATOM_FIRMWARE_INFO info;
1106         ATOM_FIRMWARE_INFO_V1_2 info_12;
1107         ATOM_FIRMWARE_INFO_V1_3 info_13;
1108         ATOM_FIRMWARE_INFO_V1_4 info_14;
1109         ATOM_FIRMWARE_INFO_V2_1 info_21;
1110         ATOM_FIRMWARE_INFO_V2_2 info_22;
1111 };
1112
1113 bool radeon_atom_get_clock_info(struct drm_device *dev)
1114 {
1115         struct radeon_device *rdev = dev->dev_private;
1116         struct radeon_mode_info *mode_info = &rdev->mode_info;
1117         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1118         union firmware_info *firmware_info;
1119         uint8_t frev, crev;
1120         struct radeon_pll *p1pll = &rdev->clock.p1pll;
1121         struct radeon_pll *p2pll = &rdev->clock.p2pll;
1122         struct radeon_pll *dcpll = &rdev->clock.dcpll;
1123         struct radeon_pll *spll = &rdev->clock.spll;
1124         struct radeon_pll *mpll = &rdev->clock.mpll;
1125         uint16_t data_offset;
1126
1127         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1128                                    &frev, &crev, &data_offset)) {
1129                 firmware_info =
1130                         (union firmware_info *)(mode_info->atom_context->bios +
1131                                                 data_offset);
1132                 /* pixel clocks */
1133                 p1pll->reference_freq =
1134                     le16_to_cpu(firmware_info->info.usReferenceClock);
1135                 p1pll->reference_div = 0;
1136
1137                 if (crev < 2)
1138                         p1pll->pll_out_min =
1139                                 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1140                 else
1141                         p1pll->pll_out_min =
1142                                 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1143                 p1pll->pll_out_max =
1144                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1145
1146                 if (crev >= 4) {
1147                         p1pll->lcd_pll_out_min =
1148                                 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1149                         if (p1pll->lcd_pll_out_min == 0)
1150                                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1151                         p1pll->lcd_pll_out_max =
1152                                 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1153                         if (p1pll->lcd_pll_out_max == 0)
1154                                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1155                 } else {
1156                         p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1157                         p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1158                 }
1159
1160                 if (p1pll->pll_out_min == 0) {
1161                         if (ASIC_IS_AVIVO(rdev))
1162                                 p1pll->pll_out_min = 64800;
1163                         else
1164                                 p1pll->pll_out_min = 20000;
1165                 }
1166
1167                 p1pll->pll_in_min =
1168                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1169                 p1pll->pll_in_max =
1170                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1171
1172                 *p2pll = *p1pll;
1173
1174                 /* system clock */
1175                 if (ASIC_IS_DCE4(rdev))
1176                         spll->reference_freq =
1177                                 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1178                 else
1179                         spll->reference_freq =
1180                                 le16_to_cpu(firmware_info->info.usReferenceClock);
1181                 spll->reference_div = 0;
1182
1183                 spll->pll_out_min =
1184                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1185                 spll->pll_out_max =
1186                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1187
1188                 /* ??? */
1189                 if (spll->pll_out_min == 0) {
1190                         if (ASIC_IS_AVIVO(rdev))
1191                                 spll->pll_out_min = 64800;
1192                         else
1193                                 spll->pll_out_min = 20000;
1194                 }
1195
1196                 spll->pll_in_min =
1197                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1198                 spll->pll_in_max =
1199                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1200
1201                 /* memory clock */
1202                 if (ASIC_IS_DCE4(rdev))
1203                         mpll->reference_freq =
1204                                 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1205                 else
1206                         mpll->reference_freq =
1207                                 le16_to_cpu(firmware_info->info.usReferenceClock);
1208                 mpll->reference_div = 0;
1209
1210                 mpll->pll_out_min =
1211                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1212                 mpll->pll_out_max =
1213                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1214
1215                 /* ??? */
1216                 if (mpll->pll_out_min == 0) {
1217                         if (ASIC_IS_AVIVO(rdev))
1218                                 mpll->pll_out_min = 64800;
1219                         else
1220                                 mpll->pll_out_min = 20000;
1221                 }
1222
1223                 mpll->pll_in_min =
1224                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1225                 mpll->pll_in_max =
1226                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1227
1228                 rdev->clock.default_sclk =
1229                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1230                 rdev->clock.default_mclk =
1231                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1232
1233                 if (ASIC_IS_DCE4(rdev)) {
1234                         rdev->clock.default_dispclk =
1235                                 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1236                         if (rdev->clock.default_dispclk == 0) {
1237                                 if (ASIC_IS_DCE5(rdev))
1238                                         rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1239                                 else
1240                                         rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1241                         }
1242                         rdev->clock.dp_extclk =
1243                                 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1244                 }
1245                 *dcpll = *p1pll;
1246
1247                 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1248                 if (rdev->clock.max_pixel_clock == 0)
1249                         rdev->clock.max_pixel_clock = 40000;
1250
1251                 return true;
1252         }
1253
1254         return false;
1255 }
1256
1257 union igp_info {
1258         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1259         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1260 };
1261
1262 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1263 {
1264         struct radeon_mode_info *mode_info = &rdev->mode_info;
1265         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1266         union igp_info *igp_info;
1267         u8 frev, crev;
1268         u16 data_offset;
1269
1270         /* sideport is AMD only */
1271         if (rdev->family == CHIP_RS600)
1272                 return false;
1273
1274         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1275                                    &frev, &crev, &data_offset)) {
1276                 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1277                                       data_offset);
1278                 switch (crev) {
1279                 case 1:
1280                         if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1281                                 return true;
1282                         break;
1283                 case 2:
1284                         if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1285                                 return true;
1286                         break;
1287                 default:
1288                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1289                         break;
1290                 }
1291         }
1292         return false;
1293 }
1294
1295 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1296                                    struct radeon_encoder_int_tmds *tmds)
1297 {
1298         struct drm_device *dev = encoder->base.dev;
1299         struct radeon_device *rdev = dev->dev_private;
1300         struct radeon_mode_info *mode_info = &rdev->mode_info;
1301         int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1302         uint16_t data_offset;
1303         struct _ATOM_TMDS_INFO *tmds_info;
1304         uint8_t frev, crev;
1305         uint16_t maxfreq;
1306         int i;
1307
1308         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1309                                    &frev, &crev, &data_offset)) {
1310                 tmds_info =
1311                         (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1312                                                    data_offset);
1313
1314                 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1315                 for (i = 0; i < 4; i++) {
1316                         tmds->tmds_pll[i].freq =
1317                             le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1318                         tmds->tmds_pll[i].value =
1319                             tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1320                         tmds->tmds_pll[i].value |=
1321                             (tmds_info->asMiscInfo[i].
1322                              ucPLL_VCO_Gain & 0x3f) << 6;
1323                         tmds->tmds_pll[i].value |=
1324                             (tmds_info->asMiscInfo[i].
1325                              ucPLL_DutyCycle & 0xf) << 12;
1326                         tmds->tmds_pll[i].value |=
1327                             (tmds_info->asMiscInfo[i].
1328                              ucPLL_VoltageSwing & 0xf) << 16;
1329
1330                         DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1331                                   tmds->tmds_pll[i].freq,
1332                                   tmds->tmds_pll[i].value);
1333
1334                         if (maxfreq == tmds->tmds_pll[i].freq) {
1335                                 tmds->tmds_pll[i].freq = 0xffffffff;
1336                                 break;
1337                         }
1338                 }
1339                 return true;
1340         }
1341         return false;
1342 }
1343
1344 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1345                                       struct radeon_atom_ss *ss,
1346                                       int id)
1347 {
1348         struct radeon_mode_info *mode_info = &rdev->mode_info;
1349         int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1350         uint16_t data_offset, size;
1351         struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1352         uint8_t frev, crev;
1353         int i, num_indices;
1354
1355         memset(ss, 0, sizeof(struct radeon_atom_ss));
1356         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1357                                    &frev, &crev, &data_offset)) {
1358                 ss_info =
1359                         (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1360
1361                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1362                         sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1363
1364                 for (i = 0; i < num_indices; i++) {
1365                         if (ss_info->asSS_Info[i].ucSS_Id == id) {
1366                                 ss->percentage =
1367                                         le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1368                                 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1369                                 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1370                                 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1371                                 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1372                                 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1373                                 return true;
1374                         }
1375                 }
1376         }
1377         return false;
1378 }
1379
1380 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1381                                                  struct radeon_atom_ss *ss,
1382                                                  int id)
1383 {
1384         struct radeon_mode_info *mode_info = &rdev->mode_info;
1385         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1386         u16 data_offset, size;
1387         struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *igp_info;
1388         u8 frev, crev;
1389         u16 percentage = 0, rate = 0;
1390
1391         /* get any igp specific overrides */
1392         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1393                                    &frev, &crev, &data_offset)) {
1394                 igp_info = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *)
1395                         (mode_info->atom_context->bios + data_offset);
1396                 switch (id) {
1397                 case ASIC_INTERNAL_SS_ON_TMDS:
1398                         percentage = le16_to_cpu(igp_info->usDVISSPercentage);
1399                         rate = le16_to_cpu(igp_info->usDVISSpreadRateIn10Hz);
1400                         break;
1401                 case ASIC_INTERNAL_SS_ON_HDMI:
1402                         percentage = le16_to_cpu(igp_info->usHDMISSPercentage);
1403                         rate = le16_to_cpu(igp_info->usHDMISSpreadRateIn10Hz);
1404                         break;
1405                 case ASIC_INTERNAL_SS_ON_LVDS:
1406                         percentage = le16_to_cpu(igp_info->usLvdsSSPercentage);
1407                         rate = le16_to_cpu(igp_info->usLvdsSSpreadRateIn10Hz);
1408                         break;
1409                 }
1410                 if (percentage)
1411                         ss->percentage = percentage;
1412                 if (rate)
1413                         ss->rate = rate;
1414         }
1415 }
1416
1417 union asic_ss_info {
1418         struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1419         struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1420         struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1421 };
1422
1423 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1424                                       struct radeon_atom_ss *ss,
1425                                       int id, u32 clock)
1426 {
1427         struct radeon_mode_info *mode_info = &rdev->mode_info;
1428         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1429         uint16_t data_offset, size;
1430         union asic_ss_info *ss_info;
1431         uint8_t frev, crev;
1432         int i, num_indices;
1433
1434         memset(ss, 0, sizeof(struct radeon_atom_ss));
1435         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1436                                    &frev, &crev, &data_offset)) {
1437
1438                 ss_info =
1439                         (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1440
1441                 switch (frev) {
1442                 case 1:
1443                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1444                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1445
1446                         for (i = 0; i < num_indices; i++) {
1447                                 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
1448                                     (clock <= le32_to_cpu(ss_info->info.asSpreadSpectrum[i].ulTargetClockRange))) {
1449                                         ss->percentage =
1450                                                 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1451                                         ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1452                                         ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1453                                         return true;
1454                                 }
1455                         }
1456                         break;
1457                 case 2:
1458                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1459                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1460                         for (i = 0; i < num_indices; i++) {
1461                                 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
1462                                     (clock <= le32_to_cpu(ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange))) {
1463                                         ss->percentage =
1464                                                 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1465                                         ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1466                                         ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1467                                         return true;
1468                                 }
1469                         }
1470                         break;
1471                 case 3:
1472                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1473                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1474                         for (i = 0; i < num_indices; i++) {
1475                                 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
1476                                     (clock <= le32_to_cpu(ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange))) {
1477                                         ss->percentage =
1478                                                 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1479                                         ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1480                                         ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1481                                         if (rdev->flags & RADEON_IS_IGP)
1482                                                 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1483                                         return true;
1484                                 }
1485                         }
1486                         break;
1487                 default:
1488                         DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1489                         break;
1490                 }
1491
1492         }
1493         return false;
1494 }
1495
1496 union lvds_info {
1497         struct _ATOM_LVDS_INFO info;
1498         struct _ATOM_LVDS_INFO_V12 info_12;
1499 };
1500
1501 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1502                                                               radeon_encoder
1503                                                               *encoder)
1504 {
1505         struct drm_device *dev = encoder->base.dev;
1506         struct radeon_device *rdev = dev->dev_private;
1507         struct radeon_mode_info *mode_info = &rdev->mode_info;
1508         int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1509         uint16_t data_offset, misc;
1510         union lvds_info *lvds_info;
1511         uint8_t frev, crev;
1512         struct radeon_encoder_atom_dig *lvds = NULL;
1513         int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1514
1515         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1516                                    &frev, &crev, &data_offset)) {
1517                 lvds_info =
1518                         (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1519                 lvds =
1520                     kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1521
1522                 if (!lvds)
1523                         return NULL;
1524
1525                 lvds->native_mode.clock =
1526                     le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1527                 lvds->native_mode.hdisplay =
1528                     le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1529                 lvds->native_mode.vdisplay =
1530                     le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1531                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1532                         le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1533                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1534                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1535                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1536                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1537                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1538                         le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1539                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1540                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1541                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1542                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1543                 lvds->panel_pwr_delay =
1544                     le16_to_cpu(lvds_info->info.usOffDelayInMs);
1545                 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1546
1547                 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1548                 if (misc & ATOM_VSYNC_POLARITY)
1549                         lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1550                 if (misc & ATOM_HSYNC_POLARITY)
1551                         lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1552                 if (misc & ATOM_COMPOSITESYNC)
1553                         lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1554                 if (misc & ATOM_INTERLACE)
1555                         lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1556                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1557                         lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1558
1559                 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1560                 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1561
1562                 /* set crtc values */
1563                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1564
1565                 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1566
1567                 encoder->native_mode = lvds->native_mode;
1568
1569                 if (encoder_enum == 2)
1570                         lvds->linkb = true;
1571                 else
1572                         lvds->linkb = false;
1573
1574                 /* parse the lcd record table */
1575                 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1576                         ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1577                         ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1578                         bool bad_record = false;
1579                         u8 *record;
1580
1581                         if ((frev == 1) && (crev < 2))
1582                                 /* absolute */
1583                                 record = (u8 *)(mode_info->atom_context->bios +
1584                                                 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1585                         else
1586                                 /* relative */
1587                                 record = (u8 *)(mode_info->atom_context->bios +
1588                                                 data_offset +
1589                                                 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1590                         while (*record != ATOM_RECORD_END_TYPE) {
1591                                 switch (*record) {
1592                                 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1593                                         record += sizeof(ATOM_PATCH_RECORD_MODE);
1594                                         break;
1595                                 case LCD_RTS_RECORD_TYPE:
1596                                         record += sizeof(ATOM_LCD_RTS_RECORD);
1597                                         break;
1598                                 case LCD_CAP_RECORD_TYPE:
1599                                         record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1600                                         break;
1601                                 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1602                                         fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1603                                         if (fake_edid_record->ucFakeEDIDLength) {
1604                                                 struct edid *edid;
1605                                                 int edid_size =
1606                                                         max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1607                                                 edid = kmalloc(edid_size, GFP_KERNEL);
1608                                                 if (edid) {
1609                                                         memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1610                                                                fake_edid_record->ucFakeEDIDLength);
1611
1612                                                         if (drm_edid_is_valid(edid)) {
1613                                                                 rdev->mode_info.bios_hardcoded_edid = edid;
1614                                                                 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1615                                                         } else
1616                                                                 kfree(edid);
1617                                                 }
1618                                         }
1619                                         record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1620                                         break;
1621                                 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1622                                         panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1623                                         lvds->native_mode.width_mm = panel_res_record->usHSize;
1624                                         lvds->native_mode.height_mm = panel_res_record->usVSize;
1625                                         record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1626                                         break;
1627                                 default:
1628                                         DRM_ERROR("Bad LCD record %d\n", *record);
1629                                         bad_record = true;
1630                                         break;
1631                                 }
1632                                 if (bad_record)
1633                                         break;
1634                         }
1635                 }
1636         }
1637         return lvds;
1638 }
1639
1640 struct radeon_encoder_primary_dac *
1641 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1642 {
1643         struct drm_device *dev = encoder->base.dev;
1644         struct radeon_device *rdev = dev->dev_private;
1645         struct radeon_mode_info *mode_info = &rdev->mode_info;
1646         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1647         uint16_t data_offset;
1648         struct _COMPASSIONATE_DATA *dac_info;
1649         uint8_t frev, crev;
1650         uint8_t bg, dac;
1651         struct radeon_encoder_primary_dac *p_dac = NULL;
1652
1653         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1654                                    &frev, &crev, &data_offset)) {
1655                 dac_info = (struct _COMPASSIONATE_DATA *)
1656                         (mode_info->atom_context->bios + data_offset);
1657
1658                 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1659
1660                 if (!p_dac)
1661                         return NULL;
1662
1663                 bg = dac_info->ucDAC1_BG_Adjustment;
1664                 dac = dac_info->ucDAC1_DAC_Adjustment;
1665                 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1666
1667         }
1668         return p_dac;
1669 }
1670
1671 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1672                                 struct drm_display_mode *mode)
1673 {
1674         struct radeon_mode_info *mode_info = &rdev->mode_info;
1675         ATOM_ANALOG_TV_INFO *tv_info;
1676         ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1677         ATOM_DTD_FORMAT *dtd_timings;
1678         int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1679         u8 frev, crev;
1680         u16 data_offset, misc;
1681
1682         if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1683                                     &frev, &crev, &data_offset))
1684                 return false;
1685
1686         switch (crev) {
1687         case 1:
1688                 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1689                 if (index >= MAX_SUPPORTED_TV_TIMING)
1690                         return false;
1691
1692                 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1693                 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1694                 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1695                 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1696                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1697
1698                 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1699                 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1700                 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1701                 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1702                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1703
1704                 mode->flags = 0;
1705                 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1706                 if (misc & ATOM_VSYNC_POLARITY)
1707                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1708                 if (misc & ATOM_HSYNC_POLARITY)
1709                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1710                 if (misc & ATOM_COMPOSITESYNC)
1711                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1712                 if (misc & ATOM_INTERLACE)
1713                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1714                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1715                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1716
1717                 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1718
1719                 if (index == 1) {
1720                         /* PAL timings appear to have wrong values for totals */
1721                         mode->crtc_htotal -= 1;
1722                         mode->crtc_vtotal -= 1;
1723                 }
1724                 break;
1725         case 2:
1726                 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1727                 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1728                         return false;
1729
1730                 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1731                 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1732                         le16_to_cpu(dtd_timings->usHBlanking_Time);
1733                 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1734                 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1735                         le16_to_cpu(dtd_timings->usHSyncOffset);
1736                 mode->crtc_hsync_end = mode->crtc_hsync_start +
1737                         le16_to_cpu(dtd_timings->usHSyncWidth);
1738
1739                 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1740                         le16_to_cpu(dtd_timings->usVBlanking_Time);
1741                 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1742                 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1743                         le16_to_cpu(dtd_timings->usVSyncOffset);
1744                 mode->crtc_vsync_end = mode->crtc_vsync_start +
1745                         le16_to_cpu(dtd_timings->usVSyncWidth);
1746
1747                 mode->flags = 0;
1748                 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1749                 if (misc & ATOM_VSYNC_POLARITY)
1750                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1751                 if (misc & ATOM_HSYNC_POLARITY)
1752                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1753                 if (misc & ATOM_COMPOSITESYNC)
1754                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1755                 if (misc & ATOM_INTERLACE)
1756                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1757                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1758                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1759
1760                 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1761                 break;
1762         }
1763         return true;
1764 }
1765
1766 enum radeon_tv_std
1767 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1768 {
1769         struct radeon_mode_info *mode_info = &rdev->mode_info;
1770         int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1771         uint16_t data_offset;
1772         uint8_t frev, crev;
1773         struct _ATOM_ANALOG_TV_INFO *tv_info;
1774         enum radeon_tv_std tv_std = TV_STD_NTSC;
1775
1776         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1777                                    &frev, &crev, &data_offset)) {
1778
1779                 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1780                         (mode_info->atom_context->bios + data_offset);
1781
1782                 switch (tv_info->ucTV_BootUpDefaultStandard) {
1783                 case ATOM_TV_NTSC:
1784                         tv_std = TV_STD_NTSC;
1785                         DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1786                         break;
1787                 case ATOM_TV_NTSCJ:
1788                         tv_std = TV_STD_NTSC_J;
1789                         DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1790                         break;
1791                 case ATOM_TV_PAL:
1792                         tv_std = TV_STD_PAL;
1793                         DRM_DEBUG_KMS("Default TV standard: PAL\n");
1794                         break;
1795                 case ATOM_TV_PALM:
1796                         tv_std = TV_STD_PAL_M;
1797                         DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1798                         break;
1799                 case ATOM_TV_PALN:
1800                         tv_std = TV_STD_PAL_N;
1801                         DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1802                         break;
1803                 case ATOM_TV_PALCN:
1804                         tv_std = TV_STD_PAL_CN;
1805                         DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1806                         break;
1807                 case ATOM_TV_PAL60:
1808                         tv_std = TV_STD_PAL_60;
1809                         DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1810                         break;
1811                 case ATOM_TV_SECAM:
1812                         tv_std = TV_STD_SECAM;
1813                         DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1814                         break;
1815                 default:
1816                         tv_std = TV_STD_NTSC;
1817                         DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1818                         break;
1819                 }
1820         }
1821         return tv_std;
1822 }
1823
1824 struct radeon_encoder_tv_dac *
1825 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1826 {
1827         struct drm_device *dev = encoder->base.dev;
1828         struct radeon_device *rdev = dev->dev_private;
1829         struct radeon_mode_info *mode_info = &rdev->mode_info;
1830         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1831         uint16_t data_offset;
1832         struct _COMPASSIONATE_DATA *dac_info;
1833         uint8_t frev, crev;
1834         uint8_t bg, dac;
1835         struct radeon_encoder_tv_dac *tv_dac = NULL;
1836
1837         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1838                                    &frev, &crev, &data_offset)) {
1839
1840                 dac_info = (struct _COMPASSIONATE_DATA *)
1841                         (mode_info->atom_context->bios + data_offset);
1842
1843                 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1844
1845                 if (!tv_dac)
1846                         return NULL;
1847
1848                 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1849                 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1850                 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1851
1852                 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1853                 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1854                 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1855
1856                 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1857                 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1858                 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1859
1860                 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1861         }
1862         return tv_dac;
1863 }
1864
1865 static const char *thermal_controller_names[] = {
1866         "NONE",
1867         "lm63",
1868         "adm1032",
1869         "adm1030",
1870         "max6649",
1871         "lm64",
1872         "f75375",
1873         "asc7xxx",
1874 };
1875
1876 static const char *pp_lib_thermal_controller_names[] = {
1877         "NONE",
1878         "lm63",
1879         "adm1032",
1880         "adm1030",
1881         "max6649",
1882         "lm64",
1883         "f75375",
1884         "RV6xx",
1885         "RV770",
1886         "adt7473",
1887         "NONE",
1888         "External GPIO",
1889         "Evergreen",
1890         "emc2103",
1891         "Sumo",
1892         "Northern Islands",
1893 };
1894
1895 union power_info {
1896         struct _ATOM_POWERPLAY_INFO info;
1897         struct _ATOM_POWERPLAY_INFO_V2 info_2;
1898         struct _ATOM_POWERPLAY_INFO_V3 info_3;
1899         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1900         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1901         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1902 };
1903
1904 union pplib_clock_info {
1905         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1906         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1907         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1908         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1909 };
1910
1911 union pplib_power_state {
1912         struct _ATOM_PPLIB_STATE v1;
1913         struct _ATOM_PPLIB_STATE_V2 v2;
1914 };
1915
1916 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
1917                                                  int state_index,
1918                                                  u32 misc, u32 misc2)
1919 {
1920         rdev->pm.power_state[state_index].misc = misc;
1921         rdev->pm.power_state[state_index].misc2 = misc2;
1922         /* order matters! */
1923         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1924                 rdev->pm.power_state[state_index].type =
1925                         POWER_STATE_TYPE_POWERSAVE;
1926         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1927                 rdev->pm.power_state[state_index].type =
1928                         POWER_STATE_TYPE_BATTERY;
1929         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1930                 rdev->pm.power_state[state_index].type =
1931                         POWER_STATE_TYPE_BATTERY;
1932         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1933                 rdev->pm.power_state[state_index].type =
1934                         POWER_STATE_TYPE_BALANCED;
1935         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1936                 rdev->pm.power_state[state_index].type =
1937                         POWER_STATE_TYPE_PERFORMANCE;
1938                 rdev->pm.power_state[state_index].flags &=
1939                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1940         }
1941         if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1942                 rdev->pm.power_state[state_index].type =
1943                         POWER_STATE_TYPE_BALANCED;
1944         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1945                 rdev->pm.power_state[state_index].type =
1946                         POWER_STATE_TYPE_DEFAULT;
1947                 rdev->pm.default_power_state_index = state_index;
1948                 rdev->pm.power_state[state_index].default_clock_mode =
1949                         &rdev->pm.power_state[state_index].clock_info[0];
1950         } else if (state_index == 0) {
1951                 rdev->pm.power_state[state_index].clock_info[0].flags |=
1952                         RADEON_PM_MODE_NO_DISPLAY;
1953         }
1954 }
1955
1956 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
1957 {
1958         struct radeon_mode_info *mode_info = &rdev->mode_info;
1959         u32 misc, misc2 = 0;
1960         int num_modes = 0, i;
1961         int state_index = 0;
1962         struct radeon_i2c_bus_rec i2c_bus;
1963         union power_info *power_info;
1964         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1965         u16 data_offset;
1966         u8 frev, crev;
1967
1968         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1969                                    &frev, &crev, &data_offset))
1970                 return state_index;
1971         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1972
1973         /* add the i2c bus for thermal/fan chip */
1974         if (power_info->info.ucOverdriveThermalController > 0) {
1975                 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1976                          thermal_controller_names[power_info->info.ucOverdriveThermalController],
1977                          power_info->info.ucOverdriveControllerAddress >> 1);
1978                 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1979                 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1980                 if (rdev->pm.i2c_bus) {
1981                         struct i2c_board_info info = { };
1982                         const char *name = thermal_controller_names[power_info->info.
1983                                                                     ucOverdriveThermalController];
1984                         info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1985                         strlcpy(info.type, name, sizeof(info.type));
1986                         i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1987                 }
1988         }
1989         num_modes = power_info->info.ucNumOfPowerModeEntries;
1990         if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1991                 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1992         if (num_modes == 0)
1993                 return state_index;
1994         rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
1995         if (!rdev->pm.power_state)
1996                 return state_index;
1997         /* last mode is usually default, array is low to high */
1998         for (i = 0; i < num_modes; i++) {
1999                 rdev->pm.power_state[state_index].clock_info =
2000                         kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2001                 if (!rdev->pm.power_state[state_index].clock_info)
2002                         return state_index;
2003                 rdev->pm.power_state[state_index].num_clock_modes = 1;
2004                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2005                 switch (frev) {
2006                 case 1:
2007                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2008                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2009                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2010                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2011                         /* skip invalid modes */
2012                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2013                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2014                                 continue;
2015                         rdev->pm.power_state[state_index].pcie_lanes =
2016                                 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2017                         misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2018                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2019                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2020                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2021                                         VOLTAGE_GPIO;
2022                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2023                                         radeon_lookup_gpio(rdev,
2024                                                            power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2025                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2026                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2027                                                 true;
2028                                 else
2029                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2030                                                 false;
2031                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2032                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2033                                         VOLTAGE_VDDC;
2034                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2035                                         power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2036                         }
2037                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2038                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2039                         state_index++;
2040                         break;
2041                 case 2:
2042                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2043                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2044                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2045                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2046                         /* skip invalid modes */
2047                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2048                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2049                                 continue;
2050                         rdev->pm.power_state[state_index].pcie_lanes =
2051                                 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2052                         misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2053                         misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2054                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2055                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2056                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2057                                         VOLTAGE_GPIO;
2058                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2059                                         radeon_lookup_gpio(rdev,
2060                                                            power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2061                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2062                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2063                                                 true;
2064                                 else
2065                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2066                                                 false;
2067                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2068                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2069                                         VOLTAGE_VDDC;
2070                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2071                                         power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2072                         }
2073                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2074                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2075                         state_index++;
2076                         break;
2077                 case 3:
2078                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2079                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2080                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2081                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2082                         /* skip invalid modes */
2083                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2084                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2085                                 continue;
2086                         rdev->pm.power_state[state_index].pcie_lanes =
2087                                 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2088                         misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2089                         misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2090                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2091                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2092                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2093                                         VOLTAGE_GPIO;
2094                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2095                                         radeon_lookup_gpio(rdev,
2096                                                            power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2097                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2098                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2099                                                 true;
2100                                 else
2101                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2102                                                 false;
2103                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2104                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2105                                         VOLTAGE_VDDC;
2106                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2107                                         power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2108                                 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2109                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2110                                                 true;
2111                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2112                                                 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2113                                 }
2114                         }
2115                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2116                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2117                         state_index++;
2118                         break;
2119                 }
2120         }
2121         /* last mode is usually default */
2122         if (rdev->pm.default_power_state_index == -1) {
2123                 rdev->pm.power_state[state_index - 1].type =
2124                         POWER_STATE_TYPE_DEFAULT;
2125                 rdev->pm.default_power_state_index = state_index - 1;
2126                 rdev->pm.power_state[state_index - 1].default_clock_mode =
2127                         &rdev->pm.power_state[state_index - 1].clock_info[0];
2128                 rdev->pm.power_state[state_index].flags &=
2129                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2130                 rdev->pm.power_state[state_index].misc = 0;
2131                 rdev->pm.power_state[state_index].misc2 = 0;
2132         }
2133         return state_index;
2134 }
2135
2136 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2137                                                          ATOM_PPLIB_THERMALCONTROLLER *controller)
2138 {
2139         struct radeon_i2c_bus_rec i2c_bus;
2140
2141         /* add the i2c bus for thermal/fan chip */
2142         if (controller->ucType > 0) {
2143                 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2144                         DRM_INFO("Internal thermal controller %s fan control\n",
2145                                  (controller->ucFanParameters &
2146                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2147                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2148                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2149                         DRM_INFO("Internal thermal controller %s fan control\n",
2150                                  (controller->ucFanParameters &
2151                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2152                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2153                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2154                         DRM_INFO("Internal thermal controller %s fan control\n",
2155                                  (controller->ucFanParameters &
2156                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2157                         rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2158                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2159                         DRM_INFO("Internal thermal controller %s fan control\n",
2160                                  (controller->ucFanParameters &
2161                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2162                         rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2163                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2164                         DRM_INFO("Internal thermal controller %s fan control\n",
2165                                  (controller->ucFanParameters &
2166                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2167                         rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2168                 } else if ((controller->ucType ==
2169                             ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2170                            (controller->ucType ==
2171                             ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
2172                            (controller->ucType ==
2173                             ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
2174                         DRM_INFO("Special thermal controller config\n");
2175                 } else {
2176                         DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2177                                  pp_lib_thermal_controller_names[controller->ucType],
2178                                  controller->ucI2cAddress >> 1,
2179                                  (controller->ucFanParameters &
2180                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2181                         i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2182                         rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2183                         if (rdev->pm.i2c_bus) {
2184                                 struct i2c_board_info info = { };
2185                                 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2186                                 info.addr = controller->ucI2cAddress >> 1;
2187                                 strlcpy(info.type, name, sizeof(info.type));
2188                                 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2189                         }
2190                 }
2191         }
2192 }
2193
2194 static void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2195                                                  u16 *vddc, u16 *vddci)
2196 {
2197         struct radeon_mode_info *mode_info = &rdev->mode_info;
2198         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2199         u8 frev, crev;
2200         u16 data_offset;
2201         union firmware_info *firmware_info;
2202
2203         *vddc = 0;
2204         *vddci = 0;
2205
2206         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2207                                    &frev, &crev, &data_offset)) {
2208                 firmware_info =
2209                         (union firmware_info *)(mode_info->atom_context->bios +
2210                                                 data_offset);
2211                 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2212                 if ((frev == 2) && (crev >= 2))
2213                         *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2214         }
2215 }
2216
2217 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2218                                                        int state_index, int mode_index,
2219                                                        struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2220 {
2221         int j;
2222         u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2223         u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2224         u16 vddc, vddci;
2225
2226         radeon_atombios_get_default_voltages(rdev, &vddc, &vddci);
2227
2228         rdev->pm.power_state[state_index].misc = misc;
2229         rdev->pm.power_state[state_index].misc2 = misc2;
2230         rdev->pm.power_state[state_index].pcie_lanes =
2231                 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2232                  ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2233         switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2234         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2235                 rdev->pm.power_state[state_index].type =
2236                         POWER_STATE_TYPE_BATTERY;
2237                 break;
2238         case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2239                 rdev->pm.power_state[state_index].type =
2240                         POWER_STATE_TYPE_BALANCED;
2241                 break;
2242         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2243                 rdev->pm.power_state[state_index].type =
2244                         POWER_STATE_TYPE_PERFORMANCE;
2245                 break;
2246         case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2247                 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2248                         rdev->pm.power_state[state_index].type =
2249                                 POWER_STATE_TYPE_PERFORMANCE;
2250                 break;
2251         }
2252         rdev->pm.power_state[state_index].flags = 0;
2253         if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2254                 rdev->pm.power_state[state_index].flags |=
2255                         RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2256         if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2257                 rdev->pm.power_state[state_index].type =
2258                         POWER_STATE_TYPE_DEFAULT;
2259                 rdev->pm.default_power_state_index = state_index;
2260                 rdev->pm.power_state[state_index].default_clock_mode =
2261                         &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2262                 if (ASIC_IS_DCE5(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2263                         /* NI chips post without MC ucode, so default clocks are strobe mode only */
2264                         rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2265                         rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2266                         rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2267                         rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2268                 } else {
2269                         /* patch the table values with the default slck/mclk from firmware info */
2270                         for (j = 0; j < mode_index; j++) {
2271                                 rdev->pm.power_state[state_index].clock_info[j].mclk =
2272                                         rdev->clock.default_mclk;
2273                                 rdev->pm.power_state[state_index].clock_info[j].sclk =
2274                                         rdev->clock.default_sclk;
2275                                 if (vddc)
2276                                         rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2277                                                 vddc;
2278                         }
2279                 }
2280         }
2281 }
2282
2283 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2284                                                    int state_index, int mode_index,
2285                                                    union pplib_clock_info *clock_info)
2286 {
2287         u32 sclk, mclk;
2288
2289         if (rdev->flags & RADEON_IS_IGP) {
2290                 if (rdev->family >= CHIP_PALM) {
2291                         sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2292                         sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2293                         rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2294                 } else {
2295                         sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2296                         sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2297                         rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2298                 }
2299         } else if (ASIC_IS_DCE4(rdev)) {
2300                 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2301                 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2302                 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2303                 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2304                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2305                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2306                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2307                         VOLTAGE_SW;
2308                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2309                         le16_to_cpu(clock_info->evergreen.usVDDC);
2310                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2311                         le16_to_cpu(clock_info->evergreen.usVDDCI);
2312         } else {
2313                 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2314                 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2315                 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2316                 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2317                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2318                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2319                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2320                         VOLTAGE_SW;
2321                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2322                         le16_to_cpu(clock_info->r600.usVDDC);
2323         }
2324
2325         /* patch up vddc if necessary */
2326         if (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage == 0xff01) {
2327                 u16 vddc;
2328
2329                 if (radeon_atom_get_max_vddc(rdev, &vddc) == 0)
2330                         rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2331         }
2332
2333         if (rdev->flags & RADEON_IS_IGP) {
2334                 /* skip invalid modes */
2335                 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2336                         return false;
2337         } else {
2338                 /* skip invalid modes */
2339                 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2340                     (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2341                         return false;
2342         }
2343         return true;
2344 }
2345
2346 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2347 {
2348         struct radeon_mode_info *mode_info = &rdev->mode_info;
2349         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2350         union pplib_power_state *power_state;
2351         int i, j;
2352         int state_index = 0, mode_index = 0;
2353         union pplib_clock_info *clock_info;
2354         bool valid;
2355         union power_info *power_info;
2356         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2357         u16 data_offset;
2358         u8 frev, crev;
2359
2360         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2361                                    &frev, &crev, &data_offset))
2362                 return state_index;
2363         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2364
2365         radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2366         if (power_info->pplib.ucNumStates == 0)
2367                 return state_index;
2368         rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2369                                        power_info->pplib.ucNumStates, GFP_KERNEL);
2370         if (!rdev->pm.power_state)
2371                 return state_index;
2372         /* first mode is usually default, followed by low to high */
2373         for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2374                 mode_index = 0;
2375                 power_state = (union pplib_power_state *)
2376                         (mode_info->atom_context->bios + data_offset +
2377                          le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2378                          i * power_info->pplib.ucStateEntrySize);
2379                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2380                         (mode_info->atom_context->bios + data_offset +
2381                          le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2382                          (power_state->v1.ucNonClockStateIndex *
2383                           power_info->pplib.ucNonClockSize));
2384                 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2385                                                              ((power_info->pplib.ucStateEntrySize - 1) ?
2386                                                               (power_info->pplib.ucStateEntrySize - 1) : 1),
2387                                                              GFP_KERNEL);
2388                 if (!rdev->pm.power_state[i].clock_info)
2389                         return state_index;
2390                 if (power_info->pplib.ucStateEntrySize - 1) {
2391                         for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2392                                 clock_info = (union pplib_clock_info *)
2393                                         (mode_info->atom_context->bios + data_offset +
2394                                          le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2395                                          (power_state->v1.ucClockStateIndices[j] *
2396                                           power_info->pplib.ucClockInfoSize));
2397                                 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2398                                                                                state_index, mode_index,
2399                                                                                clock_info);
2400                                 if (valid)
2401                                         mode_index++;
2402                         }
2403                 } else {
2404                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2405                                 rdev->clock.default_mclk;
2406                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2407                                 rdev->clock.default_sclk;
2408                         mode_index++;
2409                 }
2410                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2411                 if (mode_index) {
2412                         radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2413                                                                    non_clock_info);
2414                         state_index++;
2415                 }
2416         }
2417         /* if multiple clock modes, mark the lowest as no display */
2418         for (i = 0; i < state_index; i++) {
2419                 if (rdev->pm.power_state[i].num_clock_modes > 1)
2420                         rdev->pm.power_state[i].clock_info[0].flags |=
2421                                 RADEON_PM_MODE_NO_DISPLAY;
2422         }
2423         /* first mode is usually default */
2424         if (rdev->pm.default_power_state_index == -1) {
2425                 rdev->pm.power_state[0].type =
2426                         POWER_STATE_TYPE_DEFAULT;
2427                 rdev->pm.default_power_state_index = 0;
2428                 rdev->pm.power_state[0].default_clock_mode =
2429                         &rdev->pm.power_state[0].clock_info[0];
2430         }
2431         return state_index;
2432 }
2433
2434 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2435 {
2436         struct radeon_mode_info *mode_info = &rdev->mode_info;
2437         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2438         union pplib_power_state *power_state;
2439         int i, j, non_clock_array_index, clock_array_index;
2440         int state_index = 0, mode_index = 0;
2441         union pplib_clock_info *clock_info;
2442         struct StateArray *state_array;
2443         struct ClockInfoArray *clock_info_array;
2444         struct NonClockInfoArray *non_clock_info_array;
2445         bool valid;
2446         union power_info *power_info;
2447         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2448         u16 data_offset;
2449         u8 frev, crev;
2450
2451         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2452                                    &frev, &crev, &data_offset))
2453                 return state_index;
2454         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2455
2456         radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2457         state_array = (struct StateArray *)
2458                 (mode_info->atom_context->bios + data_offset +
2459                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
2460         clock_info_array = (struct ClockInfoArray *)
2461                 (mode_info->atom_context->bios + data_offset +
2462                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2463         non_clock_info_array = (struct NonClockInfoArray *)
2464                 (mode_info->atom_context->bios + data_offset +
2465                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2466         if (state_array->ucNumEntries == 0)
2467                 return state_index;
2468         rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2469                                        state_array->ucNumEntries, GFP_KERNEL);
2470         if (!rdev->pm.power_state)
2471                 return state_index;
2472         for (i = 0; i < state_array->ucNumEntries; i++) {
2473                 mode_index = 0;
2474                 power_state = (union pplib_power_state *)&state_array->states[i];
2475                 /* XXX this might be an inagua bug... */
2476                 non_clock_array_index = i; /* power_state->v2.nonClockInfoIndex */
2477                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2478                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
2479                 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2480                                                              (power_state->v2.ucNumDPMLevels ?
2481                                                               power_state->v2.ucNumDPMLevels : 1),
2482                                                              GFP_KERNEL);
2483                 if (!rdev->pm.power_state[i].clock_info)
2484                         return state_index;
2485                 if (power_state->v2.ucNumDPMLevels) {
2486                         for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2487                                 clock_array_index = power_state->v2.clockInfoIndex[j];
2488                                 /* XXX this might be an inagua bug... */
2489                                 if (clock_array_index >= clock_info_array->ucNumEntries)
2490                                         continue;
2491                                 clock_info = (union pplib_clock_info *)
2492                                         &clock_info_array->clockInfo[clock_array_index];
2493                                 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2494                                                                                state_index, mode_index,
2495                                                                                clock_info);
2496                                 if (valid)
2497                                         mode_index++;
2498                         }
2499                 } else {
2500                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2501                                 rdev->clock.default_mclk;
2502                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2503                                 rdev->clock.default_sclk;
2504                         mode_index++;
2505                 }
2506                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2507                 if (mode_index) {
2508                         radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2509                                                                    non_clock_info);
2510                         state_index++;
2511                 }
2512         }
2513         /* if multiple clock modes, mark the lowest as no display */
2514         for (i = 0; i < state_index; i++) {
2515                 if (rdev->pm.power_state[i].num_clock_modes > 1)
2516                         rdev->pm.power_state[i].clock_info[0].flags |=
2517                                 RADEON_PM_MODE_NO_DISPLAY;
2518         }
2519         /* first mode is usually default */
2520         if (rdev->pm.default_power_state_index == -1) {
2521                 rdev->pm.power_state[0].type =
2522                         POWER_STATE_TYPE_DEFAULT;
2523                 rdev->pm.default_power_state_index = 0;
2524                 rdev->pm.power_state[0].default_clock_mode =
2525                         &rdev->pm.power_state[0].clock_info[0];
2526         }
2527         return state_index;
2528 }
2529
2530 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2531 {
2532         struct radeon_mode_info *mode_info = &rdev->mode_info;
2533         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2534         u16 data_offset;
2535         u8 frev, crev;
2536         int state_index = 0;
2537
2538         rdev->pm.default_power_state_index = -1;
2539
2540         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2541                                    &frev, &crev, &data_offset)) {
2542                 switch (frev) {
2543                 case 1:
2544                 case 2:
2545                 case 3:
2546                         state_index = radeon_atombios_parse_power_table_1_3(rdev);
2547                         break;
2548                 case 4:
2549                 case 5:
2550                         state_index = radeon_atombios_parse_power_table_4_5(rdev);
2551                         break;
2552                 case 6:
2553                         state_index = radeon_atombios_parse_power_table_6(rdev);
2554                         break;
2555                 default:
2556                         break;
2557                 }
2558         }
2559
2560         if (state_index == 0) {
2561                 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2562                 if (rdev->pm.power_state) {
2563                         rdev->pm.power_state[0].clock_info =
2564                                 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2565                         if (rdev->pm.power_state[0].clock_info) {
2566                                 /* add the default mode */
2567                                 rdev->pm.power_state[state_index].type =
2568                                         POWER_STATE_TYPE_DEFAULT;
2569                                 rdev->pm.power_state[state_index].num_clock_modes = 1;
2570                                 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2571                                 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2572                                 rdev->pm.power_state[state_index].default_clock_mode =
2573                                         &rdev->pm.power_state[state_index].clock_info[0];
2574                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2575                                 rdev->pm.power_state[state_index].pcie_lanes = 16;
2576                                 rdev->pm.default_power_state_index = state_index;
2577                                 rdev->pm.power_state[state_index].flags = 0;
2578                                 state_index++;
2579                         }
2580                 }
2581         }
2582
2583         rdev->pm.num_power_states = state_index;
2584
2585         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2586         rdev->pm.current_clock_mode_index = 0;
2587         if (rdev->pm.default_power_state_index >= 0)
2588                 rdev->pm.current_vddc =
2589                         rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2590         else
2591                 rdev->pm.current_vddc = 0;
2592 }
2593
2594 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2595 {
2596         DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2597         int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2598
2599         args.ucEnable = enable;
2600
2601         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2602 }
2603
2604 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2605 {
2606         GET_ENGINE_CLOCK_PS_ALLOCATION args;
2607         int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2608
2609         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2610         return le32_to_cpu(args.ulReturnEngineClock);
2611 }
2612
2613 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2614 {
2615         GET_MEMORY_CLOCK_PS_ALLOCATION args;
2616         int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2617
2618         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2619         return le32_to_cpu(args.ulReturnMemoryClock);
2620 }
2621
2622 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2623                                   uint32_t eng_clock)
2624 {
2625         SET_ENGINE_CLOCK_PS_ALLOCATION args;
2626         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2627
2628         args.ulTargetEngineClock = cpu_to_le32(eng_clock);      /* 10 khz */
2629
2630         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2631 }
2632
2633 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2634                                   uint32_t mem_clock)
2635 {
2636         SET_MEMORY_CLOCK_PS_ALLOCATION args;
2637         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2638
2639         if (rdev->flags & RADEON_IS_IGP)
2640                 return;
2641
2642         args.ulTargetMemoryClock = cpu_to_le32(mem_clock);      /* 10 khz */
2643
2644         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2645 }
2646
2647 union set_voltage {
2648         struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2649         struct _SET_VOLTAGE_PARAMETERS v1;
2650         struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2651 };
2652
2653 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
2654 {
2655         union set_voltage args;
2656         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2657         u8 frev, crev, volt_index = voltage_level;
2658
2659         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2660                 return;
2661
2662         /* 0xff01 is a flag rather then an actual voltage */
2663         if (voltage_level == 0xff01)
2664                 return;
2665
2666         switch (crev) {
2667         case 1:
2668                 args.v1.ucVoltageType = voltage_type;
2669                 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2670                 args.v1.ucVoltageIndex = volt_index;
2671                 break;
2672         case 2:
2673                 args.v2.ucVoltageType = voltage_type;
2674                 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2675                 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
2676                 break;
2677         default:
2678                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2679                 return;
2680         }
2681
2682         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2683 }
2684
2685 int radeon_atom_get_max_vddc(struct radeon_device *rdev,
2686                              u16 *voltage)
2687 {
2688         union set_voltage args;
2689         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2690         u8 frev, crev;
2691
2692         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2693                 return -EINVAL;
2694
2695         switch (crev) {
2696         case 1:
2697                 return -EINVAL;
2698         case 2:
2699                 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
2700                 args.v2.ucVoltageMode = 0;
2701                 args.v2.usVoltageLevel = 0;
2702
2703                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2704
2705                 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
2706                 break;
2707         default:
2708                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2709                 return -EINVAL;
2710         }
2711
2712         return 0;
2713 }
2714
2715 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2716 {
2717         struct radeon_device *rdev = dev->dev_private;
2718         uint32_t bios_2_scratch, bios_6_scratch;
2719
2720         if (rdev->family >= CHIP_R600) {
2721                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2722                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2723         } else {
2724                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2725                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2726         }
2727
2728         /* let the bios control the backlight */
2729         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2730
2731         /* tell the bios not to handle mode switching */
2732         bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
2733
2734         if (rdev->family >= CHIP_R600) {
2735                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2736                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2737         } else {
2738                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2739                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2740         }
2741
2742 }
2743
2744 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2745 {
2746         uint32_t scratch_reg;
2747         int i;
2748
2749         if (rdev->family >= CHIP_R600)
2750                 scratch_reg = R600_BIOS_0_SCRATCH;
2751         else
2752                 scratch_reg = RADEON_BIOS_0_SCRATCH;
2753
2754         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2755                 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2756 }
2757
2758 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2759 {
2760         uint32_t scratch_reg;
2761         int i;
2762
2763         if (rdev->family >= CHIP_R600)
2764                 scratch_reg = R600_BIOS_0_SCRATCH;
2765         else
2766                 scratch_reg = RADEON_BIOS_0_SCRATCH;
2767
2768         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2769                 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2770 }
2771
2772 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2773 {
2774         struct drm_device *dev = encoder->dev;
2775         struct radeon_device *rdev = dev->dev_private;
2776         uint32_t bios_6_scratch;
2777
2778         if (rdev->family >= CHIP_R600)
2779                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2780         else
2781                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2782
2783         if (lock) {
2784                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2785                 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
2786         } else {
2787                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2788                 bios_6_scratch |= ATOM_S6_ACC_MODE;
2789         }
2790
2791         if (rdev->family >= CHIP_R600)
2792                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2793         else
2794                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2795 }
2796
2797 /* at some point we may want to break this out into individual functions */
2798 void
2799 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2800                                        struct drm_encoder *encoder,
2801                                        bool connected)
2802 {
2803         struct drm_device *dev = connector->dev;
2804         struct radeon_device *rdev = dev->dev_private;
2805         struct radeon_connector *radeon_connector =
2806             to_radeon_connector(connector);
2807         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2808         uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2809
2810         if (rdev->family >= CHIP_R600) {
2811                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2812                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2813                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2814         } else {
2815                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2816                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2817                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2818         }
2819
2820         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2821             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2822                 if (connected) {
2823                         DRM_DEBUG_KMS("TV1 connected\n");
2824                         bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2825                         bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2826                 } else {
2827                         DRM_DEBUG_KMS("TV1 disconnected\n");
2828                         bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2829                         bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2830                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2831                 }
2832         }
2833         if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2834             (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2835                 if (connected) {
2836                         DRM_DEBUG_KMS("CV connected\n");
2837                         bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2838                         bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2839                 } else {
2840                         DRM_DEBUG_KMS("CV disconnected\n");
2841                         bios_0_scratch &= ~ATOM_S0_CV_MASK;
2842                         bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2843                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2844                 }
2845         }
2846         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2847             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2848                 if (connected) {
2849                         DRM_DEBUG_KMS("LCD1 connected\n");
2850                         bios_0_scratch |= ATOM_S0_LCD1;
2851                         bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2852                         bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2853                 } else {
2854                         DRM_DEBUG_KMS("LCD1 disconnected\n");
2855                         bios_0_scratch &= ~ATOM_S0_LCD1;
2856                         bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2857                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2858                 }
2859         }
2860         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2861             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2862                 if (connected) {
2863                         DRM_DEBUG_KMS("CRT1 connected\n");
2864                         bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2865                         bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2866                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2867                 } else {
2868                         DRM_DEBUG_KMS("CRT1 disconnected\n");
2869                         bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2870                         bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2871                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2872                 }
2873         }
2874         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2875             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2876                 if (connected) {
2877                         DRM_DEBUG_KMS("CRT2 connected\n");
2878                         bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2879                         bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2880                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2881                 } else {
2882                         DRM_DEBUG_KMS("CRT2 disconnected\n");
2883                         bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2884                         bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2885                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2886                 }
2887         }
2888         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2889             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2890                 if (connected) {
2891                         DRM_DEBUG_KMS("DFP1 connected\n");
2892                         bios_0_scratch |= ATOM_S0_DFP1;
2893                         bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2894                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2895                 } else {
2896                         DRM_DEBUG_KMS("DFP1 disconnected\n");
2897                         bios_0_scratch &= ~ATOM_S0_DFP1;
2898                         bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2899                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2900                 }
2901         }
2902         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2903             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2904                 if (connected) {
2905                         DRM_DEBUG_KMS("DFP2 connected\n");
2906                         bios_0_scratch |= ATOM_S0_DFP2;
2907                         bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2908                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2909                 } else {
2910                         DRM_DEBUG_KMS("DFP2 disconnected\n");
2911                         bios_0_scratch &= ~ATOM_S0_DFP2;
2912                         bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2913                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2914                 }
2915         }
2916         if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2917             (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2918                 if (connected) {
2919                         DRM_DEBUG_KMS("DFP3 connected\n");
2920                         bios_0_scratch |= ATOM_S0_DFP3;
2921                         bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2922                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2923                 } else {
2924                         DRM_DEBUG_KMS("DFP3 disconnected\n");
2925                         bios_0_scratch &= ~ATOM_S0_DFP3;
2926                         bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2927                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2928                 }
2929         }
2930         if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2931             (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2932                 if (connected) {
2933                         DRM_DEBUG_KMS("DFP4 connected\n");
2934                         bios_0_scratch |= ATOM_S0_DFP4;
2935                         bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2936                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2937                 } else {
2938                         DRM_DEBUG_KMS("DFP4 disconnected\n");
2939                         bios_0_scratch &= ~ATOM_S0_DFP4;
2940                         bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2941                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2942                 }
2943         }
2944         if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2945             (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2946                 if (connected) {
2947                         DRM_DEBUG_KMS("DFP5 connected\n");
2948                         bios_0_scratch |= ATOM_S0_DFP5;
2949                         bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2950                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2951                 } else {
2952                         DRM_DEBUG_KMS("DFP5 disconnected\n");
2953                         bios_0_scratch &= ~ATOM_S0_DFP5;
2954                         bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2955                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2956                 }
2957         }
2958
2959         if (rdev->family >= CHIP_R600) {
2960                 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2961                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2962                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2963         } else {
2964                 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2965                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2966                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2967         }
2968 }
2969
2970 void
2971 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2972 {
2973         struct drm_device *dev = encoder->dev;
2974         struct radeon_device *rdev = dev->dev_private;
2975         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2976         uint32_t bios_3_scratch;
2977
2978         if (rdev->family >= CHIP_R600)
2979                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2980         else
2981                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2982
2983         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2984                 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2985                 bios_3_scratch |= (crtc << 18);
2986         }
2987         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2988                 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2989                 bios_3_scratch |= (crtc << 24);
2990         }
2991         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2992                 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2993                 bios_3_scratch |= (crtc << 16);
2994         }
2995         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2996                 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2997                 bios_3_scratch |= (crtc << 20);
2998         }
2999         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3000                 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
3001                 bios_3_scratch |= (crtc << 17);
3002         }
3003         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3004                 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
3005                 bios_3_scratch |= (crtc << 19);
3006         }
3007         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3008                 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
3009                 bios_3_scratch |= (crtc << 23);
3010         }
3011         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
3012                 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
3013                 bios_3_scratch |= (crtc << 25);
3014         }
3015
3016         if (rdev->family >= CHIP_R600)
3017                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
3018         else
3019                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
3020 }
3021
3022 void
3023 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3024 {
3025         struct drm_device *dev = encoder->dev;
3026         struct radeon_device *rdev = dev->dev_private;
3027         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3028         uint32_t bios_2_scratch;
3029
3030         if (rdev->family >= CHIP_R600)
3031                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
3032         else
3033                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
3034
3035         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3036                 if (on)
3037                         bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
3038                 else
3039                         bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
3040         }
3041         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
3042                 if (on)
3043                         bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
3044                 else
3045                         bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
3046         }
3047         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3048                 if (on)
3049                         bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
3050                 else
3051                         bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
3052         }
3053         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3054                 if (on)
3055                         bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
3056                 else
3057                         bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
3058         }
3059         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3060                 if (on)
3061                         bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
3062                 else
3063                         bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
3064         }
3065         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3066                 if (on)
3067                         bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
3068                 else
3069                         bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
3070         }
3071         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3072                 if (on)
3073                         bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
3074                 else
3075                         bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
3076         }
3077         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
3078                 if (on)
3079                         bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
3080                 else
3081                         bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
3082         }
3083         if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
3084                 if (on)
3085                         bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
3086                 else
3087                         bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
3088         }
3089         if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
3090                 if (on)
3091                         bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
3092                 else
3093                         bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
3094         }
3095
3096         if (rdev->family >= CHIP_R600)
3097                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
3098         else
3099                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
3100 }