2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/slab.h>
29 #include <linux/seq_file.h>
30 #include <linux/firmware.h>
31 #include <linux/platform_device.h>
33 #include "radeon_drm.h"
35 #include "radeon_asic.h"
36 #include "radeon_mode.h"
41 #define PFP_UCODE_SIZE 576
42 #define PM4_UCODE_SIZE 1792
43 #define RLC_UCODE_SIZE 768
44 #define R700_PFP_UCODE_SIZE 848
45 #define R700_PM4_UCODE_SIZE 1360
46 #define R700_RLC_UCODE_SIZE 1024
49 MODULE_FIRMWARE("radeon/R600_pfp.bin");
50 MODULE_FIRMWARE("radeon/R600_me.bin");
51 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
52 MODULE_FIRMWARE("radeon/RV610_me.bin");
53 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
54 MODULE_FIRMWARE("radeon/RV630_me.bin");
55 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
56 MODULE_FIRMWARE("radeon/RV620_me.bin");
57 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
58 MODULE_FIRMWARE("radeon/RV635_me.bin");
59 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
60 MODULE_FIRMWARE("radeon/RV670_me.bin");
61 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
62 MODULE_FIRMWARE("radeon/RS780_me.bin");
63 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
64 MODULE_FIRMWARE("radeon/RV770_me.bin");
65 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
66 MODULE_FIRMWARE("radeon/RV730_me.bin");
67 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
68 MODULE_FIRMWARE("radeon/RV710_me.bin");
69 MODULE_FIRMWARE("radeon/R600_rlc.bin");
70 MODULE_FIRMWARE("radeon/R700_rlc.bin");
72 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
74 /* r600,rv610,rv630,rv620,rv635,rv670 */
75 int r600_mc_wait_for_idle(struct radeon_device *rdev);
76 void r600_gpu_init(struct radeon_device *rdev);
77 void r600_fini(struct radeon_device *rdev);
79 /* hpd for digital panel detect/disconnect */
80 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
82 bool connected = false;
84 if (ASIC_IS_DCE3(rdev)) {
87 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
91 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
95 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
99 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
104 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
108 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
117 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
121 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
125 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
135 void r600_hpd_set_polarity(struct radeon_device *rdev,
136 enum radeon_hpd_id hpd)
139 bool connected = r600_hpd_sense(rdev, hpd);
141 if (ASIC_IS_DCE3(rdev)) {
144 tmp = RREG32(DC_HPD1_INT_CONTROL);
146 tmp &= ~DC_HPDx_INT_POLARITY;
148 tmp |= DC_HPDx_INT_POLARITY;
149 WREG32(DC_HPD1_INT_CONTROL, tmp);
152 tmp = RREG32(DC_HPD2_INT_CONTROL);
154 tmp &= ~DC_HPDx_INT_POLARITY;
156 tmp |= DC_HPDx_INT_POLARITY;
157 WREG32(DC_HPD2_INT_CONTROL, tmp);
160 tmp = RREG32(DC_HPD3_INT_CONTROL);
162 tmp &= ~DC_HPDx_INT_POLARITY;
164 tmp |= DC_HPDx_INT_POLARITY;
165 WREG32(DC_HPD3_INT_CONTROL, tmp);
168 tmp = RREG32(DC_HPD4_INT_CONTROL);
170 tmp &= ~DC_HPDx_INT_POLARITY;
172 tmp |= DC_HPDx_INT_POLARITY;
173 WREG32(DC_HPD4_INT_CONTROL, tmp);
176 tmp = RREG32(DC_HPD5_INT_CONTROL);
178 tmp &= ~DC_HPDx_INT_POLARITY;
180 tmp |= DC_HPDx_INT_POLARITY;
181 WREG32(DC_HPD5_INT_CONTROL, tmp);
185 tmp = RREG32(DC_HPD6_INT_CONTROL);
187 tmp &= ~DC_HPDx_INT_POLARITY;
189 tmp |= DC_HPDx_INT_POLARITY;
190 WREG32(DC_HPD6_INT_CONTROL, tmp);
198 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
200 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
202 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
203 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
206 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
208 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
210 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
211 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
214 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
216 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
218 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
219 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
227 void r600_hpd_init(struct radeon_device *rdev)
229 struct drm_device *dev = rdev->ddev;
230 struct drm_connector *connector;
232 if (ASIC_IS_DCE3(rdev)) {
233 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
234 if (ASIC_IS_DCE32(rdev))
237 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
238 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
239 switch (radeon_connector->hpd.hpd) {
241 WREG32(DC_HPD1_CONTROL, tmp);
242 rdev->irq.hpd[0] = true;
245 WREG32(DC_HPD2_CONTROL, tmp);
246 rdev->irq.hpd[1] = true;
249 WREG32(DC_HPD3_CONTROL, tmp);
250 rdev->irq.hpd[2] = true;
253 WREG32(DC_HPD4_CONTROL, tmp);
254 rdev->irq.hpd[3] = true;
258 WREG32(DC_HPD5_CONTROL, tmp);
259 rdev->irq.hpd[4] = true;
262 WREG32(DC_HPD6_CONTROL, tmp);
263 rdev->irq.hpd[5] = true;
270 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
271 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
272 switch (radeon_connector->hpd.hpd) {
274 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
275 rdev->irq.hpd[0] = true;
278 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
279 rdev->irq.hpd[1] = true;
282 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
283 rdev->irq.hpd[2] = true;
290 if (rdev->irq.installed)
294 void r600_hpd_fini(struct radeon_device *rdev)
296 struct drm_device *dev = rdev->ddev;
297 struct drm_connector *connector;
299 if (ASIC_IS_DCE3(rdev)) {
300 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
301 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
302 switch (radeon_connector->hpd.hpd) {
304 WREG32(DC_HPD1_CONTROL, 0);
305 rdev->irq.hpd[0] = false;
308 WREG32(DC_HPD2_CONTROL, 0);
309 rdev->irq.hpd[1] = false;
312 WREG32(DC_HPD3_CONTROL, 0);
313 rdev->irq.hpd[2] = false;
316 WREG32(DC_HPD4_CONTROL, 0);
317 rdev->irq.hpd[3] = false;
321 WREG32(DC_HPD5_CONTROL, 0);
322 rdev->irq.hpd[4] = false;
325 WREG32(DC_HPD6_CONTROL, 0);
326 rdev->irq.hpd[5] = false;
333 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
334 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
335 switch (radeon_connector->hpd.hpd) {
337 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
338 rdev->irq.hpd[0] = false;
341 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
342 rdev->irq.hpd[1] = false;
345 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
346 rdev->irq.hpd[2] = false;
358 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
363 /* flush hdp cache so updates hit vram */
364 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
366 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
367 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
368 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
369 for (i = 0; i < rdev->usec_timeout; i++) {
371 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
372 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
374 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
384 int r600_pcie_gart_init(struct radeon_device *rdev)
388 if (rdev->gart.table.vram.robj) {
389 WARN(1, "R600 PCIE GART already initialized.\n");
392 /* Initialize common gart structure */
393 r = radeon_gart_init(rdev);
396 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
397 return radeon_gart_table_vram_alloc(rdev);
400 int r600_pcie_gart_enable(struct radeon_device *rdev)
405 if (rdev->gart.table.vram.robj == NULL) {
406 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
409 r = radeon_gart_table_vram_pin(rdev);
412 radeon_gart_restore(rdev);
415 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
416 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
417 EFFECTIVE_L2_QUEUE_SIZE(7));
418 WREG32(VM_L2_CNTL2, 0);
419 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
420 /* Setup TLB control */
421 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
422 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
423 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
424 ENABLE_WAIT_L2_QUERY;
425 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
426 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
427 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
428 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
429 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
430 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
431 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
432 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
433 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
434 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
435 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
436 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
437 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
438 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
439 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
440 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
441 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
442 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
443 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
444 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
445 (u32)(rdev->dummy_page.addr >> 12));
446 for (i = 1; i < 7; i++)
447 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
449 r600_pcie_gart_tlb_flush(rdev);
450 rdev->gart.ready = true;
454 void r600_pcie_gart_disable(struct radeon_device *rdev)
459 /* Disable all tables */
460 for (i = 0; i < 7; i++)
461 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
463 /* Disable L2 cache */
464 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
465 EFFECTIVE_L2_QUEUE_SIZE(7));
466 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
467 /* Setup L1 TLB control */
468 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
469 ENABLE_WAIT_L2_QUERY;
470 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
471 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
472 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
473 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
474 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
475 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
476 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
477 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
478 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
479 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
480 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
481 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
482 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
483 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
484 if (rdev->gart.table.vram.robj) {
485 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
486 if (likely(r == 0)) {
487 radeon_bo_kunmap(rdev->gart.table.vram.robj);
488 radeon_bo_unpin(rdev->gart.table.vram.robj);
489 radeon_bo_unreserve(rdev->gart.table.vram.robj);
494 void r600_pcie_gart_fini(struct radeon_device *rdev)
496 radeon_gart_fini(rdev);
497 r600_pcie_gart_disable(rdev);
498 radeon_gart_table_vram_free(rdev);
501 void r600_agp_enable(struct radeon_device *rdev)
507 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
508 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
509 EFFECTIVE_L2_QUEUE_SIZE(7));
510 WREG32(VM_L2_CNTL2, 0);
511 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
512 /* Setup TLB control */
513 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
514 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
515 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
516 ENABLE_WAIT_L2_QUERY;
517 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
518 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
519 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
520 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
521 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
522 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
523 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
524 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
525 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
526 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
527 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
528 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
529 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
530 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
531 for (i = 0; i < 7; i++)
532 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
535 int r600_mc_wait_for_idle(struct radeon_device *rdev)
540 for (i = 0; i < rdev->usec_timeout; i++) {
542 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
550 static void r600_mc_program(struct radeon_device *rdev)
552 struct rv515_mc_save save;
557 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
558 WREG32((0x2c14 + j), 0x00000000);
559 WREG32((0x2c18 + j), 0x00000000);
560 WREG32((0x2c1c + j), 0x00000000);
561 WREG32((0x2c20 + j), 0x00000000);
562 WREG32((0x2c24 + j), 0x00000000);
564 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
566 rv515_mc_stop(rdev, &save);
567 if (r600_mc_wait_for_idle(rdev)) {
568 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
570 /* Lockout access through VGA aperture (doesn't exist before R600) */
571 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
572 /* Update configuration */
573 if (rdev->flags & RADEON_IS_AGP) {
574 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
575 /* VRAM before AGP */
576 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
577 rdev->mc.vram_start >> 12);
578 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
579 rdev->mc.gtt_end >> 12);
582 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
583 rdev->mc.gtt_start >> 12);
584 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
585 rdev->mc.vram_end >> 12);
588 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
589 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
591 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
592 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
593 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
594 WREG32(MC_VM_FB_LOCATION, tmp);
595 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
596 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
597 WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF);
598 if (rdev->flags & RADEON_IS_AGP) {
599 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
600 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
601 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
603 WREG32(MC_VM_AGP_BASE, 0);
604 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
605 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
607 if (r600_mc_wait_for_idle(rdev)) {
608 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
610 rv515_mc_resume(rdev, &save);
611 /* we need to own VRAM, so turn off the VGA renderer here
612 * to stop it overwriting our objects */
613 rv515_vga_render_disable(rdev);
617 * r600_vram_gtt_location - try to find VRAM & GTT location
618 * @rdev: radeon device structure holding all necessary informations
619 * @mc: memory controller structure holding memory informations
621 * Function will place try to place VRAM at same place as in CPU (PCI)
622 * address space as some GPU seems to have issue when we reprogram at
623 * different address space.
625 * If there is not enough space to fit the unvisible VRAM after the
626 * aperture then we limit the VRAM size to the aperture.
628 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
629 * them to be in one from GPU point of view so that we can program GPU to
630 * catch access outside them (weird GPU policy see ??).
632 * This function will never fails, worst case are limiting VRAM or GTT.
634 * Note: GTT start, end, size should be initialized before calling this
635 * function on AGP platform.
637 void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
639 u64 size_bf, size_af;
641 if (mc->mc_vram_size > 0xE0000000) {
642 /* leave room for at least 512M GTT */
643 dev_warn(rdev->dev, "limiting VRAM\n");
644 mc->real_vram_size = 0xE0000000;
645 mc->mc_vram_size = 0xE0000000;
647 if (rdev->flags & RADEON_IS_AGP) {
648 size_bf = mc->gtt_start;
649 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
650 if (size_bf > size_af) {
651 if (mc->mc_vram_size > size_bf) {
652 dev_warn(rdev->dev, "limiting VRAM\n");
653 mc->real_vram_size = size_bf;
654 mc->mc_vram_size = size_bf;
656 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
658 if (mc->mc_vram_size > size_af) {
659 dev_warn(rdev->dev, "limiting VRAM\n");
660 mc->real_vram_size = size_af;
661 mc->mc_vram_size = size_af;
663 mc->vram_start = mc->gtt_end;
665 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
666 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
667 mc->mc_vram_size >> 20, mc->vram_start,
668 mc->vram_end, mc->real_vram_size >> 20);
671 if (rdev->flags & RADEON_IS_IGP)
672 base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
673 radeon_vram_location(rdev, &rdev->mc, base);
674 radeon_gtt_location(rdev, mc);
678 int r600_mc_init(struct radeon_device *rdev)
681 int chansize, numchan;
683 /* Get VRAM informations */
684 rdev->mc.vram_is_ddr = true;
685 tmp = RREG32(RAMCFG);
686 if (tmp & CHANSIZE_OVERRIDE) {
688 } else if (tmp & CHANSIZE_MASK) {
694 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
709 rdev->mc.vram_width = numchan * chansize;
710 /* Could aper size report 0 ? */
711 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
712 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
713 /* Setup GPU memory space */
714 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
715 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
716 rdev->mc.visible_vram_size = rdev->mc.aper_size;
717 /* FIXME remove this once we support unmappable VRAM */
718 if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
719 rdev->mc.mc_vram_size = rdev->mc.aper_size;
720 rdev->mc.real_vram_size = rdev->mc.aper_size;
722 r600_vram_gtt_location(rdev, &rdev->mc);
724 if (rdev->flags & RADEON_IS_IGP)
725 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
726 radeon_update_bandwidth_info(rdev);
730 /* We doesn't check that the GPU really needs a reset we simply do the
731 * reset, it's up to the caller to determine if the GPU needs one. We
732 * might add an helper function to check that.
734 int r600_gpu_soft_reset(struct radeon_device *rdev)
736 struct rv515_mc_save save;
737 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
738 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
739 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
740 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
741 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
742 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
743 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
744 S_008010_GUI_ACTIVE(1);
745 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
746 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
747 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
748 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
749 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
750 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
751 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
752 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
755 dev_info(rdev->dev, "GPU softreset \n");
756 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
757 RREG32(R_008010_GRBM_STATUS));
758 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
759 RREG32(R_008014_GRBM_STATUS2));
760 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
761 RREG32(R_000E50_SRBM_STATUS));
762 rv515_mc_stop(rdev, &save);
763 if (r600_mc_wait_for_idle(rdev)) {
764 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
766 /* Disable CP parsing/prefetching */
767 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
768 /* Check if any of the rendering block is busy and reset it */
769 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
770 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
771 tmp = S_008020_SOFT_RESET_CR(1) |
772 S_008020_SOFT_RESET_DB(1) |
773 S_008020_SOFT_RESET_CB(1) |
774 S_008020_SOFT_RESET_PA(1) |
775 S_008020_SOFT_RESET_SC(1) |
776 S_008020_SOFT_RESET_SMX(1) |
777 S_008020_SOFT_RESET_SPI(1) |
778 S_008020_SOFT_RESET_SX(1) |
779 S_008020_SOFT_RESET_SH(1) |
780 S_008020_SOFT_RESET_TC(1) |
781 S_008020_SOFT_RESET_TA(1) |
782 S_008020_SOFT_RESET_VC(1) |
783 S_008020_SOFT_RESET_VGT(1);
784 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
785 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
786 RREG32(R_008020_GRBM_SOFT_RESET);
788 WREG32(R_008020_GRBM_SOFT_RESET, 0);
790 /* Reset CP (we always reset CP) */
791 tmp = S_008020_SOFT_RESET_CP(1);
792 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
793 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
794 RREG32(R_008020_GRBM_SOFT_RESET);
796 WREG32(R_008020_GRBM_SOFT_RESET, 0);
797 /* Wait a little for things to settle down */
799 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
800 RREG32(R_008010_GRBM_STATUS));
801 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
802 RREG32(R_008014_GRBM_STATUS2));
803 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
804 RREG32(R_000E50_SRBM_STATUS));
805 rv515_mc_resume(rdev, &save);
809 bool r600_gpu_is_lockup(struct radeon_device *rdev)
816 srbm_status = RREG32(R_000E50_SRBM_STATUS);
817 grbm_status = RREG32(R_008010_GRBM_STATUS);
818 grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
819 if (!G_008010_GUI_ACTIVE(grbm_status)) {
820 r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp);
823 /* force CP activities */
824 r = radeon_ring_lock(rdev, 2);
827 radeon_ring_write(rdev, 0x80000000);
828 radeon_ring_write(rdev, 0x80000000);
829 radeon_ring_unlock_commit(rdev);
831 rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
832 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp);
835 int r600_asic_reset(struct radeon_device *rdev)
837 return r600_gpu_soft_reset(rdev);
840 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
842 u32 backend_disable_mask)
845 u32 enabled_backends_mask;
846 u32 enabled_backends_count;
848 u32 swizzle_pipe[R6XX_MAX_PIPES];
852 if (num_tile_pipes > R6XX_MAX_PIPES)
853 num_tile_pipes = R6XX_MAX_PIPES;
854 if (num_tile_pipes < 1)
856 if (num_backends > R6XX_MAX_BACKENDS)
857 num_backends = R6XX_MAX_BACKENDS;
858 if (num_backends < 1)
861 enabled_backends_mask = 0;
862 enabled_backends_count = 0;
863 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
864 if (((backend_disable_mask >> i) & 1) == 0) {
865 enabled_backends_mask |= (1 << i);
866 ++enabled_backends_count;
868 if (enabled_backends_count == num_backends)
872 if (enabled_backends_count == 0) {
873 enabled_backends_mask = 1;
874 enabled_backends_count = 1;
877 if (enabled_backends_count != num_backends)
878 num_backends = enabled_backends_count;
880 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
881 switch (num_tile_pipes) {
937 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
938 while (((1 << cur_backend) & enabled_backends_mask) == 0)
939 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
941 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
943 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
949 int r600_count_pipe_bits(uint32_t val)
953 for (i = 0; i < 32; i++) {
960 void r600_gpu_init(struct radeon_device *rdev)
965 u32 cc_rb_backend_disable;
966 u32 cc_gc_shader_pipe_config;
970 u32 sq_gpr_resource_mgmt_1 = 0;
971 u32 sq_gpr_resource_mgmt_2 = 0;
972 u32 sq_thread_resource_mgmt = 0;
973 u32 sq_stack_resource_mgmt_1 = 0;
974 u32 sq_stack_resource_mgmt_2 = 0;
976 /* FIXME: implement */
977 switch (rdev->family) {
979 rdev->config.r600.max_pipes = 4;
980 rdev->config.r600.max_tile_pipes = 8;
981 rdev->config.r600.max_simds = 4;
982 rdev->config.r600.max_backends = 4;
983 rdev->config.r600.max_gprs = 256;
984 rdev->config.r600.max_threads = 192;
985 rdev->config.r600.max_stack_entries = 256;
986 rdev->config.r600.max_hw_contexts = 8;
987 rdev->config.r600.max_gs_threads = 16;
988 rdev->config.r600.sx_max_export_size = 128;
989 rdev->config.r600.sx_max_export_pos_size = 16;
990 rdev->config.r600.sx_max_export_smx_size = 128;
991 rdev->config.r600.sq_num_cf_insts = 2;
995 rdev->config.r600.max_pipes = 2;
996 rdev->config.r600.max_tile_pipes = 2;
997 rdev->config.r600.max_simds = 3;
998 rdev->config.r600.max_backends = 1;
999 rdev->config.r600.max_gprs = 128;
1000 rdev->config.r600.max_threads = 192;
1001 rdev->config.r600.max_stack_entries = 128;
1002 rdev->config.r600.max_hw_contexts = 8;
1003 rdev->config.r600.max_gs_threads = 4;
1004 rdev->config.r600.sx_max_export_size = 128;
1005 rdev->config.r600.sx_max_export_pos_size = 16;
1006 rdev->config.r600.sx_max_export_smx_size = 128;
1007 rdev->config.r600.sq_num_cf_insts = 2;
1013 rdev->config.r600.max_pipes = 1;
1014 rdev->config.r600.max_tile_pipes = 1;
1015 rdev->config.r600.max_simds = 2;
1016 rdev->config.r600.max_backends = 1;
1017 rdev->config.r600.max_gprs = 128;
1018 rdev->config.r600.max_threads = 192;
1019 rdev->config.r600.max_stack_entries = 128;
1020 rdev->config.r600.max_hw_contexts = 4;
1021 rdev->config.r600.max_gs_threads = 4;
1022 rdev->config.r600.sx_max_export_size = 128;
1023 rdev->config.r600.sx_max_export_pos_size = 16;
1024 rdev->config.r600.sx_max_export_smx_size = 128;
1025 rdev->config.r600.sq_num_cf_insts = 1;
1028 rdev->config.r600.max_pipes = 4;
1029 rdev->config.r600.max_tile_pipes = 4;
1030 rdev->config.r600.max_simds = 4;
1031 rdev->config.r600.max_backends = 4;
1032 rdev->config.r600.max_gprs = 192;
1033 rdev->config.r600.max_threads = 192;
1034 rdev->config.r600.max_stack_entries = 256;
1035 rdev->config.r600.max_hw_contexts = 8;
1036 rdev->config.r600.max_gs_threads = 16;
1037 rdev->config.r600.sx_max_export_size = 128;
1038 rdev->config.r600.sx_max_export_pos_size = 16;
1039 rdev->config.r600.sx_max_export_smx_size = 128;
1040 rdev->config.r600.sq_num_cf_insts = 2;
1046 /* Initialize HDP */
1047 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1048 WREG32((0x2c14 + j), 0x00000000);
1049 WREG32((0x2c18 + j), 0x00000000);
1050 WREG32((0x2c1c + j), 0x00000000);
1051 WREG32((0x2c20 + j), 0x00000000);
1052 WREG32((0x2c24 + j), 0x00000000);
1055 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1059 ramcfg = RREG32(RAMCFG);
1060 switch (rdev->config.r600.max_tile_pipes) {
1062 tiling_config |= PIPE_TILING(0);
1065 tiling_config |= PIPE_TILING(1);
1068 tiling_config |= PIPE_TILING(2);
1071 tiling_config |= PIPE_TILING(3);
1076 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1077 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1078 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1079 tiling_config |= GROUP_SIZE(0);
1080 rdev->config.r600.tiling_group_size = 256;
1081 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1083 tiling_config |= ROW_TILING(3);
1084 tiling_config |= SAMPLE_SPLIT(3);
1086 tiling_config |= ROW_TILING(tmp);
1087 tiling_config |= SAMPLE_SPLIT(tmp);
1089 tiling_config |= BANK_SWAPS(1);
1091 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1092 cc_rb_backend_disable |=
1093 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1095 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1096 cc_gc_shader_pipe_config |=
1097 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1098 cc_gc_shader_pipe_config |=
1099 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1101 backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1102 (R6XX_MAX_BACKENDS -
1103 r600_count_pipe_bits((cc_rb_backend_disable &
1104 R6XX_MAX_BACKENDS_MASK) >> 16)),
1105 (cc_rb_backend_disable >> 16));
1107 tiling_config |= BACKEND_MAP(backend_map);
1108 WREG32(GB_TILING_CONFIG, tiling_config);
1109 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1110 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1113 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1114 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1115 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1117 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1118 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1119 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1121 /* Setup some CP states */
1122 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1123 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1125 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1126 SYNC_WALKER | SYNC_ALIGNER));
1127 /* Setup various GPU states */
1128 if (rdev->family == CHIP_RV670)
1129 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1131 tmp = RREG32(SX_DEBUG_1);
1132 tmp |= SMX_EVENT_RELEASE;
1133 if ((rdev->family > CHIP_R600))
1134 tmp |= ENABLE_NEW_SMX_ADDRESS;
1135 WREG32(SX_DEBUG_1, tmp);
1137 if (((rdev->family) == CHIP_R600) ||
1138 ((rdev->family) == CHIP_RV630) ||
1139 ((rdev->family) == CHIP_RV610) ||
1140 ((rdev->family) == CHIP_RV620) ||
1141 ((rdev->family) == CHIP_RS780) ||
1142 ((rdev->family) == CHIP_RS880)) {
1143 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1145 WREG32(DB_DEBUG, 0);
1147 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1148 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1150 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1151 WREG32(VGT_NUM_INSTANCES, 0);
1153 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1154 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1156 tmp = RREG32(SQ_MS_FIFO_SIZES);
1157 if (((rdev->family) == CHIP_RV610) ||
1158 ((rdev->family) == CHIP_RV620) ||
1159 ((rdev->family) == CHIP_RS780) ||
1160 ((rdev->family) == CHIP_RS880)) {
1161 tmp = (CACHE_FIFO_SIZE(0xa) |
1162 FETCH_FIFO_HIWATER(0xa) |
1163 DONE_FIFO_HIWATER(0xe0) |
1164 ALU_UPDATE_FIFO_HIWATER(0x8));
1165 } else if (((rdev->family) == CHIP_R600) ||
1166 ((rdev->family) == CHIP_RV630)) {
1167 tmp &= ~DONE_FIFO_HIWATER(0xff);
1168 tmp |= DONE_FIFO_HIWATER(0x4);
1170 WREG32(SQ_MS_FIFO_SIZES, tmp);
1172 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1173 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1175 sq_config = RREG32(SQ_CONFIG);
1176 sq_config &= ~(PS_PRIO(3) |
1180 sq_config |= (DX9_CONSTS |
1187 if ((rdev->family) == CHIP_R600) {
1188 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1190 NUM_CLAUSE_TEMP_GPRS(4));
1191 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1193 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1194 NUM_VS_THREADS(48) |
1197 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1198 NUM_VS_STACK_ENTRIES(128));
1199 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1200 NUM_ES_STACK_ENTRIES(0));
1201 } else if (((rdev->family) == CHIP_RV610) ||
1202 ((rdev->family) == CHIP_RV620) ||
1203 ((rdev->family) == CHIP_RS780) ||
1204 ((rdev->family) == CHIP_RS880)) {
1205 /* no vertex cache */
1206 sq_config &= ~VC_ENABLE;
1208 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1210 NUM_CLAUSE_TEMP_GPRS(2));
1211 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1213 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1214 NUM_VS_THREADS(78) |
1216 NUM_ES_THREADS(31));
1217 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1218 NUM_VS_STACK_ENTRIES(40));
1219 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1220 NUM_ES_STACK_ENTRIES(16));
1221 } else if (((rdev->family) == CHIP_RV630) ||
1222 ((rdev->family) == CHIP_RV635)) {
1223 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1225 NUM_CLAUSE_TEMP_GPRS(2));
1226 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1228 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1229 NUM_VS_THREADS(78) |
1231 NUM_ES_THREADS(31));
1232 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1233 NUM_VS_STACK_ENTRIES(40));
1234 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1235 NUM_ES_STACK_ENTRIES(16));
1236 } else if ((rdev->family) == CHIP_RV670) {
1237 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1239 NUM_CLAUSE_TEMP_GPRS(2));
1240 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1242 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1243 NUM_VS_THREADS(78) |
1245 NUM_ES_THREADS(31));
1246 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1247 NUM_VS_STACK_ENTRIES(64));
1248 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1249 NUM_ES_STACK_ENTRIES(64));
1252 WREG32(SQ_CONFIG, sq_config);
1253 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1254 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1255 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1256 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1257 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1259 if (((rdev->family) == CHIP_RV610) ||
1260 ((rdev->family) == CHIP_RV620) ||
1261 ((rdev->family) == CHIP_RS780) ||
1262 ((rdev->family) == CHIP_RS880)) {
1263 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1265 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1268 /* More default values. 2D/3D driver should adjust as needed */
1269 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1270 S1_X(0x4) | S1_Y(0xc)));
1271 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1272 S1_X(0x2) | S1_Y(0x2) |
1273 S2_X(0xa) | S2_Y(0x6) |
1274 S3_X(0x6) | S3_Y(0xa)));
1275 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1276 S1_X(0x4) | S1_Y(0xc) |
1277 S2_X(0x1) | S2_Y(0x6) |
1278 S3_X(0xa) | S3_Y(0xe)));
1279 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1280 S5_X(0x0) | S5_Y(0x0) |
1281 S6_X(0xb) | S6_Y(0x4) |
1282 S7_X(0x7) | S7_Y(0x8)));
1284 WREG32(VGT_STRMOUT_EN, 0);
1285 tmp = rdev->config.r600.max_pipes * 16;
1286 switch (rdev->family) {
1302 WREG32(VGT_ES_PER_GS, 128);
1303 WREG32(VGT_GS_PER_ES, tmp);
1304 WREG32(VGT_GS_PER_VS, 2);
1305 WREG32(VGT_GS_VERTEX_REUSE, 16);
1307 /* more default values. 2D/3D driver should adjust as needed */
1308 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1309 WREG32(VGT_STRMOUT_EN, 0);
1311 WREG32(PA_SC_MODE_CNTL, 0);
1312 WREG32(PA_SC_AA_CONFIG, 0);
1313 WREG32(PA_SC_LINE_STIPPLE, 0);
1314 WREG32(SPI_INPUT_Z, 0);
1315 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1316 WREG32(CB_COLOR7_FRAG, 0);
1318 /* Clear render buffer base addresses */
1319 WREG32(CB_COLOR0_BASE, 0);
1320 WREG32(CB_COLOR1_BASE, 0);
1321 WREG32(CB_COLOR2_BASE, 0);
1322 WREG32(CB_COLOR3_BASE, 0);
1323 WREG32(CB_COLOR4_BASE, 0);
1324 WREG32(CB_COLOR5_BASE, 0);
1325 WREG32(CB_COLOR6_BASE, 0);
1326 WREG32(CB_COLOR7_BASE, 0);
1327 WREG32(CB_COLOR7_FRAG, 0);
1329 switch (rdev->family) {
1334 tmp = TC_L2_SIZE(8);
1338 tmp = TC_L2_SIZE(4);
1341 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1344 tmp = TC_L2_SIZE(0);
1347 WREG32(TC_CNTL, tmp);
1349 tmp = RREG32(HDP_HOST_PATH_CNTL);
1350 WREG32(HDP_HOST_PATH_CNTL, tmp);
1352 tmp = RREG32(ARB_POP);
1353 tmp |= ENABLE_TC128;
1354 WREG32(ARB_POP, tmp);
1356 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1357 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1359 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1364 * Indirect registers accessor
1366 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1370 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1371 (void)RREG32(PCIE_PORT_INDEX);
1372 r = RREG32(PCIE_PORT_DATA);
1376 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1378 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1379 (void)RREG32(PCIE_PORT_INDEX);
1380 WREG32(PCIE_PORT_DATA, (v));
1381 (void)RREG32(PCIE_PORT_DATA);
1387 void r600_cp_stop(struct radeon_device *rdev)
1389 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1392 int r600_init_microcode(struct radeon_device *rdev)
1394 struct platform_device *pdev;
1395 const char *chip_name;
1396 const char *rlc_chip_name;
1397 size_t pfp_req_size, me_req_size, rlc_req_size;
1403 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1406 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1410 switch (rdev->family) {
1413 rlc_chip_name = "R600";
1416 chip_name = "RV610";
1417 rlc_chip_name = "R600";
1420 chip_name = "RV630";
1421 rlc_chip_name = "R600";
1424 chip_name = "RV620";
1425 rlc_chip_name = "R600";
1428 chip_name = "RV635";
1429 rlc_chip_name = "R600";
1432 chip_name = "RV670";
1433 rlc_chip_name = "R600";
1437 chip_name = "RS780";
1438 rlc_chip_name = "R600";
1441 chip_name = "RV770";
1442 rlc_chip_name = "R700";
1446 chip_name = "RV730";
1447 rlc_chip_name = "R700";
1450 chip_name = "RV710";
1451 rlc_chip_name = "R700";
1456 if (rdev->family >= CHIP_RV770) {
1457 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1458 me_req_size = R700_PM4_UCODE_SIZE * 4;
1459 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
1461 pfp_req_size = PFP_UCODE_SIZE * 4;
1462 me_req_size = PM4_UCODE_SIZE * 12;
1463 rlc_req_size = RLC_UCODE_SIZE * 4;
1466 DRM_INFO("Loading %s Microcode\n", chip_name);
1468 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1469 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1472 if (rdev->pfp_fw->size != pfp_req_size) {
1474 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1475 rdev->pfp_fw->size, fw_name);
1480 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1481 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1484 if (rdev->me_fw->size != me_req_size) {
1486 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1487 rdev->me_fw->size, fw_name);
1491 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
1492 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
1495 if (rdev->rlc_fw->size != rlc_req_size) {
1497 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
1498 rdev->rlc_fw->size, fw_name);
1503 platform_device_unregister(pdev);
1508 "r600_cp: Failed to load firmware \"%s\"\n",
1510 release_firmware(rdev->pfp_fw);
1511 rdev->pfp_fw = NULL;
1512 release_firmware(rdev->me_fw);
1514 release_firmware(rdev->rlc_fw);
1515 rdev->rlc_fw = NULL;
1520 static int r600_cp_load_microcode(struct radeon_device *rdev)
1522 const __be32 *fw_data;
1525 if (!rdev->me_fw || !rdev->pfp_fw)
1530 WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1533 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1534 RREG32(GRBM_SOFT_RESET);
1536 WREG32(GRBM_SOFT_RESET, 0);
1538 WREG32(CP_ME_RAM_WADDR, 0);
1540 fw_data = (const __be32 *)rdev->me_fw->data;
1541 WREG32(CP_ME_RAM_WADDR, 0);
1542 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
1543 WREG32(CP_ME_RAM_DATA,
1544 be32_to_cpup(fw_data++));
1546 fw_data = (const __be32 *)rdev->pfp_fw->data;
1547 WREG32(CP_PFP_UCODE_ADDR, 0);
1548 for (i = 0; i < PFP_UCODE_SIZE; i++)
1549 WREG32(CP_PFP_UCODE_DATA,
1550 be32_to_cpup(fw_data++));
1552 WREG32(CP_PFP_UCODE_ADDR, 0);
1553 WREG32(CP_ME_RAM_WADDR, 0);
1554 WREG32(CP_ME_RAM_RADDR, 0);
1558 int r600_cp_start(struct radeon_device *rdev)
1563 r = radeon_ring_lock(rdev, 7);
1565 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1568 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1569 radeon_ring_write(rdev, 0x1);
1570 if (rdev->family < CHIP_RV770) {
1571 radeon_ring_write(rdev, 0x3);
1572 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
1574 radeon_ring_write(rdev, 0x0);
1575 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
1577 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1578 radeon_ring_write(rdev, 0);
1579 radeon_ring_write(rdev, 0);
1580 radeon_ring_unlock_commit(rdev);
1583 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
1587 int r600_cp_resume(struct radeon_device *rdev)
1594 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1595 RREG32(GRBM_SOFT_RESET);
1597 WREG32(GRBM_SOFT_RESET, 0);
1599 /* Set ring buffer size */
1600 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1601 tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1603 tmp |= BUF_SWAP_32BIT;
1605 WREG32(CP_RB_CNTL, tmp);
1606 WREG32(CP_SEM_WAIT_TIMER, 0x4);
1608 /* Set the write pointer delay */
1609 WREG32(CP_RB_WPTR_DELAY, 0);
1611 /* Initialize the ring buffer's read and write pointers */
1612 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1613 WREG32(CP_RB_RPTR_WR, 0);
1614 WREG32(CP_RB_WPTR, 0);
1615 WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
1616 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
1618 WREG32(CP_RB_CNTL, tmp);
1620 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1621 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1623 rdev->cp.rptr = RREG32(CP_RB_RPTR);
1624 rdev->cp.wptr = RREG32(CP_RB_WPTR);
1626 r600_cp_start(rdev);
1627 rdev->cp.ready = true;
1628 r = radeon_ring_test(rdev);
1630 rdev->cp.ready = false;
1636 void r600_cp_commit(struct radeon_device *rdev)
1638 WREG32(CP_RB_WPTR, rdev->cp.wptr);
1639 (void)RREG32(CP_RB_WPTR);
1642 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
1646 /* Align ring size */
1647 rb_bufsz = drm_order(ring_size / 8);
1648 ring_size = (1 << (rb_bufsz + 1)) * 4;
1649 rdev->cp.ring_size = ring_size;
1650 rdev->cp.align_mask = 16 - 1;
1653 void r600_cp_fini(struct radeon_device *rdev)
1656 radeon_ring_fini(rdev);
1661 * GPU scratch registers helpers function.
1663 void r600_scratch_init(struct radeon_device *rdev)
1667 rdev->scratch.num_reg = 7;
1668 for (i = 0; i < rdev->scratch.num_reg; i++) {
1669 rdev->scratch.free[i] = true;
1670 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
1674 int r600_ring_test(struct radeon_device *rdev)
1681 r = radeon_scratch_get(rdev, &scratch);
1683 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
1686 WREG32(scratch, 0xCAFEDEAD);
1687 r = radeon_ring_lock(rdev, 3);
1689 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1690 radeon_scratch_free(rdev, scratch);
1693 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1694 radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1695 radeon_ring_write(rdev, 0xDEADBEEF);
1696 radeon_ring_unlock_commit(rdev);
1697 for (i = 0; i < rdev->usec_timeout; i++) {
1698 tmp = RREG32(scratch);
1699 if (tmp == 0xDEADBEEF)
1703 if (i < rdev->usec_timeout) {
1704 DRM_INFO("ring test succeeded in %d usecs\n", i);
1706 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1710 radeon_scratch_free(rdev, scratch);
1714 void r600_wb_disable(struct radeon_device *rdev)
1718 WREG32(SCRATCH_UMSK, 0);
1719 if (rdev->wb.wb_obj) {
1720 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1721 if (unlikely(r != 0))
1723 radeon_bo_kunmap(rdev->wb.wb_obj);
1724 radeon_bo_unpin(rdev->wb.wb_obj);
1725 radeon_bo_unreserve(rdev->wb.wb_obj);
1729 void r600_wb_fini(struct radeon_device *rdev)
1731 r600_wb_disable(rdev);
1732 if (rdev->wb.wb_obj) {
1733 radeon_bo_unref(&rdev->wb.wb_obj);
1735 rdev->wb.wb_obj = NULL;
1739 int r600_wb_enable(struct radeon_device *rdev)
1743 if (rdev->wb.wb_obj == NULL) {
1744 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
1745 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
1747 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
1750 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1751 if (unlikely(r != 0)) {
1755 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
1756 &rdev->wb.gpu_addr);
1758 radeon_bo_unreserve(rdev->wb.wb_obj);
1759 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
1763 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
1764 radeon_bo_unreserve(rdev->wb.wb_obj);
1766 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
1771 WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
1772 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
1773 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
1774 WREG32(SCRATCH_UMSK, 0xff);
1778 void r600_fence_ring_emit(struct radeon_device *rdev,
1779 struct radeon_fence *fence)
1781 /* Also consider EVENT_WRITE_EOP. it handles the interrupts + timestamps + events */
1783 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
1784 radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
1785 /* wait for 3D idle clean */
1786 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1787 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
1788 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
1789 /* Emit fence sequence & fire IRQ */
1790 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1791 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1792 radeon_ring_write(rdev, fence->seq);
1793 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
1794 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
1795 radeon_ring_write(rdev, RB_INT_STAT);
1798 int r600_copy_blit(struct radeon_device *rdev,
1799 uint64_t src_offset, uint64_t dst_offset,
1800 unsigned num_pages, struct radeon_fence *fence)
1804 mutex_lock(&rdev->r600_blit.mutex);
1805 rdev->r600_blit.vb_ib = NULL;
1806 r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
1808 if (rdev->r600_blit.vb_ib)
1809 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
1810 mutex_unlock(&rdev->r600_blit.mutex);
1813 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
1814 r600_blit_done_copy(rdev, fence);
1815 mutex_unlock(&rdev->r600_blit.mutex);
1819 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
1820 uint32_t tiling_flags, uint32_t pitch,
1821 uint32_t offset, uint32_t obj_size)
1823 /* FIXME: implement */
1827 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
1829 /* FIXME: implement */
1833 bool r600_card_posted(struct radeon_device *rdev)
1837 /* first check CRTCs */
1838 reg = RREG32(D1CRTC_CONTROL) |
1839 RREG32(D2CRTC_CONTROL);
1843 /* then check MEM_SIZE, in case the crtcs are off */
1844 if (RREG32(CONFIG_MEMSIZE))
1850 int r600_startup(struct radeon_device *rdev)
1854 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1855 r = r600_init_microcode(rdev);
1857 DRM_ERROR("Failed to load firmware!\n");
1862 r600_mc_program(rdev);
1863 if (rdev->flags & RADEON_IS_AGP) {
1864 r600_agp_enable(rdev);
1866 r = r600_pcie_gart_enable(rdev);
1870 r600_gpu_init(rdev);
1871 r = r600_blit_init(rdev);
1873 r600_blit_fini(rdev);
1874 rdev->asic->copy = NULL;
1875 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1877 /* pin copy shader into vram */
1878 if (rdev->r600_blit.shader_obj) {
1879 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1880 if (unlikely(r != 0))
1882 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
1883 &rdev->r600_blit.shader_gpu_addr);
1884 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1886 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
1891 r = r600_irq_init(rdev);
1893 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1894 radeon_irq_kms_fini(rdev);
1899 r = radeon_ring_init(rdev, rdev->cp.ring_size);
1902 r = r600_cp_load_microcode(rdev);
1905 r = r600_cp_resume(rdev);
1908 /* write back buffer are not vital so don't worry about failure */
1909 r600_wb_enable(rdev);
1913 void r600_vga_set_state(struct radeon_device *rdev, bool state)
1917 temp = RREG32(CONFIG_CNTL);
1918 if (state == false) {
1924 WREG32(CONFIG_CNTL, temp);
1927 int r600_resume(struct radeon_device *rdev)
1931 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
1932 * posting will perform necessary task to bring back GPU into good
1936 atom_asic_init(rdev->mode_info.atom_context);
1937 /* Initialize clocks */
1938 r = radeon_clocks_init(rdev);
1943 r = r600_startup(rdev);
1945 DRM_ERROR("r600 startup failed on resume\n");
1949 r = r600_ib_test(rdev);
1951 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1955 r = r600_audio_init(rdev);
1957 DRM_ERROR("radeon: audio resume failed\n");
1964 int r600_suspend(struct radeon_device *rdev)
1968 r600_audio_fini(rdev);
1969 /* FIXME: we should wait for ring to be empty */
1971 rdev->cp.ready = false;
1972 r600_irq_suspend(rdev);
1973 r600_wb_disable(rdev);
1974 r600_pcie_gart_disable(rdev);
1975 /* unpin shaders bo */
1976 if (rdev->r600_blit.shader_obj) {
1977 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1979 radeon_bo_unpin(rdev->r600_blit.shader_obj);
1980 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1986 /* Plan is to move initialization in that function and use
1987 * helper function so that radeon_device_init pretty much
1988 * do nothing more than calling asic specific function. This
1989 * should also allow to remove a bunch of callback function
1992 int r600_init(struct radeon_device *rdev)
1996 r = radeon_dummy_page_init(rdev);
1999 if (r600_debugfs_mc_info_init(rdev)) {
2000 DRM_ERROR("Failed to register debugfs file for mc !\n");
2002 /* This don't do much */
2003 r = radeon_gem_init(rdev);
2007 if (!radeon_get_bios(rdev)) {
2008 if (ASIC_IS_AVIVO(rdev))
2011 /* Must be an ATOMBIOS */
2012 if (!rdev->is_atom_bios) {
2013 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2016 r = radeon_atombios_init(rdev);
2019 /* Post card if necessary */
2020 if (!r600_card_posted(rdev)) {
2022 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2025 DRM_INFO("GPU not posted. posting now...\n");
2026 atom_asic_init(rdev->mode_info.atom_context);
2028 /* Initialize scratch registers */
2029 r600_scratch_init(rdev);
2030 /* Initialize surface registers */
2031 radeon_surface_init(rdev);
2032 /* Initialize clocks */
2033 radeon_get_clock_info(rdev->ddev);
2034 r = radeon_clocks_init(rdev);
2037 /* Initialize power management */
2038 radeon_pm_init(rdev);
2040 r = radeon_fence_driver_init(rdev);
2043 if (rdev->flags & RADEON_IS_AGP) {
2044 r = radeon_agp_init(rdev);
2046 radeon_agp_disable(rdev);
2048 r = r600_mc_init(rdev);
2051 /* Memory manager */
2052 r = radeon_bo_init(rdev);
2056 r = radeon_irq_kms_init(rdev);
2060 rdev->cp.ring_obj = NULL;
2061 r600_ring_init(rdev, 1024 * 1024);
2063 rdev->ih.ring_obj = NULL;
2064 r600_ih_ring_init(rdev, 64 * 1024);
2066 r = r600_pcie_gart_init(rdev);
2070 rdev->accel_working = true;
2071 r = r600_startup(rdev);
2073 dev_err(rdev->dev, "disabling GPU acceleration\n");
2076 r600_irq_fini(rdev);
2077 radeon_irq_kms_fini(rdev);
2078 r600_pcie_gart_fini(rdev);
2079 rdev->accel_working = false;
2081 if (rdev->accel_working) {
2082 r = radeon_ib_pool_init(rdev);
2084 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2085 rdev->accel_working = false;
2087 r = r600_ib_test(rdev);
2089 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2090 rdev->accel_working = false;
2095 r = r600_audio_init(rdev);
2097 return r; /* TODO error handling */
2101 void r600_fini(struct radeon_device *rdev)
2103 radeon_pm_fini(rdev);
2104 r600_audio_fini(rdev);
2105 r600_blit_fini(rdev);
2108 r600_irq_fini(rdev);
2109 radeon_irq_kms_fini(rdev);
2110 r600_pcie_gart_fini(rdev);
2111 radeon_agp_fini(rdev);
2112 radeon_gem_fini(rdev);
2113 radeon_fence_driver_fini(rdev);
2114 radeon_clocks_fini(rdev);
2115 radeon_bo_fini(rdev);
2116 radeon_atombios_fini(rdev);
2119 radeon_dummy_page_fini(rdev);
2126 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2128 /* FIXME: implement */
2129 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2130 radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2131 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2132 radeon_ring_write(rdev, ib->length_dw);
2135 int r600_ib_test(struct radeon_device *rdev)
2137 struct radeon_ib *ib;
2143 r = radeon_scratch_get(rdev, &scratch);
2145 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2148 WREG32(scratch, 0xCAFEDEAD);
2149 r = radeon_ib_get(rdev, &ib);
2151 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2154 ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2155 ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2156 ib->ptr[2] = 0xDEADBEEF;
2157 ib->ptr[3] = PACKET2(0);
2158 ib->ptr[4] = PACKET2(0);
2159 ib->ptr[5] = PACKET2(0);
2160 ib->ptr[6] = PACKET2(0);
2161 ib->ptr[7] = PACKET2(0);
2162 ib->ptr[8] = PACKET2(0);
2163 ib->ptr[9] = PACKET2(0);
2164 ib->ptr[10] = PACKET2(0);
2165 ib->ptr[11] = PACKET2(0);
2166 ib->ptr[12] = PACKET2(0);
2167 ib->ptr[13] = PACKET2(0);
2168 ib->ptr[14] = PACKET2(0);
2169 ib->ptr[15] = PACKET2(0);
2171 r = radeon_ib_schedule(rdev, ib);
2173 radeon_scratch_free(rdev, scratch);
2174 radeon_ib_free(rdev, &ib);
2175 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2178 r = radeon_fence_wait(ib->fence, false);
2180 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2183 for (i = 0; i < rdev->usec_timeout; i++) {
2184 tmp = RREG32(scratch);
2185 if (tmp == 0xDEADBEEF)
2189 if (i < rdev->usec_timeout) {
2190 DRM_INFO("ib test succeeded in %u usecs\n", i);
2192 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
2196 radeon_scratch_free(rdev, scratch);
2197 radeon_ib_free(rdev, &ib);
2204 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
2205 * the same as the CP ring buffer, but in reverse. Rather than the CPU
2206 * writing to the ring and the GPU consuming, the GPU writes to the ring
2207 * and host consumes. As the host irq handler processes interrupts, it
2208 * increments the rptr. When the rptr catches up with the wptr, all the
2209 * current interrupts have been processed.
2212 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2216 /* Align ring size */
2217 rb_bufsz = drm_order(ring_size / 4);
2218 ring_size = (1 << rb_bufsz) * 4;
2219 rdev->ih.ring_size = ring_size;
2220 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2224 static int r600_ih_ring_alloc(struct radeon_device *rdev)
2228 /* Allocate ring buffer */
2229 if (rdev->ih.ring_obj == NULL) {
2230 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2232 RADEON_GEM_DOMAIN_GTT,
2233 &rdev->ih.ring_obj);
2235 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2238 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2239 if (unlikely(r != 0))
2241 r = radeon_bo_pin(rdev->ih.ring_obj,
2242 RADEON_GEM_DOMAIN_GTT,
2243 &rdev->ih.gpu_addr);
2245 radeon_bo_unreserve(rdev->ih.ring_obj);
2246 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2249 r = radeon_bo_kmap(rdev->ih.ring_obj,
2250 (void **)&rdev->ih.ring);
2251 radeon_bo_unreserve(rdev->ih.ring_obj);
2253 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2260 static void r600_ih_ring_fini(struct radeon_device *rdev)
2263 if (rdev->ih.ring_obj) {
2264 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2265 if (likely(r == 0)) {
2266 radeon_bo_kunmap(rdev->ih.ring_obj);
2267 radeon_bo_unpin(rdev->ih.ring_obj);
2268 radeon_bo_unreserve(rdev->ih.ring_obj);
2270 radeon_bo_unref(&rdev->ih.ring_obj);
2271 rdev->ih.ring = NULL;
2272 rdev->ih.ring_obj = NULL;
2276 static void r600_rlc_stop(struct radeon_device *rdev)
2279 if (rdev->family >= CHIP_RV770) {
2280 /* r7xx asics need to soft reset RLC before halting */
2281 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2282 RREG32(SRBM_SOFT_RESET);
2284 WREG32(SRBM_SOFT_RESET, 0);
2285 RREG32(SRBM_SOFT_RESET);
2288 WREG32(RLC_CNTL, 0);
2291 static void r600_rlc_start(struct radeon_device *rdev)
2293 WREG32(RLC_CNTL, RLC_ENABLE);
2296 static int r600_rlc_init(struct radeon_device *rdev)
2299 const __be32 *fw_data;
2304 r600_rlc_stop(rdev);
2306 WREG32(RLC_HB_BASE, 0);
2307 WREG32(RLC_HB_CNTL, 0);
2308 WREG32(RLC_HB_RPTR, 0);
2309 WREG32(RLC_HB_WPTR, 0);
2310 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2311 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2312 WREG32(RLC_MC_CNTL, 0);
2313 WREG32(RLC_UCODE_CNTL, 0);
2315 fw_data = (const __be32 *)rdev->rlc_fw->data;
2316 if (rdev->family >= CHIP_RV770) {
2317 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2318 WREG32(RLC_UCODE_ADDR, i);
2319 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2322 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2323 WREG32(RLC_UCODE_ADDR, i);
2324 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2327 WREG32(RLC_UCODE_ADDR, 0);
2329 r600_rlc_start(rdev);
2334 static void r600_enable_interrupts(struct radeon_device *rdev)
2336 u32 ih_cntl = RREG32(IH_CNTL);
2337 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2339 ih_cntl |= ENABLE_INTR;
2340 ih_rb_cntl |= IH_RB_ENABLE;
2341 WREG32(IH_CNTL, ih_cntl);
2342 WREG32(IH_RB_CNTL, ih_rb_cntl);
2343 rdev->ih.enabled = true;
2346 static void r600_disable_interrupts(struct radeon_device *rdev)
2348 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2349 u32 ih_cntl = RREG32(IH_CNTL);
2351 ih_rb_cntl &= ~IH_RB_ENABLE;
2352 ih_cntl &= ~ENABLE_INTR;
2353 WREG32(IH_RB_CNTL, ih_rb_cntl);
2354 WREG32(IH_CNTL, ih_cntl);
2355 /* set rptr, wptr to 0 */
2356 WREG32(IH_RB_RPTR, 0);
2357 WREG32(IH_RB_WPTR, 0);
2358 rdev->ih.enabled = false;
2363 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2367 WREG32(CP_INT_CNTL, 0);
2368 WREG32(GRBM_INT_CNTL, 0);
2369 WREG32(DxMODE_INT_MASK, 0);
2370 if (ASIC_IS_DCE3(rdev)) {
2371 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2372 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2373 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2374 WREG32(DC_HPD1_INT_CONTROL, tmp);
2375 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2376 WREG32(DC_HPD2_INT_CONTROL, tmp);
2377 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2378 WREG32(DC_HPD3_INT_CONTROL, tmp);
2379 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2380 WREG32(DC_HPD4_INT_CONTROL, tmp);
2381 if (ASIC_IS_DCE32(rdev)) {
2382 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2383 WREG32(DC_HPD5_INT_CONTROL, tmp);
2384 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2385 WREG32(DC_HPD6_INT_CONTROL, tmp);
2388 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2389 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2390 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2391 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2392 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2393 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2394 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2395 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2399 int r600_irq_init(struct radeon_device *rdev)
2403 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2406 ret = r600_ih_ring_alloc(rdev);
2411 r600_disable_interrupts(rdev);
2414 ret = r600_rlc_init(rdev);
2416 r600_ih_ring_fini(rdev);
2420 /* setup interrupt control */
2421 /* set dummy read address to ring address */
2422 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2423 interrupt_cntl = RREG32(INTERRUPT_CNTL);
2424 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2425 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2427 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2428 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2429 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2430 WREG32(INTERRUPT_CNTL, interrupt_cntl);
2432 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2433 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2435 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2436 IH_WPTR_OVERFLOW_CLEAR |
2438 /* WPTR writeback, not yet */
2439 /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/
2440 WREG32(IH_RB_WPTR_ADDR_LO, 0);
2441 WREG32(IH_RB_WPTR_ADDR_HI, 0);
2443 WREG32(IH_RB_CNTL, ih_rb_cntl);
2445 /* set rptr, wptr to 0 */
2446 WREG32(IH_RB_RPTR, 0);
2447 WREG32(IH_RB_WPTR, 0);
2449 /* Default settings for IH_CNTL (disabled at first) */
2450 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2451 /* RPTR_REARM only works if msi's are enabled */
2452 if (rdev->msi_enabled)
2453 ih_cntl |= RPTR_REARM;
2456 ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2458 WREG32(IH_CNTL, ih_cntl);
2460 /* force the active interrupt state to all disabled */
2461 r600_disable_interrupt_state(rdev);
2464 r600_enable_interrupts(rdev);
2469 void r600_irq_suspend(struct radeon_device *rdev)
2471 r600_disable_interrupts(rdev);
2472 r600_rlc_stop(rdev);
2475 void r600_irq_fini(struct radeon_device *rdev)
2477 r600_irq_suspend(rdev);
2478 r600_ih_ring_fini(rdev);
2481 int r600_irq_set(struct radeon_device *rdev)
2483 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2485 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2487 if (!rdev->irq.installed) {
2488 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
2491 /* don't enable anything if the ih is disabled */
2492 if (!rdev->ih.enabled) {
2493 r600_disable_interrupts(rdev);
2494 /* force the active interrupt state to all disabled */
2495 r600_disable_interrupt_state(rdev);
2499 if (ASIC_IS_DCE3(rdev)) {
2500 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2501 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2502 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2503 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2504 if (ASIC_IS_DCE32(rdev)) {
2505 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2506 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2509 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2510 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2511 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2514 if (rdev->irq.sw_int) {
2515 DRM_DEBUG("r600_irq_set: sw int\n");
2516 cp_int_cntl |= RB_INT_ENABLE;
2518 if (rdev->irq.crtc_vblank_int[0]) {
2519 DRM_DEBUG("r600_irq_set: vblank 0\n");
2520 mode_int |= D1MODE_VBLANK_INT_MASK;
2522 if (rdev->irq.crtc_vblank_int[1]) {
2523 DRM_DEBUG("r600_irq_set: vblank 1\n");
2524 mode_int |= D2MODE_VBLANK_INT_MASK;
2526 if (rdev->irq.hpd[0]) {
2527 DRM_DEBUG("r600_irq_set: hpd 1\n");
2528 hpd1 |= DC_HPDx_INT_EN;
2530 if (rdev->irq.hpd[1]) {
2531 DRM_DEBUG("r600_irq_set: hpd 2\n");
2532 hpd2 |= DC_HPDx_INT_EN;
2534 if (rdev->irq.hpd[2]) {
2535 DRM_DEBUG("r600_irq_set: hpd 3\n");
2536 hpd3 |= DC_HPDx_INT_EN;
2538 if (rdev->irq.hpd[3]) {
2539 DRM_DEBUG("r600_irq_set: hpd 4\n");
2540 hpd4 |= DC_HPDx_INT_EN;
2542 if (rdev->irq.hpd[4]) {
2543 DRM_DEBUG("r600_irq_set: hpd 5\n");
2544 hpd5 |= DC_HPDx_INT_EN;
2546 if (rdev->irq.hpd[5]) {
2547 DRM_DEBUG("r600_irq_set: hpd 6\n");
2548 hpd6 |= DC_HPDx_INT_EN;
2551 WREG32(CP_INT_CNTL, cp_int_cntl);
2552 WREG32(DxMODE_INT_MASK, mode_int);
2553 if (ASIC_IS_DCE3(rdev)) {
2554 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2555 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2556 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2557 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2558 if (ASIC_IS_DCE32(rdev)) {
2559 WREG32(DC_HPD5_INT_CONTROL, hpd5);
2560 WREG32(DC_HPD6_INT_CONTROL, hpd6);
2563 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
2564 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
2565 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
2571 static inline void r600_irq_ack(struct radeon_device *rdev,
2574 u32 *disp_int_cont2)
2578 if (ASIC_IS_DCE3(rdev)) {
2579 *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
2580 *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
2581 *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
2583 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
2584 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2585 *disp_int_cont2 = 0;
2588 if (*disp_int & LB_D1_VBLANK_INTERRUPT)
2589 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2590 if (*disp_int & LB_D1_VLINE_INTERRUPT)
2591 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2592 if (*disp_int & LB_D2_VBLANK_INTERRUPT)
2593 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2594 if (*disp_int & LB_D2_VLINE_INTERRUPT)
2595 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2596 if (*disp_int & DC_HPD1_INTERRUPT) {
2597 if (ASIC_IS_DCE3(rdev)) {
2598 tmp = RREG32(DC_HPD1_INT_CONTROL);
2599 tmp |= DC_HPDx_INT_ACK;
2600 WREG32(DC_HPD1_INT_CONTROL, tmp);
2602 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
2603 tmp |= DC_HPDx_INT_ACK;
2604 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2607 if (*disp_int & DC_HPD2_INTERRUPT) {
2608 if (ASIC_IS_DCE3(rdev)) {
2609 tmp = RREG32(DC_HPD2_INT_CONTROL);
2610 tmp |= DC_HPDx_INT_ACK;
2611 WREG32(DC_HPD2_INT_CONTROL, tmp);
2613 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
2614 tmp |= DC_HPDx_INT_ACK;
2615 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2618 if (*disp_int_cont & DC_HPD3_INTERRUPT) {
2619 if (ASIC_IS_DCE3(rdev)) {
2620 tmp = RREG32(DC_HPD3_INT_CONTROL);
2621 tmp |= DC_HPDx_INT_ACK;
2622 WREG32(DC_HPD3_INT_CONTROL, tmp);
2624 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
2625 tmp |= DC_HPDx_INT_ACK;
2626 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2629 if (*disp_int_cont & DC_HPD4_INTERRUPT) {
2630 tmp = RREG32(DC_HPD4_INT_CONTROL);
2631 tmp |= DC_HPDx_INT_ACK;
2632 WREG32(DC_HPD4_INT_CONTROL, tmp);
2634 if (ASIC_IS_DCE32(rdev)) {
2635 if (*disp_int_cont2 & DC_HPD5_INTERRUPT) {
2636 tmp = RREG32(DC_HPD5_INT_CONTROL);
2637 tmp |= DC_HPDx_INT_ACK;
2638 WREG32(DC_HPD5_INT_CONTROL, tmp);
2640 if (*disp_int_cont2 & DC_HPD6_INTERRUPT) {
2641 tmp = RREG32(DC_HPD5_INT_CONTROL);
2642 tmp |= DC_HPDx_INT_ACK;
2643 WREG32(DC_HPD6_INT_CONTROL, tmp);
2648 void r600_irq_disable(struct radeon_device *rdev)
2650 u32 disp_int, disp_int_cont, disp_int_cont2;
2652 r600_disable_interrupts(rdev);
2653 /* Wait and acknowledge irq */
2655 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
2656 r600_disable_interrupt_state(rdev);
2659 static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
2663 /* XXX use writeback */
2664 wptr = RREG32(IH_RB_WPTR);
2666 if (wptr & RB_OVERFLOW) {
2667 /* When a ring buffer overflow happen start parsing interrupt
2668 * from the last not overwritten vector (wptr + 16). Hopefully
2669 * this should allow us to catchup.
2671 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2672 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2673 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2674 tmp = RREG32(IH_RB_CNTL);
2675 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2676 WREG32(IH_RB_CNTL, tmp);
2678 return (wptr & rdev->ih.ptr_mask);
2682 * Each IV ring entry is 128 bits:
2683 * [7:0] - interrupt source id
2685 * [59:32] - interrupt source data
2686 * [127:60] - reserved
2688 * The basic interrupt vector entries
2689 * are decoded as follows:
2690 * src_id src_data description
2695 * 19 0 FP Hot plug detection A
2696 * 19 1 FP Hot plug detection B
2697 * 19 2 DAC A auto-detection
2698 * 19 3 DAC B auto-detection
2702 * 181 - EOP Interrupt
2705 * Note, these are based on r600 and may need to be
2706 * adjusted or added to on newer asics
2709 int r600_irq_process(struct radeon_device *rdev)
2711 u32 wptr = r600_get_ih_wptr(rdev);
2712 u32 rptr = rdev->ih.rptr;
2713 u32 src_id, src_data;
2714 u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
2715 unsigned long flags;
2716 bool queue_hotplug = false;
2718 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2719 if (!rdev->ih.enabled)
2722 spin_lock_irqsave(&rdev->ih.lock, flags);
2725 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2728 if (rdev->shutdown) {
2729 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2734 /* display interrupts */
2735 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
2737 rdev->ih.wptr = wptr;
2738 while (rptr != wptr) {
2739 /* wptr/rptr are in bytes! */
2740 ring_index = rptr / 4;
2741 src_id = rdev->ih.ring[ring_index] & 0xff;
2742 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
2745 case 1: /* D1 vblank/vline */
2747 case 0: /* D1 vblank */
2748 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
2749 drm_handle_vblank(rdev->ddev, 0);
2750 rdev->pm.vblank_sync = true;
2751 wake_up(&rdev->irq.vblank_queue);
2752 disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2753 DRM_DEBUG("IH: D1 vblank\n");
2756 case 1: /* D1 vline */
2757 if (disp_int & LB_D1_VLINE_INTERRUPT) {
2758 disp_int &= ~LB_D1_VLINE_INTERRUPT;
2759 DRM_DEBUG("IH: D1 vline\n");
2763 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2767 case 5: /* D2 vblank/vline */
2769 case 0: /* D2 vblank */
2770 if (disp_int & LB_D2_VBLANK_INTERRUPT) {
2771 drm_handle_vblank(rdev->ddev, 1);
2772 rdev->pm.vblank_sync = true;
2773 wake_up(&rdev->irq.vblank_queue);
2774 disp_int &= ~LB_D2_VBLANK_INTERRUPT;
2775 DRM_DEBUG("IH: D2 vblank\n");
2778 case 1: /* D1 vline */
2779 if (disp_int & LB_D2_VLINE_INTERRUPT) {
2780 disp_int &= ~LB_D2_VLINE_INTERRUPT;
2781 DRM_DEBUG("IH: D2 vline\n");
2785 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2789 case 19: /* HPD/DAC hotplug */
2792 if (disp_int & DC_HPD1_INTERRUPT) {
2793 disp_int &= ~DC_HPD1_INTERRUPT;
2794 queue_hotplug = true;
2795 DRM_DEBUG("IH: HPD1\n");
2799 if (disp_int & DC_HPD2_INTERRUPT) {
2800 disp_int &= ~DC_HPD2_INTERRUPT;
2801 queue_hotplug = true;
2802 DRM_DEBUG("IH: HPD2\n");
2806 if (disp_int_cont & DC_HPD3_INTERRUPT) {
2807 disp_int_cont &= ~DC_HPD3_INTERRUPT;
2808 queue_hotplug = true;
2809 DRM_DEBUG("IH: HPD3\n");
2813 if (disp_int_cont & DC_HPD4_INTERRUPT) {
2814 disp_int_cont &= ~DC_HPD4_INTERRUPT;
2815 queue_hotplug = true;
2816 DRM_DEBUG("IH: HPD4\n");
2820 if (disp_int_cont2 & DC_HPD5_INTERRUPT) {
2821 disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
2822 queue_hotplug = true;
2823 DRM_DEBUG("IH: HPD5\n");
2827 if (disp_int_cont2 & DC_HPD6_INTERRUPT) {
2828 disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
2829 queue_hotplug = true;
2830 DRM_DEBUG("IH: HPD6\n");
2834 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2838 case 176: /* CP_INT in ring buffer */
2839 case 177: /* CP_INT in IB1 */
2840 case 178: /* CP_INT in IB2 */
2841 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2842 radeon_fence_process(rdev);
2844 case 181: /* CP EOP event */
2845 DRM_DEBUG("IH: CP EOP\n");
2848 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2852 /* wptr/rptr are in bytes! */
2854 rptr &= rdev->ih.ptr_mask;
2856 /* make sure wptr hasn't changed while processing */
2857 wptr = r600_get_ih_wptr(rdev);
2858 if (wptr != rdev->ih.wptr)
2861 queue_work(rdev->wq, &rdev->hotplug_work);
2862 rdev->ih.rptr = rptr;
2863 WREG32(IH_RB_RPTR, rdev->ih.rptr);
2864 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2871 #if defined(CONFIG_DEBUG_FS)
2873 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
2875 struct drm_info_node *node = (struct drm_info_node *) m->private;
2876 struct drm_device *dev = node->minor->dev;
2877 struct radeon_device *rdev = dev->dev_private;
2878 unsigned count, i, j;
2880 radeon_ring_free_size(rdev);
2881 count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
2882 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
2883 seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
2884 seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
2885 seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
2886 seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
2887 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2888 seq_printf(m, "%u dwords in ring\n", count);
2890 for (j = 0; j <= count; j++) {
2891 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2892 i = (i + 1) & rdev->cp.ptr_mask;
2897 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
2899 struct drm_info_node *node = (struct drm_info_node *) m->private;
2900 struct drm_device *dev = node->minor->dev;
2901 struct radeon_device *rdev = dev->dev_private;
2903 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
2904 DREG32_SYS(m, rdev, VM_L2_STATUS);
2908 static struct drm_info_list r600_mc_info_list[] = {
2909 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
2910 {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
2914 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
2916 #if defined(CONFIG_DEBUG_FS)
2917 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
2924 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
2925 * rdev: radeon device structure
2926 * bo: buffer object struct which userspace is waiting for idle
2928 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
2929 * through ring buffer, this leads to corruption in rendering, see
2930 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
2931 * directly perform HDP flush by writing register through MMIO.
2933 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
2935 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);