drivers/gpu/drm/radeon/atombios_encoders.c

   1 /*
   2  * Copyright 2007-11 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "drm_crtc_helper.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 extern int atom_debug;
  33
  34 /* evil but including atombios.h is much worse */
  35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
  36                                 struct drm_display_mode *mode);
  37
  38
  39 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
  40 {
  41         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  42         switch (radeon_encoder->encoder_id) {
  43         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
  44         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
  45         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
  46         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
  47         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
  48         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
  49         case ENCODER_OBJECT_ID_INTERNAL_DDI:
  50         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
  51         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
  52         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
  53         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
  54                 return true;
  55         default:
  56                 return false;
  57         }
  58 }
  59
  60 static struct drm_connector *
  61 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder)
  62 {
  63         struct drm_device *dev = encoder->dev;
  64         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  65         struct drm_connector *connector;
  66         struct radeon_connector *radeon_connector;
  67
  68         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  69                 radeon_connector = to_radeon_connector(connector);
  70                 if (radeon_encoder->devices & radeon_connector->devices)
  71                         return connector;
  72         }
  73         return NULL;
  74 }
  75
  76 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
  77                                    struct drm_display_mode *mode,
  78                                    struct drm_display_mode *adjusted_mode)
  79 {
  80         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  81         struct drm_device *dev = encoder->dev;
  82         struct radeon_device *rdev = dev->dev_private;
  83
  84         /* set the active encoder to connector routing */
  85         radeon_encoder_set_active_device(encoder);
  86         drm_mode_set_crtcinfo(adjusted_mode, 0);
  87
  88         /* hw bug */
  89         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
  90             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
  91                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
  92
  93         /* get the native mode for LVDS */
  94         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
  95                 radeon_panel_mode_fixup(encoder, adjusted_mode);
  96
  97         /* get the native mode for TV */
  98         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
  99                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 100                 if (tv_dac) {
 101                         if (tv_dac->tv_std == TV_STD_NTSC ||
 102                             tv_dac->tv_std == TV_STD_NTSC_J ||
 103                             tv_dac->tv_std == TV_STD_PAL_M)
 104                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
 105                         else
 106                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
 107                 }
 108         }
 109
 110         if (ASIC_IS_DCE3(rdev) &&
 111             ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
 112              (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
 113                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 114                 radeon_dp_set_link_config(connector, adjusted_mode);
 115         }
 116
 117         return true;
 118 }
 119
 120 static void
 121 atombios_dac_setup(struct drm_encoder *encoder, int action)
 122 {
 123         struct drm_device *dev = encoder->dev;
 124         struct radeon_device *rdev = dev->dev_private;
 125         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 126         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 127         int index = 0;
 128         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 129
 130         memset(&args, 0, sizeof(args));
 131
 132         switch (radeon_encoder->encoder_id) {
 133         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 134         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 135                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 136                 break;
 137         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 138         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 139                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 140                 break;
 141         }
 142
 143         args.ucAction = action;
 144
 145         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 146                 args.ucDacStandard = ATOM_DAC1_PS2;
 147         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 148                 args.ucDacStandard = ATOM_DAC1_CV;
 149         else {
 150                 switch (dac_info->tv_std) {
 151                 case TV_STD_PAL:
 152                 case TV_STD_PAL_M:
 153                 case TV_STD_SCART_PAL:
 154                 case TV_STD_SECAM:
 155                 case TV_STD_PAL_CN:
 156                         args.ucDacStandard = ATOM_DAC1_PAL;
 157                         break;
 158                 case TV_STD_NTSC:
 159                 case TV_STD_NTSC_J:
 160                 case TV_STD_PAL_60:
 161                 default:
 162                         args.ucDacStandard = ATOM_DAC1_NTSC;
 163                         break;
 164                 }
 165         }
 166         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 167
 168         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 169
 170 }
 171
 172 static void
 173 atombios_tv_setup(struct drm_encoder *encoder, int action)
 174 {
 175         struct drm_device *dev = encoder->dev;
 176         struct radeon_device *rdev = dev->dev_private;
 177         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 178         TV_ENCODER_CONTROL_PS_ALLOCATION args;
 179         int index = 0;
 180         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 181
 182         memset(&args, 0, sizeof(args));
 183
 184         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 185
 186         args.sTVEncoder.ucAction = action;
 187
 188         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 189                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 190         else {
 191                 switch (dac_info->tv_std) {
 192                 case TV_STD_NTSC:
 193                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 194                         break;
 195                 case TV_STD_PAL:
 196                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 197                         break;
 198                 case TV_STD_PAL_M:
 199                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 200                         break;
 201                 case TV_STD_PAL_60:
 202                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 203                         break;
 204                 case TV_STD_NTSC_J:
 205                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 206                         break;
 207                 case TV_STD_SCART_PAL:
 208                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 209                         break;
 210                 case TV_STD_SECAM:
 211                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 212                         break;
 213                 case TV_STD_PAL_CN:
 214                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 215                         break;
 216                 default:
 217                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 218                         break;
 219                 }
 220         }
 221
 222         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 223
 224         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 225
 226 }
 227
 228 union dvo_encoder_control {
 229         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
 230         DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
 231         DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
 232 };
 233
 234 void
 235 atombios_dvo_setup(struct drm_encoder *encoder, int action)
 236 {
 237         struct drm_device *dev = encoder->dev;
 238         struct radeon_device *rdev = dev->dev_private;
 239         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 240         union dvo_encoder_control args;
 241         int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 242         uint8_t frev, crev;
 243
 244         memset(&args, 0, sizeof(args));
 245
 246         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 247                 return;
 248
 249         /* some R4xx chips have the wrong frev */
 250         if (rdev->family <= CHIP_RV410)
 251                 frev = 1;
 252
 253         switch (frev) {
 254         case 1:
 255                 switch (crev) {
 256                 case 1:
 257                         /* R4xx, R5xx */
 258                         args.ext_tmds.sXTmdsEncoder.ucEnable = action;
 259
 260                         if (radeon_encoder->pixel_clock > 165000)
 261                                 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 262
 263                         args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
 264                         break;
 265                 case 2:
 266                         /* RS600/690/740 */
 267                         args.dvo.sDVOEncoder.ucAction = action;
 268                         args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 269                         /* DFP1, CRT1, TV1 depending on the type of port */
 270                         args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
 271
 272                         if (radeon_encoder->pixel_clock > 165000)
 273                                 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
 274                         break;
 275                 case 3:
 276                         /* R6xx */
 277                         args.dvo_v3.ucAction = action;
 278                         args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 279                         args.dvo_v3.ucDVOConfig = 0; /* XXX */
 280                         break;
 281                 default:
 282                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 283                         break;
 284                 }
 285                 break;
 286         default:
 287                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 288                 break;
 289         }
 290
 291         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 292 }
 293
 294 union lvds_encoder_control {
 295         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 296         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 297 };
 298
 299 void
 300 atombios_digital_setup(struct drm_encoder *encoder, int action)
 301 {
 302         struct drm_device *dev = encoder->dev;
 303         struct radeon_device *rdev = dev->dev_private;
 304         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 305         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 306         union lvds_encoder_control args;
 307         int index = 0;
 308         int hdmi_detected = 0;
 309         uint8_t frev, crev;
 310
 311         if (!dig)
 312                 return;
 313
 314         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
 315                 hdmi_detected = 1;
 316
 317         memset(&args, 0, sizeof(args));
 318
 319         switch (radeon_encoder->encoder_id) {
 320         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 321                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 322                 break;
 323         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 324         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 325                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 326                 break;
 327         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 328                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 329                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 330                 else
 331                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 332                 break;
 333         }
 334
 335         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 336                 return;
 337
 338         switch (frev) {
 339         case 1:
 340         case 2:
 341                 switch (crev) {
 342                 case 1:
 343                         args.v1.ucMisc = 0;
 344                         args.v1.ucAction = action;
 345                         if (hdmi_detected)
 346                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 347                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 348                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 349                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 350                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 351                                 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 352                                         args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 353                         } else {
 354                                 if (dig->linkb)
 355                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 356                                 if (radeon_encoder->pixel_clock > 165000)
 357                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 358                                 /*if (pScrn->rgbBits == 8) */
 359                                 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 360                         }
 361                         break;
 362                 case 2:
 363                 case 3:
 364                         args.v2.ucMisc = 0;
 365                         args.v2.ucAction = action;
 366                         if (crev == 3) {
 367                                 if (dig->coherent_mode)
 368                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 369                         }
 370                         if (hdmi_detected)
 371                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 372                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 373                         args.v2.ucTruncate = 0;
 374                         args.v2.ucSpatial = 0;
 375                         args.v2.ucTemporal = 0;
 376                         args.v2.ucFRC = 0;
 377                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 378                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 379                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 380                                 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
 381                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 382                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 383                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 384                                 }
 385                                 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
 386                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 387                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 388                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 389                                         if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
 390                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 391                                 }
 392                         } else {
 393                                 if (dig->linkb)
 394                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 395                                 if (radeon_encoder->pixel_clock > 165000)
 396                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 397                         }
 398                         break;
 399                 default:
 400                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 401                         break;
 402                 }
 403                 break;
 404         default:
 405                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 406                 break;
 407         }
 408
 409         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 410 }
 411
 412 int
 413 atombios_get_encoder_mode(struct drm_encoder *encoder)
 414 {
 415         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 416         struct drm_device *dev = encoder->dev;
 417         struct radeon_device *rdev = dev->dev_private;
 418         struct drm_connector *connector;
 419         struct radeon_connector *radeon_connector;
 420         struct radeon_connector_atom_dig *dig_connector;
 421
 422         /* dp bridges are always DP */
 423         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
 424                 return ATOM_ENCODER_MODE_DP;
 425
 426         /* DVO is always DVO */
 427         if (radeon_encoder->encoder_id == ATOM_ENCODER_MODE_DVO)
 428                 return ATOM_ENCODER_MODE_DVO;
 429
 430         connector = radeon_get_connector_for_encoder(encoder);
 431         /* if we don't have an active device yet, just use one of
 432          * the connectors tied to the encoder.
 433          */
 434         if (!connector)
 435                 connector = radeon_get_connector_for_encoder_init(encoder);
 436         radeon_connector = to_radeon_connector(connector);
 437
 438         switch (connector->connector_type) {
 439         case DRM_MODE_CONNECTOR_DVII:
 440         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 441                 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
 442                         /* fix me */
 443                         if (ASIC_IS_DCE4(rdev))
 444                                 return ATOM_ENCODER_MODE_DVI;
 445                         else
 446                                 return ATOM_ENCODER_MODE_HDMI;
 447                 } else if (radeon_connector->use_digital)
 448                         return ATOM_ENCODER_MODE_DVI;
 449                 else
 450                         return ATOM_ENCODER_MODE_CRT;
 451                 break;
 452         case DRM_MODE_CONNECTOR_DVID:
 453         case DRM_MODE_CONNECTOR_HDMIA:
 454         default:
 455                 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
 456                         /* fix me */
 457                         if (ASIC_IS_DCE4(rdev))
 458                                 return ATOM_ENCODER_MODE_DVI;
 459                         else
 460                                 return ATOM_ENCODER_MODE_HDMI;
 461                 } else
 462                         return ATOM_ENCODER_MODE_DVI;
 463                 break;
 464         case DRM_MODE_CONNECTOR_LVDS:
 465                 return ATOM_ENCODER_MODE_LVDS;
 466                 break;
 467         case DRM_MODE_CONNECTOR_DisplayPort:
 468                 dig_connector = radeon_connector->con_priv;
 469                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 470                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
 471                         return ATOM_ENCODER_MODE_DP;
 472                 else if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
 473                         /* fix me */
 474                         if (ASIC_IS_DCE4(rdev))
 475                                 return ATOM_ENCODER_MODE_DVI;
 476                         else
 477                                 return ATOM_ENCODER_MODE_HDMI;
 478                 } else
 479                         return ATOM_ENCODER_MODE_DVI;
 480                 break;
 481         case DRM_MODE_CONNECTOR_eDP:
 482                 return ATOM_ENCODER_MODE_DP;
 483         case DRM_MODE_CONNECTOR_DVIA:
 484         case DRM_MODE_CONNECTOR_VGA:
 485                 return ATOM_ENCODER_MODE_CRT;
 486                 break;
 487         case DRM_MODE_CONNECTOR_Composite:
 488         case DRM_MODE_CONNECTOR_SVIDEO:
 489         case DRM_MODE_CONNECTOR_9PinDIN:
 490                 /* fix me */
 491                 return ATOM_ENCODER_MODE_TV;
 492                 /*return ATOM_ENCODER_MODE_CV;*/
 493                 break;
 494         }
 495 }
 496
 497 /*
 498  * DIG Encoder/Transmitter Setup
 499  *
 500  * DCE 3.0/3.1
 501  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
 502  * Supports up to 3 digital outputs
 503  * - 2 DIG encoder blocks.
 504  * DIG1 can drive UNIPHY link A or link B
 505  * DIG2 can drive UNIPHY link B or LVTMA
 506  *
 507  * DCE 3.2
 508  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
 509  * Supports up to 5 digital outputs
 510  * - 2 DIG encoder blocks.
 511  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 512  *
 513  * DCE 4.0/5.0
 514  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 515  * Supports up to 6 digital outputs
 516  * - 6 DIG encoder blocks.
 517  * - DIG to PHY mapping is hardcoded
 518  * DIG1 drives UNIPHY0 link A, A+B
 519  * DIG2 drives UNIPHY0 link B
 520  * DIG3 drives UNIPHY1 link A, A+B
 521  * DIG4 drives UNIPHY1 link B
 522  * DIG5 drives UNIPHY2 link A, A+B
 523  * DIG6 drives UNIPHY2 link B
 524  *
 525  * DCE 4.1
 526  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 527  * Supports up to 6 digital outputs
 528  * - 2 DIG encoder blocks.
 529  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 530  *
 531  * Routing
 532  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
 533  * Examples:
 534  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
 535  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
 536  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
 537  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
 538  */
 539
 540 union dig_encoder_control {
 541         DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
 542         DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
 543         DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
 544         DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
 545 };
 546
 547 void
 548 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
 549 {
 550         struct drm_device *dev = encoder->dev;
 551         struct radeon_device *rdev = dev->dev_private;
 552         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 553         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 554         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 555         union dig_encoder_control args;
 556         int index = 0;
 557         uint8_t frev, crev;
 558         int dp_clock = 0;
 559         int dp_lane_count = 0;
 560         int hpd_id = RADEON_HPD_NONE;
 561         int bpc = 8;
 562
 563         if (connector) {
 564                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 565                 struct radeon_connector_atom_dig *dig_connector =
 566                         radeon_connector->con_priv;
 567
 568                 dp_clock = dig_connector->dp_clock;
 569                 dp_lane_count = dig_connector->dp_lane_count;
 570                 hpd_id = radeon_connector->hpd.hpd;
 571                 bpc = connector->display_info.bpc;
 572         }
 573
 574         /* no dig encoder assigned */
 575         if (dig->dig_encoder == -1)
 576                 return;
 577
 578         memset(&args, 0, sizeof(args));
 579
 580         if (ASIC_IS_DCE4(rdev))
 581                 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
 582         else {
 583                 if (dig->dig_encoder)
 584                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 585                 else
 586                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 587         }
 588
 589         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 590                 return;
 591
 592         switch (frev) {
 593         case 1:
 594                 switch (crev) {
 595                 case 1:
 596                         args.v1.ucAction = action;
 597                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 598                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 599                                 args.v3.ucPanelMode = panel_mode;
 600                         else
 601                                 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
 602
 603                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
 604                                 args.v1.ucLaneNum = dp_lane_count;
 605                         else if (radeon_encoder->pixel_clock > 165000)
 606                                 args.v1.ucLaneNum = 8;
 607                         else
 608                                 args.v1.ucLaneNum = 4;
 609
 610                         switch (radeon_encoder->encoder_id) {
 611                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 612                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 613                                 break;
 614                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 615                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 616                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 617                                 break;
 618                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 619                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 620                                 break;
 621                         }
 622                         if (dig->linkb)
 623                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 624                         else
 625                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 626
 627                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
 628                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
 629
 630                         break;
 631                 case 2:
 632                 case 3:
 633                         args.v3.ucAction = action;
 634                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 635                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 636                                 args.v3.ucPanelMode = panel_mode;
 637                         else
 638                                 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
 639
 640                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
 641                                 args.v3.ucLaneNum = dp_lane_count;
 642                         else if (radeon_encoder->pixel_clock > 165000)
 643                                 args.v3.ucLaneNum = 8;
 644                         else
 645                                 args.v3.ucLaneNum = 4;
 646
 647                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
 648                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
 649                         args.v3.acConfig.ucDigSel = dig->dig_encoder;
 650                         switch (bpc) {
 651                         case 0:
 652                                 args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE;
 653                                 break;
 654                         case 6:
 655                                 args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR;
 656                                 break;
 657                         case 8:
 658                         default:
 659                                 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
 660                                 break;
 661                         case 10:
 662                                 args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR;
 663                                 break;
 664                         case 12:
 665                                 args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR;
 666                                 break;
 667                         case 16:
 668                                 args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR;
 669                                 break;
 670                         }
 671                         break;
 672                 case 4:
 673                         args.v4.ucAction = action;
 674                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 675                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 676                                 args.v4.ucPanelMode = panel_mode;
 677                         else
 678                                 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
 679
 680                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
 681                                 args.v4.ucLaneNum = dp_lane_count;
 682                         else if (radeon_encoder->pixel_clock > 165000)
 683                                 args.v4.ucLaneNum = 8;
 684                         else
 685                                 args.v4.ucLaneNum = 4;
 686
 687                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) {
 688                                 if (dp_clock == 270000)
 689                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
 690                                 else if (dp_clock == 540000)
 691                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
 692                         }
 693                         args.v4.acConfig.ucDigSel = dig->dig_encoder;
 694                         switch (bpc) {
 695                         case 0:
 696                                 args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE;
 697                                 break;
 698                         case 6:
 699                                 args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR;
 700                                 break;
 701                         case 8:
 702                         default:
 703                                 args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
 704                                 break;
 705                         case 10:
 706                                 args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR;
 707                                 break;
 708                         case 12:
 709                                 args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR;
 710                                 break;
 711                         case 16:
 712                                 args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR;
 713                                 break;
 714                         }
 715                         if (hpd_id == RADEON_HPD_NONE)
 716                                 args.v4.ucHPD_ID = 0;
 717                         else
 718                                 args.v4.ucHPD_ID = hpd_id + 1;
 719                         break;
 720                 default:
 721                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 722                         break;
 723                 }
 724                 break;
 725         default:
 726                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 727                 break;
 728         }
 729
 730         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 731
 732 }
 733
 734 union dig_transmitter_control {
 735         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
 736         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
 737         DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
 738         DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
 739 };
 740
 741 void
 742 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
 743 {
 744         struct drm_device *dev = encoder->dev;
 745         struct radeon_device *rdev = dev->dev_private;
 746         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 747         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 748         struct drm_connector *connector;
 749         union dig_transmitter_control args;
 750         int index = 0;
 751         uint8_t frev, crev;
 752         bool is_dp = false;
 753         int pll_id = 0;
 754         int dp_clock = 0;
 755         int dp_lane_count = 0;
 756         int connector_object_id = 0;
 757         int igp_lane_info = 0;
 758         int dig_encoder = dig->dig_encoder;
 759
 760         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 761                 connector = radeon_get_connector_for_encoder_init(encoder);
 762                 /* just needed to avoid bailing in the encoder check.  the encoder
 763                  * isn't used for init
 764                  */
 765                 dig_encoder = 0;
 766         } else
 767                 connector = radeon_get_connector_for_encoder(encoder);
 768
 769         if (connector) {
 770                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 771                 struct radeon_connector_atom_dig *dig_connector =
 772                         radeon_connector->con_priv;
 773
 774                 dp_clock = dig_connector->dp_clock;
 775                 dp_lane_count = dig_connector->dp_lane_count;
 776                 connector_object_id =
 777                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 778                 igp_lane_info = dig_connector->igp_lane_info;
 779         }
 780
 781         if (encoder->crtc) {
 782                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 783                 pll_id = radeon_crtc->pll_id;
 784         }
 785
 786         /* no dig encoder assigned */
 787         if (dig_encoder == -1)
 788                 return;
 789
 790         if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
 791                 is_dp = true;
 792
 793         memset(&args, 0, sizeof(args));
 794
 795         switch (radeon_encoder->encoder_id) {
 796         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 797                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
 798                 break;
 799         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 800         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 801         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 802                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
 803                 break;
 804         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 805                 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
 806                 break;
 807         }
 808
 809         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 810                 return;
 811
 812         switch (frev) {
 813         case 1:
 814                 switch (crev) {
 815                 case 1:
 816                         args.v1.ucAction = action;
 817                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 818                                 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
 819                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
 820                                 args.v1.asMode.ucLaneSel = lane_num;
 821                                 args.v1.asMode.ucLaneSet = lane_set;
 822                         } else {
 823                                 if (is_dp)
 824                                         args.v1.usPixelClock =
 825                                                 cpu_to_le16(dp_clock / 10);
 826                                 else if (radeon_encoder->pixel_clock > 165000)
 827                                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
 828                                 else
 829                                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 830                         }
 831
 832                         args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
 833
 834                         if (dig_encoder)
 835                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
 836                         else
 837                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
 838
 839                         if ((rdev->flags & RADEON_IS_IGP) &&
 840                             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
 841                                 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
 842                                         if (igp_lane_info & 0x1)
 843                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
 844                                         else if (igp_lane_info & 0x2)
 845                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
 846                                         else if (igp_lane_info & 0x4)
 847                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
 848                                         else if (igp_lane_info & 0x8)
 849                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
 850                                 } else {
 851                                         if (igp_lane_info & 0x3)
 852                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
 853                                         else if (igp_lane_info & 0xc)
 854                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
 855                                 }
 856                         }
 857
 858                         if (dig->linkb)
 859                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
 860                         else
 861                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
 862
 863                         if (is_dp)
 864                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 865                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 866                                 if (dig->coherent_mode)
 867                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 868                                 if (radeon_encoder->pixel_clock > 165000)
 869                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
 870                         }
 871                         break;
 872                 case 2:
 873                         args.v2.ucAction = action;
 874                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 875                                 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
 876                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
 877                                 args.v2.asMode.ucLaneSel = lane_num;
 878                                 args.v2.asMode.ucLaneSet = lane_set;
 879                         } else {
 880                                 if (is_dp)
 881                                         args.v2.usPixelClock =
 882                                                 cpu_to_le16(dp_clock / 10);
 883                                 else if (radeon_encoder->pixel_clock > 165000)
 884                                         args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
 885                                 else
 886                                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 887                         }
 888
 889                         args.v2.acConfig.ucEncoderSel = dig_encoder;
 890                         if (dig->linkb)
 891                                 args.v2.acConfig.ucLinkSel = 1;
 892
 893                         switch (radeon_encoder->encoder_id) {
 894                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 895                                 args.v2.acConfig.ucTransmitterSel = 0;
 896                                 break;
 897                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 898                                 args.v2.acConfig.ucTransmitterSel = 1;
 899                                 break;
 900                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 901                                 args.v2.acConfig.ucTransmitterSel = 2;
 902                                 break;
 903                         }
 904
 905                         if (is_dp) {
 906                                 args.v2.acConfig.fCoherentMode = 1;
 907                                 args.v2.acConfig.fDPConnector = 1;
 908                         } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 909                                 if (dig->coherent_mode)
 910                                         args.v2.acConfig.fCoherentMode = 1;
 911                                 if (radeon_encoder->pixel_clock > 165000)
 912                                         args.v2.acConfig.fDualLinkConnector = 1;
 913                         }
 914                         break;
 915                 case 3:
 916                         args.v3.ucAction = action;
 917                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 918                                 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
 919                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
 920                                 args.v3.asMode.ucLaneSel = lane_num;
 921                                 args.v3.asMode.ucLaneSet = lane_set;
 922                         } else {
 923                                 if (is_dp)
 924                                         args.v3.usPixelClock =
 925                                                 cpu_to_le16(dp_clock / 10);
 926                                 else if (radeon_encoder->pixel_clock > 165000)
 927                                         args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
 928                                 else
 929                                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 930                         }
 931
 932                         if (is_dp)
 933                                 args.v3.ucLaneNum = dp_lane_count;
 934                         else if (radeon_encoder->pixel_clock > 165000)
 935                                 args.v3.ucLaneNum = 8;
 936                         else
 937                                 args.v3.ucLaneNum = 4;
 938
 939                         if (dig->linkb)
 940                                 args.v3.acConfig.ucLinkSel = 1;
 941                         if (dig_encoder & 1)
 942                                 args.v3.acConfig.ucEncoderSel = 1;
 943
 944                         /* Select the PLL for the PHY
 945                          * DP PHY should be clocked from external src if there is
 946                          * one.
 947                          */
 948                         /* On DCE4, if there is an external clock, it generates the DP ref clock */
 949                         if (is_dp && rdev->clock.dp_extclk)
 950                                 args.v3.acConfig.ucRefClkSource = 2; /* external src */
 951                         else
 952                                 args.v3.acConfig.ucRefClkSource = pll_id;
 953
 954                         switch (radeon_encoder->encoder_id) {
 955                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 956                                 args.v3.acConfig.ucTransmitterSel = 0;
 957                                 break;
 958                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 959                                 args.v3.acConfig.ucTransmitterSel = 1;
 960                                 break;
 961                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 962                                 args.v3.acConfig.ucTransmitterSel = 2;
 963                                 break;
 964                         }
 965
 966                         if (is_dp)
 967                                 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
 968                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 969                                 if (dig->coherent_mode)
 970                                         args.v3.acConfig.fCoherentMode = 1;
 971                                 if (radeon_encoder->pixel_clock > 165000)
 972                                         args.v3.acConfig.fDualLinkConnector = 1;
 973                         }
 974                         break;
 975                 case 4:
 976                         args.v4.ucAction = action;
 977                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 978                                 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
 979                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
 980                                 args.v4.asMode.ucLaneSel = lane_num;
 981                                 args.v4.asMode.ucLaneSet = lane_set;
 982                         } else {
 983                                 if (is_dp)
 984                                         args.v4.usPixelClock =
 985                                                 cpu_to_le16(dp_clock / 10);
 986                                 else if (radeon_encoder->pixel_clock > 165000)
 987                                         args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
 988                                 else
 989                                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 990                         }
 991
 992                         if (is_dp)
 993                                 args.v4.ucLaneNum = dp_lane_count;
 994                         else if (radeon_encoder->pixel_clock > 165000)
 995                                 args.v4.ucLaneNum = 8;
 996                         else
 997                                 args.v4.ucLaneNum = 4;
 998
 999                         if (dig->linkb)
1000                                 args.v4.acConfig.ucLinkSel = 1;
1001                         if (dig_encoder & 1)
1002                                 args.v4.acConfig.ucEncoderSel = 1;
1003
1004                         /* Select the PLL for the PHY
1005                          * DP PHY should be clocked from external src if there is
1006                          * one.
1007                          */
1008                         /* On DCE5 DCPLL usually generates the DP ref clock */
1009                         if (is_dp) {
1010                                 if (rdev->clock.dp_extclk)
1011                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1012                                 else
1013                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1014                         } else
1015                                 args.v4.acConfig.ucRefClkSource = pll_id;
1016
1017                         switch (radeon_encoder->encoder_id) {
1018                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1019                                 args.v4.acConfig.ucTransmitterSel = 0;
1020                                 break;
1021                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1022                                 args.v4.acConfig.ucTransmitterSel = 1;
1023                                 break;
1024                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1025                                 args.v4.acConfig.ucTransmitterSel = 2;
1026                                 break;
1027                         }
1028
1029                         if (is_dp)
1030                                 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1031                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1032                                 if (dig->coherent_mode)
1033                                         args.v4.acConfig.fCoherentMode = 1;
1034                                 if (radeon_encoder->pixel_clock > 165000)
1035                                         args.v4.acConfig.fDualLinkConnector = 1;
1036                         }
1037                         break;
1038                 default:
1039                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1040                         break;
1041                 }
1042                 break;
1043         default:
1044                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1045                 break;
1046         }
1047
1048         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1049 }
1050
1051 bool
1052 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1053 {
1054         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1055         struct drm_device *dev = radeon_connector->base.dev;
1056         struct radeon_device *rdev = dev->dev_private;
1057         union dig_transmitter_control args;
1058         int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1059         uint8_t frev, crev;
1060
1061         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1062                 goto done;
1063
1064         if (!ASIC_IS_DCE4(rdev))
1065                 goto done;
1066
1067         if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1068             (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1069                 goto done;
1070
1071         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1072                 goto done;
1073
1074         memset(&args, 0, sizeof(args));
1075
1076         args.v1.ucAction = action;
1077
1078         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1079
1080         /* wait for the panel to power up */
1081         if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1082                 int i;
1083
1084                 for (i = 0; i < 300; i++) {
1085                         if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1086                                 return true;
1087                         mdelay(1);
1088                 }
1089                 return false;
1090         }
1091 done:
1092         return true;
1093 }
1094
1095 union external_encoder_control {
1096         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1097         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1098 };
1099
1100 static void
1101 atombios_external_encoder_setup(struct drm_encoder *encoder,
1102                                 struct drm_encoder *ext_encoder,
1103                                 int action)
1104 {
1105         struct drm_device *dev = encoder->dev;
1106         struct radeon_device *rdev = dev->dev_private;
1107         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1108         struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1109         union external_encoder_control args;
1110         struct drm_connector *connector;
1111         int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1112         u8 frev, crev;
1113         int dp_clock = 0;
1114         int dp_lane_count = 0;
1115         int connector_object_id = 0;
1116         u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1117         int bpc = 8;
1118
1119         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1120                 connector = radeon_get_connector_for_encoder_init(encoder);
1121         else
1122                 connector = radeon_get_connector_for_encoder(encoder);
1123
1124         if (connector) {
1125                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1126                 struct radeon_connector_atom_dig *dig_connector =
1127                         radeon_connector->con_priv;
1128
1129                 dp_clock = dig_connector->dp_clock;
1130                 dp_lane_count = dig_connector->dp_lane_count;
1131                 connector_object_id =
1132                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1133                 bpc = connector->display_info.bpc;
1134         }
1135
1136         memset(&args, 0, sizeof(args));
1137
1138         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1139                 return;
1140
1141         switch (frev) {
1142         case 1:
1143                 /* no params on frev 1 */
1144                 break;
1145         case 2:
1146                 switch (crev) {
1147                 case 1:
1148                 case 2:
1149                         args.v1.sDigEncoder.ucAction = action;
1150                         args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1151                         args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1152
1153                         if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1154                                 if (dp_clock == 270000)
1155                                         args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1156                                 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1157                         } else if (radeon_encoder->pixel_clock > 165000)
1158                                 args.v1.sDigEncoder.ucLaneNum = 8;
1159                         else
1160                                 args.v1.sDigEncoder.ucLaneNum = 4;
1161                         break;
1162                 case 3:
1163                         args.v3.sExtEncoder.ucAction = action;
1164                         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1165                                 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1166                         else
1167                                 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1168                         args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1169
1170                         if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1171                                 if (dp_clock == 270000)
1172                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1173                                 else if (dp_clock == 540000)
1174                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1175                                 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1176                         } else if (radeon_encoder->pixel_clock > 165000)
1177                                 args.v3.sExtEncoder.ucLaneNum = 8;
1178                         else
1179                                 args.v3.sExtEncoder.ucLaneNum = 4;
1180                         switch (ext_enum) {
1181                         case GRAPH_OBJECT_ENUM_ID1:
1182                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1183                                 break;
1184                         case GRAPH_OBJECT_ENUM_ID2:
1185                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1186                                 break;
1187                         case GRAPH_OBJECT_ENUM_ID3:
1188                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1189                                 break;
1190                         }
1191                         switch (bpc) {
1192                         case 0:
1193                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE;
1194                                 break;
1195                         case 6:
1196                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR;
1197                                 break;
1198                         case 8:
1199                         default:
1200                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;
1201                                 break;
1202                         case 10:
1203                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR;
1204                                 break;
1205                         case 12:
1206                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR;
1207                                 break;
1208                         case 16:
1209                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR;
1210                                 break;
1211                         }
1212                         break;
1213                 default:
1214                         DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1215                         return;
1216                 }
1217                 break;
1218         default:
1219                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1220                 return;
1221         }
1222         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1223 }
1224
1225 static void
1226 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1227 {
1228         struct drm_device *dev = encoder->dev;
1229         struct radeon_device *rdev = dev->dev_private;
1230         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1231         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1232         ENABLE_YUV_PS_ALLOCATION args;
1233         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1234         uint32_t temp, reg;
1235
1236         memset(&args, 0, sizeof(args));
1237
1238         if (rdev->family >= CHIP_R600)
1239                 reg = R600_BIOS_3_SCRATCH;
1240         else
1241                 reg = RADEON_BIOS_3_SCRATCH;
1242
1243         /* XXX: fix up scratch reg handling */
1244         temp = RREG32(reg);
1245         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1246                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1247                              (radeon_crtc->crtc_id << 18)));
1248         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1249                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1250         else
1251                 WREG32(reg, 0);
1252
1253         if (enable)
1254                 args.ucEnable = ATOM_ENABLE;
1255         args.ucCRTC = radeon_crtc->crtc_id;
1256
1257         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1258
1259         WREG32(reg, temp);
1260 }
1261
1262 static void
1263 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1264 {
1265         struct drm_device *dev = encoder->dev;
1266         struct radeon_device *rdev = dev->dev_private;
1267         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1268         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1269         int index = 0;
1270
1271         memset(&args, 0, sizeof(args));
1272
1273         switch (radeon_encoder->encoder_id) {
1274         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1275         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1276                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1277                 break;
1278         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1279         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1280         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1281                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1282                 break;
1283         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1284                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1285                 break;
1286         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1287                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1288                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1289                 else
1290                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1291                 break;
1292         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1293         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1294                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1295                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1296                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1297                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1298                 else
1299                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1300                 break;
1301         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1302         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1303                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1304                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1305                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1306                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1307                 else
1308                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1309                 break;
1310         default:
1311                 return;
1312         }
1313
1314         switch (mode) {
1315         case DRM_MODE_DPMS_ON:
1316                 args.ucAction = ATOM_ENABLE;
1317                 /* workaround for DVOOutputControl on some RS690 systems */
1318                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1319                         u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1320                         WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1321                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1322                         WREG32(RADEON_BIOS_3_SCRATCH, reg);
1323                 } else
1324                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1325                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1326                         args.ucAction = ATOM_LCD_BLON;
1327                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1328                 }
1329                 break;
1330         case DRM_MODE_DPMS_STANDBY:
1331         case DRM_MODE_DPMS_SUSPEND:
1332         case DRM_MODE_DPMS_OFF:
1333                 args.ucAction = ATOM_DISABLE;
1334                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1335                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1336                         args.ucAction = ATOM_LCD_BLOFF;
1337                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1338                 }
1339                 break;
1340         }
1341 }
1342
1343 static void
1344 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1345 {
1346         struct drm_device *dev = encoder->dev;
1347         struct radeon_device *rdev = dev->dev_private;
1348         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1349         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1350         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1351         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1352         struct radeon_connector *radeon_connector = NULL;
1353         struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1354
1355         if (connector) {
1356                 radeon_connector = to_radeon_connector(connector);
1357                 radeon_dig_connector = radeon_connector->con_priv;
1358         }
1359
1360         switch (mode) {
1361         case DRM_MODE_DPMS_ON:
1362                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1363                         if (!connector)
1364                                 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1365                         else
1366                                 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1367
1368                         /* setup and enable the encoder */
1369                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1370                         atombios_dig_encoder_setup(encoder,
1371                                                    ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1372                                                    dig->panel_mode);
1373                         if (ext_encoder) {
1374                                 if (ASIC_IS_DCE41(rdev))
1375                                         atombios_external_encoder_setup(encoder, ext_encoder,
1376                                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1377                         }
1378                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1379                 } else if (ASIC_IS_DCE4(rdev)) {
1380                         /* setup and enable the encoder */
1381                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1382                         /* enable the transmitter */
1383                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1384                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1385                 } else {
1386                         /* setup and enable the encoder and transmitter */
1387                         atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1388                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1389                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1390                         /* some dce3.x boards have a bug in their transmitter control table.
1391                          * ACTION_ENABLE_OUTPUT can probably be dropped since ACTION_ENABLE
1392                          * does the same thing and more.
1393                          */
1394                         if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730) &&
1395                             (rdev->family != CHIP_RS780) && (rdev->family != CHIP_RS880))
1396                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1397                 }
1398                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1399                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1400                                 atombios_set_edp_panel_power(connector,
1401                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
1402                                 radeon_dig_connector->edp_on = true;
1403                         }
1404                         radeon_dp_link_train(encoder, connector);
1405                         if (ASIC_IS_DCE4(rdev))
1406                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1407                 }
1408                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1409                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1410                 break;
1411         case DRM_MODE_DPMS_STANDBY:
1412         case DRM_MODE_DPMS_SUSPEND:
1413         case DRM_MODE_DPMS_OFF:
1414                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1415                         /* disable the transmitter */
1416                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1417                 } else if (ASIC_IS_DCE4(rdev)) {
1418                         /* disable the transmitter */
1419                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1420                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1421                 } else {
1422                         /* disable the encoder and transmitter */
1423                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1424                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1425                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1426                 }
1427                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1428                         if (ASIC_IS_DCE4(rdev))
1429                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1430                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1431                                 atombios_set_edp_panel_power(connector,
1432                                                              ATOM_TRANSMITTER_ACTION_POWER_OFF);
1433                                 radeon_dig_connector->edp_on = false;
1434                         }
1435                 }
1436                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1437                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1438                 break;
1439         }
1440 }
1441
1442 static void
1443 radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1444                              struct drm_encoder *ext_encoder,
1445                              int mode)
1446 {
1447         struct drm_device *dev = encoder->dev;
1448         struct radeon_device *rdev = dev->dev_private;
1449
1450         switch (mode) {
1451         case DRM_MODE_DPMS_ON:
1452         default:
1453                 if (ASIC_IS_DCE41(rdev)) {
1454                         atombios_external_encoder_setup(encoder, ext_encoder,
1455                                                         EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1456                         atombios_external_encoder_setup(encoder, ext_encoder,
1457                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1458                 } else
1459                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1460                 break;
1461         case DRM_MODE_DPMS_STANDBY:
1462         case DRM_MODE_DPMS_SUSPEND:
1463         case DRM_MODE_DPMS_OFF:
1464                 if (ASIC_IS_DCE41(rdev)) {
1465                         atombios_external_encoder_setup(encoder, ext_encoder,
1466                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1467                         atombios_external_encoder_setup(encoder, ext_encoder,
1468                                                         EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1469                 } else
1470                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1471                 break;
1472         }
1473 }
1474
1475 static void
1476 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1477 {
1478         struct drm_device *dev = encoder->dev;
1479         struct radeon_device *rdev = dev->dev_private;
1480         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1481         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1482
1483         DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1484                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1485                   radeon_encoder->active_device);
1486         switch (radeon_encoder->encoder_id) {
1487         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1488         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1489         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1490         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1491         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1492         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1493         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1494         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1495                 radeon_atom_encoder_dpms_avivo(encoder, mode);
1496                 break;
1497         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1498         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1499         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1500         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1501                 radeon_atom_encoder_dpms_dig(encoder, mode);
1502                 break;
1503         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1504                 if (ASIC_IS_DCE5(rdev)) {
1505                         switch (mode) {
1506                         case DRM_MODE_DPMS_ON:
1507                                 atombios_dvo_setup(encoder, ATOM_ENABLE);
1508                                 break;
1509                         case DRM_MODE_DPMS_STANDBY:
1510                         case DRM_MODE_DPMS_SUSPEND:
1511                         case DRM_MODE_DPMS_OFF:
1512                                 atombios_dvo_setup(encoder, ATOM_DISABLE);
1513                                 break;
1514                         }
1515                 } else if (ASIC_IS_DCE3(rdev))
1516                         radeon_atom_encoder_dpms_dig(encoder, mode);
1517                 else
1518                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1519                 break;
1520         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1521         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1522                 if (ASIC_IS_DCE5(rdev)) {
1523                         switch (mode) {
1524                         case DRM_MODE_DPMS_ON:
1525                                 atombios_dac_setup(encoder, ATOM_ENABLE);
1526                                 break;
1527                         case DRM_MODE_DPMS_STANDBY:
1528                         case DRM_MODE_DPMS_SUSPEND:
1529                         case DRM_MODE_DPMS_OFF:
1530                                 atombios_dac_setup(encoder, ATOM_DISABLE);
1531                                 break;
1532                         }
1533                 } else
1534                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1535                 break;
1536         default:
1537                 return;
1538         }
1539
1540         if (ext_encoder)
1541                 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1542
1543         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1544
1545 }
1546
1547 union crtc_source_param {
1548         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1549         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1550 };
1551
1552 static void
1553 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1554 {
1555         struct drm_device *dev = encoder->dev;
1556         struct radeon_device *rdev = dev->dev_private;
1557         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1558         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1559         union crtc_source_param args;
1560         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1561         uint8_t frev, crev;
1562         struct radeon_encoder_atom_dig *dig;
1563
1564         memset(&args, 0, sizeof(args));
1565
1566         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1567                 return;
1568
1569         switch (frev) {
1570         case 1:
1571                 switch (crev) {
1572                 case 1:
1573                 default:
1574                         if (ASIC_IS_AVIVO(rdev))
1575                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1576                         else {
1577                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1578                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1579                                 } else {
1580                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1581                                 }
1582                         }
1583                         switch (radeon_encoder->encoder_id) {
1584                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1585                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1586                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1587                                 break;
1588                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1589                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1590                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1591                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1592                                 else
1593                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1594                                 break;
1595                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1596                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1597                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1598                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1599                                 break;
1600                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1601                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1602                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1603                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1604                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1605                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1606                                 else
1607                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1608                                 break;
1609                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1610                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1611                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1612                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1613                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1614                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1615                                 else
1616                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1617                                 break;
1618                         }
1619                         break;
1620                 case 2:
1621                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1622                         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1623                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1624
1625                                 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1626                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1627                                 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1628                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1629                                 else
1630                                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1631                         } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1632                                 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1633                         } else {
1634                                 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1635                         }
1636                         switch (radeon_encoder->encoder_id) {
1637                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1638                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1639                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1640                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1641                                 dig = radeon_encoder->enc_priv;
1642                                 switch (dig->dig_encoder) {
1643                                 case 0:
1644                                         args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1645                                         break;
1646                                 case 1:
1647                                         args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1648                                         break;
1649                                 case 2:
1650                                         args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1651                                         break;
1652                                 case 3:
1653                                         args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1654                                         break;
1655                                 case 4:
1656                                         args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1657                                         break;
1658                                 case 5:
1659                                         args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1660                                         break;
1661                                 }
1662                                 break;
1663                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1664                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1665                                 break;
1666                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1667                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1668                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1669                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1670                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1671                                 else
1672                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1673                                 break;
1674                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1675                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1676                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1677                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1678                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1679                                 else
1680                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1681                                 break;
1682                         }
1683                         break;
1684                 }
1685                 break;
1686         default:
1687                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1688                 return;
1689         }
1690
1691         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1692
1693         /* update scratch regs with new routing */
1694         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1695 }
1696
1697 static void
1698 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1699                               struct drm_display_mode *mode)
1700 {
1701         struct drm_device *dev = encoder->dev;
1702         struct radeon_device *rdev = dev->dev_private;
1703         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1704         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1705
1706         /* Funky macbooks */
1707         if ((dev->pdev->device == 0x71C5) &&
1708             (dev->pdev->subsystem_vendor == 0x106b) &&
1709             (dev->pdev->subsystem_device == 0x0080)) {
1710                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1711                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1712
1713                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1714                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1715
1716                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1717                 }
1718         }
1719
1720         /* set scaler clears this on some chips */
1721         if (ASIC_IS_AVIVO(rdev) &&
1722             (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1723                 if (ASIC_IS_DCE4(rdev)) {
1724                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1725                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1726                                        EVERGREEN_INTERLEAVE_EN);
1727                         else
1728                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1729                 } else {
1730                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1731                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1732                                        AVIVO_D1MODE_INTERLEAVE_EN);
1733                         else
1734                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1735                 }
1736         }
1737 }
1738
1739 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1740 {
1741         struct drm_device *dev = encoder->dev;
1742         struct radeon_device *rdev = dev->dev_private;
1743         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1744         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1745         struct drm_encoder *test_encoder;
1746         struct radeon_encoder_atom_dig *dig;
1747         uint32_t dig_enc_in_use = 0;
1748
1749         /* DCE4/5 */
1750         if (ASIC_IS_DCE4(rdev)) {
1751                 dig = radeon_encoder->enc_priv;
1752                 if (ASIC_IS_DCE41(rdev)) {
1753                         /* ontario follows DCE4 */
1754                         if (rdev->family == CHIP_PALM) {
1755                                 if (dig->linkb)
1756                                         return 1;
1757                                 else
1758                                         return 0;
1759                         } else
1760                                 /* llano follows DCE3.2 */
1761                                 return radeon_crtc->crtc_id;
1762                 } else {
1763                         switch (radeon_encoder->encoder_id) {
1764                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1765                                 if (dig->linkb)
1766                                         return 1;
1767                                 else
1768                                         return 0;
1769                                 break;
1770                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1771                                 if (dig->linkb)
1772                                         return 3;
1773                                 else
1774                                         return 2;
1775                                 break;
1776                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1777                                 if (dig->linkb)
1778                                         return 5;
1779                                 else
1780                                         return 4;
1781                                 break;
1782                         }
1783                 }
1784         }
1785
1786         /* on DCE32 and encoder can driver any block so just crtc id */
1787         if (ASIC_IS_DCE32(rdev)) {
1788                 return radeon_crtc->crtc_id;
1789         }
1790
1791         /* on DCE3 - LVTMA can only be driven by DIGB */
1792         list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1793                 struct radeon_encoder *radeon_test_encoder;
1794
1795                 if (encoder == test_encoder)
1796                         continue;
1797
1798                 if (!radeon_encoder_is_digital(test_encoder))
1799                         continue;
1800
1801                 radeon_test_encoder = to_radeon_encoder(test_encoder);
1802                 dig = radeon_test_encoder->enc_priv;
1803
1804                 if (dig->dig_encoder >= 0)
1805                         dig_enc_in_use |= (1 << dig->dig_encoder);
1806         }
1807
1808         if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1809                 if (dig_enc_in_use & 0x2)
1810                         DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1811                 return 1;
1812         }
1813         if (!(dig_enc_in_use & 1))
1814                 return 0;
1815         return 1;
1816 }
1817
1818 /* This only needs to be called once at startup */
1819 void
1820 radeon_atom_encoder_init(struct radeon_device *rdev)
1821 {
1822         struct drm_device *dev = rdev->ddev;
1823         struct drm_encoder *encoder;
1824
1825         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1826                 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1827                 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1828
1829                 switch (radeon_encoder->encoder_id) {
1830                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1831                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1832                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1833                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1834                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1835                         break;
1836                 default:
1837                         break;
1838                 }
1839
1840                 if (ext_encoder && ASIC_IS_DCE41(rdev))
1841                         atombios_external_encoder_setup(encoder, ext_encoder,
1842                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
1843         }
1844 }
1845
1846 static void
1847 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1848                              struct drm_display_mode *mode,
1849                              struct drm_display_mode *adjusted_mode)
1850 {
1851         struct drm_device *dev = encoder->dev;
1852         struct radeon_device *rdev = dev->dev_private;
1853         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1854
1855         radeon_encoder->pixel_clock = adjusted_mode->clock;
1856
1857         /* need to call this here rather than in prepare() since we need some crtc info */
1858         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1859
1860         if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1861                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1862                         atombios_yuv_setup(encoder, true);
1863                 else
1864                         atombios_yuv_setup(encoder, false);
1865         }
1866
1867         switch (radeon_encoder->encoder_id) {
1868         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1869         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1870         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1871         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1872                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1873                 break;
1874         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1875         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1876         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1877         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1878                 /* handled in dpms */
1879                 break;
1880         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1881         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1882         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1883                 atombios_dvo_setup(encoder, ATOM_ENABLE);
1884                 break;
1885         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1886         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1887         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1888         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1889                 atombios_dac_setup(encoder, ATOM_ENABLE);
1890                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1891                         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1892                                 atombios_tv_setup(encoder, ATOM_ENABLE);
1893                         else
1894                                 atombios_tv_setup(encoder, ATOM_DISABLE);
1895                 }
1896                 break;
1897         }
1898
1899         atombios_apply_encoder_quirks(encoder, adjusted_mode);
1900
1901         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1902                 r600_hdmi_enable(encoder);
1903                 r600_hdmi_setmode(encoder, adjusted_mode);
1904         }
1905 }
1906
1907 static bool
1908 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1909 {
1910         struct drm_device *dev = encoder->dev;
1911         struct radeon_device *rdev = dev->dev_private;
1912         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1913         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1914
1915         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1916                                        ATOM_DEVICE_CV_SUPPORT |
1917                                        ATOM_DEVICE_CRT_SUPPORT)) {
1918                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1919                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1920                 uint8_t frev, crev;
1921
1922                 memset(&args, 0, sizeof(args));
1923
1924                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1925                         return false;
1926
1927                 args.sDacload.ucMisc = 0;
1928
1929                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1930                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1931                         args.sDacload.ucDacType = ATOM_DAC_A;
1932                 else
1933                         args.sDacload.ucDacType = ATOM_DAC_B;
1934
1935                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1936                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1937                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1938                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1939                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1940                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1941                         if (crev >= 3)
1942                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1943                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1944                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1945                         if (crev >= 3)
1946                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1947                 }
1948
1949                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1950
1951                 return true;
1952         } else
1953                 return false;
1954 }
1955
1956 static enum drm_connector_status
1957 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1958 {
1959         struct drm_device *dev = encoder->dev;
1960         struct radeon_device *rdev = dev->dev_private;
1961         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1962         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1963         uint32_t bios_0_scratch;
1964
1965         if (!atombios_dac_load_detect(encoder, connector)) {
1966                 DRM_DEBUG_KMS("detect returned false \n");
1967                 return connector_status_unknown;
1968         }
1969
1970         if (rdev->family >= CHIP_R600)
1971                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1972         else
1973                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1974
1975         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1976         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1977                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1978                         return connector_status_connected;
1979         }
1980         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1981                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1982                         return connector_status_connected;
1983         }
1984         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1985                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1986                         return connector_status_connected;
1987         }
1988         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1989                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1990                         return connector_status_connected; /* CTV */
1991                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1992                         return connector_status_connected; /* STV */
1993         }
1994         return connector_status_disconnected;
1995 }
1996
1997 static enum drm_connector_status
1998 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1999 {
2000         struct drm_device *dev = encoder->dev;
2001         struct radeon_device *rdev = dev->dev_private;
2002         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2003         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2004         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2005         u32 bios_0_scratch;
2006
2007         if (!ASIC_IS_DCE4(rdev))
2008                 return connector_status_unknown;
2009
2010         if (!ext_encoder)
2011                 return connector_status_unknown;
2012
2013         if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2014                 return connector_status_unknown;
2015
2016         /* load detect on the dp bridge */
2017         atombios_external_encoder_setup(encoder, ext_encoder,
2018                                         EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2019
2020         bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2021
2022         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2023         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2024                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2025                         return connector_status_connected;
2026         }
2027         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2028                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2029                         return connector_status_connected;
2030         }
2031         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2032                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2033                         return connector_status_connected;
2034         }
2035         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2036                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2037                         return connector_status_connected; /* CTV */
2038                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2039                         return connector_status_connected; /* STV */
2040         }
2041         return connector_status_disconnected;
2042 }
2043
2044 void
2045 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2046 {
2047         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2048
2049         if (ext_encoder)
2050                 /* ddc_setup on the dp bridge */
2051                 atombios_external_encoder_setup(encoder, ext_encoder,
2052                                                 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2053
2054 }
2055
2056 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2057 {
2058         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2059         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2060
2061         if ((radeon_encoder->active_device &
2062              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2063             (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2064              ENCODER_OBJECT_ID_NONE)) {
2065                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2066                 if (dig)
2067                         dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
2068         }
2069
2070         radeon_atom_output_lock(encoder, true);
2071
2072         if (connector) {
2073                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2074
2075                 /* select the clock/data port if it uses a router */
2076                 if (radeon_connector->router.cd_valid)
2077                         radeon_router_select_cd_port(radeon_connector);
2078
2079                 /* turn eDP panel on for mode set */
2080                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2081                         atombios_set_edp_panel_power(connector,
2082                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
2083         }
2084
2085         /* this is needed for the pll/ss setup to work correctly in some cases */
2086         atombios_set_encoder_crtc_source(encoder);
2087 }
2088
2089 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2090 {
2091         /* need to call this here as we need the crtc set up */
2092         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2093         radeon_atom_output_lock(encoder, false);
2094 }
2095
2096 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2097 {
2098         struct drm_device *dev = encoder->dev;
2099         struct radeon_device *rdev = dev->dev_private;
2100         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2101         struct radeon_encoder_atom_dig *dig;
2102
2103         /* check for pre-DCE3 cards with shared encoders;
2104          * can't really use the links individually, so don't disable
2105          * the encoder if it's in use by another connector
2106          */
2107         if (!ASIC_IS_DCE3(rdev)) {
2108                 struct drm_encoder *other_encoder;
2109                 struct radeon_encoder *other_radeon_encoder;
2110
2111                 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2112                         other_radeon_encoder = to_radeon_encoder(other_encoder);
2113                         if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2114                             drm_helper_encoder_in_use(other_encoder))
2115                                 goto disable_done;
2116                 }
2117         }
2118
2119         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2120
2121         switch (radeon_encoder->encoder_id) {
2122         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2123         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2124         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2125         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2126                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2127                 break;
2128         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2129         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2130         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2131         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2132                 /* handled in dpms */
2133                 break;
2134         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2135         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2136         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2137                 atombios_dvo_setup(encoder, ATOM_DISABLE);
2138                 break;
2139         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2140         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2141         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2142         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2143                 atombios_dac_setup(encoder, ATOM_DISABLE);
2144                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2145                         atombios_tv_setup(encoder, ATOM_DISABLE);
2146                 break;
2147         }
2148
2149 disable_done:
2150         if (radeon_encoder_is_digital(encoder)) {
2151                 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
2152                         r600_hdmi_disable(encoder);
2153                 dig = radeon_encoder->enc_priv;
2154                 dig->dig_encoder = -1;
2155         }
2156         radeon_encoder->active_device = 0;
2157 }
2158
2159 /* these are handled by the primary encoders */
2160 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2161 {
2162
2163 }
2164
2165 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2166 {
2167
2168 }
2169
2170 static void
2171 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2172                          struct drm_display_mode *mode,
2173                          struct drm_display_mode *adjusted_mode)
2174 {
2175
2176 }
2177
2178 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2179 {
2180
2181 }
2182
2183 static void
2184 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2185 {
2186
2187 }
2188
2189 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2190                                        struct drm_display_mode *mode,
2191                                        struct drm_display_mode *adjusted_mode)
2192 {
2193         return true;
2194 }
2195
2196 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2197         .dpms = radeon_atom_ext_dpms,
2198         .mode_fixup = radeon_atom_ext_mode_fixup,
2199         .prepare = radeon_atom_ext_prepare,
2200         .mode_set = radeon_atom_ext_mode_set,
2201         .commit = radeon_atom_ext_commit,
2202         .disable = radeon_atom_ext_disable,
2203         /* no detect for TMDS/LVDS yet */
2204 };
2205
2206 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2207         .dpms = radeon_atom_encoder_dpms,
2208         .mode_fixup = radeon_atom_mode_fixup,
2209         .prepare = radeon_atom_encoder_prepare,
2210         .mode_set = radeon_atom_encoder_mode_set,
2211         .commit = radeon_atom_encoder_commit,
2212         .disable = radeon_atom_encoder_disable,
2213         .detect = radeon_atom_dig_detect,
2214 };
2215
2216 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2217         .dpms = radeon_atom_encoder_dpms,
2218         .mode_fixup = radeon_atom_mode_fixup,
2219         .prepare = radeon_atom_encoder_prepare,
2220         .mode_set = radeon_atom_encoder_mode_set,
2221         .commit = radeon_atom_encoder_commit,
2222         .detect = radeon_atom_dac_detect,
2223 };
2224
2225 void radeon_enc_destroy(struct drm_encoder *encoder)
2226 {
2227         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2228         kfree(radeon_encoder->enc_priv);
2229         drm_encoder_cleanup(encoder);
2230         kfree(radeon_encoder);
2231 }
2232
2233 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2234         .destroy = radeon_enc_destroy,
2235 };
2236
2237 struct radeon_encoder_atom_dac *
2238 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2239 {
2240         struct drm_device *dev = radeon_encoder->base.dev;
2241         struct radeon_device *rdev = dev->dev_private;
2242         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2243
2244         if (!dac)
2245                 return NULL;
2246
2247         dac->tv_std = radeon_atombios_get_tv_info(rdev);
2248         return dac;
2249 }
2250
2251 struct radeon_encoder_atom_dig *
2252 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2253 {
2254         int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2255         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2256
2257         if (!dig)
2258                 return NULL;
2259
2260         /* coherent mode by default */
2261         dig->coherent_mode = true;
2262         dig->dig_encoder = -1;
2263
2264         if (encoder_enum == 2)
2265                 dig->linkb = true;
2266         else
2267                 dig->linkb = false;
2268
2269         return dig;
2270 }
2271
2272 void
2273 radeon_add_atom_encoder(struct drm_device *dev,
2274                         uint32_t encoder_enum,
2275                         uint32_t supported_device,
2276                         u16 caps)
2277 {
2278         struct radeon_device *rdev = dev->dev_private;
2279         struct drm_encoder *encoder;
2280         struct radeon_encoder *radeon_encoder;
2281
2282         /* see if we already added it */
2283         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2284                 radeon_encoder = to_radeon_encoder(encoder);
2285                 if (radeon_encoder->encoder_enum == encoder_enum) {
2286                         radeon_encoder->devices |= supported_device;
2287                         return;
2288                 }
2289
2290         }
2291
2292         /* add a new one */
2293         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2294         if (!radeon_encoder)
2295                 return;
2296
2297         encoder = &radeon_encoder->base;
2298         switch (rdev->num_crtc) {
2299         case 1:
2300                 encoder->possible_crtcs = 0x1;
2301                 break;
2302         case 2:
2303         default:
2304                 encoder->possible_crtcs = 0x3;
2305                 break;
2306         case 4:
2307                 encoder->possible_crtcs = 0xf;
2308                 break;
2309         case 6:
2310                 encoder->possible_crtcs = 0x3f;
2311                 break;
2312         }
2313
2314         radeon_encoder->enc_priv = NULL;
2315
2316         radeon_encoder->encoder_enum = encoder_enum;
2317         radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2318         radeon_encoder->devices = supported_device;
2319         radeon_encoder->rmx_type = RMX_OFF;
2320         radeon_encoder->underscan_type = UNDERSCAN_OFF;
2321         radeon_encoder->is_ext_encoder = false;
2322         radeon_encoder->caps = caps;
2323
2324         switch (radeon_encoder->encoder_id) {
2325         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2326         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2327         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2328         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2329                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2330                         radeon_encoder->rmx_type = RMX_FULL;
2331                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2332                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2333                 } else {
2334                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2335                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2336                 }
2337                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2338                 break;
2339         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2340                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2341                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2342                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2343                 break;
2344         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2345         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2346         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2347                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2348                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2349                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2350                 break;
2351         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2352         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2353         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2354         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2355         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2356         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2357         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2358                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2359                         radeon_encoder->rmx_type = RMX_FULL;
2360                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2361                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2362                 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2363                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2364                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2365                 } else {
2366                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2367                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2368                 }
2369                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2370                 break;
2371         case ENCODER_OBJECT_ID_SI170B:
2372         case ENCODER_OBJECT_ID_CH7303:
2373         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2374         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2375         case ENCODER_OBJECT_ID_TITFP513:
2376         case ENCODER_OBJECT_ID_VT1623:
2377         case ENCODER_OBJECT_ID_HDMI_SI1930:
2378         case ENCODER_OBJECT_ID_TRAVIS:
2379         case ENCODER_OBJECT_ID_NUTMEG:
2380                 /* these are handled by the primary encoders */
2381                 radeon_encoder->is_ext_encoder = true;
2382                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2383                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2384                 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2385                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2386                 else
2387                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2388                 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2389                 break;
2390         }
2391 }