/* Lock the mpu dpll */
sr32(CM_CLKMODE_DPLL_MPU, 0, 3, PLL_LOCK | 0x10);
wait_on_value(BIT0, 1, CM_IDLEST_DPLL_MPU, LDELAY);
-
- return;
}
static void configure_iva_dpll(u32 clk_index)
sr32(CM_CLKDCOLDO_DPLL_USB, 0, 32, 0x100);
}
-static void configure_core_dpll(clk_index)
+#if 0
+
+/* to remove warning about unused function; will be deleted in decruft patch */
+static void configure_core_dpll(int clk_index)
{
struct dpll_param *dpll_param_p;
sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_LOCK);
wait_on_value(BIT0, 1, CM_IDLEST_DPLL_CORE, LDELAY);
}
-
+#endif
void configure_core_dpll_no_lock(void)
{
- struct dpll_param *dpll_param_p;
+ struct dpll_param *dpll_param_p = NULL;
u32 clk_index;
/* Get the sysclk speed from cm_sys_clksel
case OMAP4430_ES2_1:
dpll_param_p = &core_dpll_param_ddr400[clk_index];
break;
+ default:
+ /* we are screwed */
+ break;
}
/* Disable autoidle */
void lock_core_dpll_shadow(void)
{
- struct dpll_param *dpll_param_p;
+ struct dpll_param *dpll_param_p = NULL;
/* Lock the core dpll using freq update method */
- *(volatile int*)0x4A004120 = 10; /* CM_CLKMODE_DPLL_CORE */
+ __raw_writel(10, 0x4A004120); /* CM_CLKMODE_DPLL_CORE */
switch (omap_revision()) {
case OMAP4430_ES1_0:
case OMAP4430_ES2_1:
dpll_param_p = &core_dpll_param_ddr400[6];
break;
+ default:
+ /* we are screwed */
+ break;
}
/* CM_SHADOW_FREQ_CONFIG1: DLL_OVERRIDE = 1(hack), DLL_RESET = 1,
* DPLL_CORE_M2_DIV =1, DPLL_CORE_DPLL_EN = 0x7, FREQ_UPDATE = 1
*/
- *(volatile int*)0x4A004260 = 0x70D | (dpll_param_p->m2 << 11);
+ __raw_writel(0x70D | (dpll_param_p->m2 << 11), 0x4A004260);
/* Wait for Freq_Update to get cleared: CM_SHADOW_FREQ_CONFIG1 */
- while (((*(volatile int*)0x4A004260) & 0x1) == 0x1)
+ while (__raw_readl(0x4A004260) & 1)
;
/* Wait for DPLL to Lock : CM_IDLEST_DPLL_CORE */
static void enable_all_clocks(void)
{
- volatile int regvalue = 0;
-
/* Enable Ducati clocks */
sr32(CM_DUCATI_DUCATI_CLKCTRL, 0, 32, 0x1);
sr32(CM_DUCATI_CLKSTCTRL, 0, 32, 0x2);
wait_on_value(BIT8, BIT8, CM_DUCATI_CLKSTCTRL, LDELAY);
- /*
- * wait_on_value(BIT18|BIT17|BIT16, 0, CM_DUCATI_DUCATI_CLKCTRL,
- * LDELAY);
- */
/* Enable ivahd and sl2 clocks */
sr32(IVAHD_IVAHD_CLKCTRL, 0, 32, 0x1);
wait_on_value(BIT8, BIT8, IVAHD_CLKSTCTRL, LDELAY);
- /* wait for ivahd to become accessible */
- /* wait_on_value(BIT18|BIT17|BIT16, 0, IVAHD_IVAHD_CLKCTRL, LDELAY); */
- /* wait for sl2 to become accessible */
- /* wait_on_value(BIT17|BIT16, 0, IVAHD_SL2_CLKCTRL, LDELAY); */
-
/* Enable Tesla clocks */
sr32(DSP_DSP_CLKCTRL, 0, 32, 0x1);
sr32(DSP_CLKSTCTRL, 0, 32, 0x2);
wait_on_value(BIT8, BIT8, DSP_CLKSTCTRL, LDELAY);
/* wait for tesla to become accessible */
- /* wait_on_value(BIT18|BIT17|BIT16, 0, DSP_DSP_CLKCTRL, LDELAY); */
-
- /* TODO: Some hack needed by MM: Clean this */
- #if 0 /* Doesn't work on some Zebu */
- *(volatile int *)0x4a306910 = 0x00000003;
- *(volatile int *)0x550809a0 = 0x00000001;
- *(volatile int *)0x55080a20 = 0x00000007;
- #endif
/* ABE clocks */
sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x3);
sr32(CM1_ABE_AESS_CLKCTRL, 0, 32, 0x2);
- /* wait_on_value(BIT18|BIT17|BIT16, 0, CM1_ABE_AESS_CLKCTRL, LDELAY); */
sr32(CM1_ABE_PDM_CLKCTRL, 0, 32, 0x2);
- /* wait_on_value(BIT17|BIT16, 0, CM1_ABE_PDM_CLKCTRL, LDELAY); */
sr32(CM1_ABE_DMIC_CLKCTRL, 0, 32, 0x2);
- /* wait_on_value(BIT17|BIT16, 0, CM1_ABE_DMIC_CLKCTRL, LDELAY); */
sr32(CM1_ABE_MCASP_CLKCTRL, 0, 32, 0x2);
- /* wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCASP_CLKCTRL, LDELAY); */
sr32(CM1_ABE_MCBSP1_CLKCTRL, 0, 32, 0x08000002);
- /* wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP1_CLKCTRL, LDELAY); */
sr32(CM1_ABE_MCBSP2_CLKCTRL, 0, 32, 0x08000002);
- /* wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP2_CLKCTRL, LDELAY); */
sr32(CM1_ABE_MCBSP3_CLKCTRL, 0, 32, 0x08000002);
- /* wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP3_CLKCTRL, LDELAY); */
sr32(CM1_ABE_SLIMBUS_CLKCTRL, 0, 32, 0xf02);
- /* wait_on_value(BIT17|BIT16, 0, CM1_ABE_SLIMBUS_CLKCTRL, LDELAY); */
sr32(CM1_ABE_TIMER5_CLKCTRL, 0, 32, 0x2);
- /* wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER5_CLKCTRL, LDELAY); */
sr32(CM1_ABE_TIMER6_CLKCTRL, 0, 32, 0x2);
- /* wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER6_CLKCTRL, LDELAY); */
sr32(CM1_ABE_TIMER7_CLKCTRL, 0, 32, 0x2);
- /* wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER7_CLKCTRL, LDELAY); */
sr32(CM1_ABE_TIMER8_CLKCTRL, 0, 32, 0x2);
- /* wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER8_CLKCTRL, LDELAY); */
sr32(CM1_ABE_WDT3_CLKCTRL, 0, 32, 0x2);
- /* wait_on_value(BIT17|BIT16, 0, CM1_ABE_WDT3_CLKCTRL, LDELAY); */
/* Disable sleep transitions */
sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x0);
/* MMC clocks */
sr32(CM_L3INIT_HSMMC1_CLKCTRL, 0, 2, 0x2);
sr32(CM_L3INIT_HSMMC1_CLKCTRL, 24, 1, 0x1);
- /*wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSMMC1_CLKCTRL,
- * LDELAY); */
sr32(CM_L3INIT_HSMMC2_CLKCTRL, 0, 2, 0x2);
sr32(CM_L3INIT_HSMMC2_CLKCTRL, 24, 1, 0x1);
- /*wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSMMC2_CLKCTRL,
- * LDELAY); */
sr32(CM_L4PER_MMCSD3_CLKCTRL, 0, 32, 0x2);
wait_on_value(BIT18|BIT17|BIT16, 0, CM_L4PER_MMCSD3_CLKCTRL, LDELAY);
sr32(CM_L4PER_MMCSD4_CLKCTRL, 0, 32, 0x2);
/* Enable Camera clocks */
sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x3);
sr32(CM_CAM_ISS_CLKCTRL, 0, 32, 0x102);
- /* wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_ISS_CLKCTRL, LDELAY); */
sr32(CM_CAM_FDIF_CLKCTRL, 0, 32, 0x2);
- /* wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_FDIF_CLKCTRL, LDELAY); */
sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x0);
/* Enable DSS clocks */
/* PM_DSS_PWRSTCTRL ON State and LogicState = 1 (Retention) */
- *(volatile int *)0x4A307100 = 0x7; /* DSS_PRM */
+ __raw_writel(7, 0x4A307100); /* DSS_PRM */
+
sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x2);
sr32(CM_DSS_DSS_CLKCTRL, 0, 32, 0xf02);
- /* wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DSS_CLKCTRL, LDELAY); */
sr32(CM_DSS_DEISS_CLKCTRL, 0, 32, 0x2);
- /* wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DEISS_CLKCTRL, LDELAY); */
/* Check for DSS Clocks */
- while (((*(volatile int *)0x4A009100) & 0xF00) != 0xE00)
+ while ((__raw_readl(0x4A009100) & 0xF00) != 0xE00)
;
/* Set HW_AUTO transition mode */
sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x3);
/* Enable SGX clocks */
sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x2);
sr32(CM_SGX_SGX_CLKCTRL, 0, 32, 0x2);
- /* wait_on_value(BIT18|BIT17|BIT16, 0, CM_SGX_SGX_CLKCTRL, LDELAY); */
/* Check for SGX FCLK and ICLK */
- while ((*(volatile int *)0x4A009200) != 0x302)
+ while (__raw_readl(0x4A009200) != 0x302)
;
- /* sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x0); */
/* Enable hsi/unipro/usb clocks */
sr32(CM_L3INIT_HSI_CLKCTRL, 0, 32, 0x1);
- /* wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSI_CLKCTRL,
- * LDELAY); */
sr32(CM_L3INIT_UNIPRO1_CLKCTRL, 0, 32, 0x2);
- /* wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_UNIPRO1_CLKCTRL,
- * LDELAY); */
sr32(CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, 0x2);
- /* wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBHOST_CLKCTRL,
- * LDELAY); */
sr32(CM_L3INIT_HSUSBOTG_CLKCTRL, 0, 32, 0x1);
- /* wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBOTG_CLKCTRL,
- * LDELAY); */
sr32(CM_L3INIT_HSUSBTLL_CLKCTRL, 0, 32, 0x1);
- /* wait_on_value(BIT17|BIT16, 0, CM_L3INIT_HSUSBTLL_CLKCTRL, LDELAY); */
sr32(CM_L3INIT_FSUSB_CLKCTRL, 0, 32, 0x2);
- /* wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_FSUSB_CLKCTRL,
- * LDELAY); */
/* enable the 32K, 48M optional clocks and enable the module */
sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x301);
- /* wait_on_value(BIT17|BIT16, 0, CM_L3INIT_USBPHY_CLKCTRL, LDELAY); */
}
/******************************************************************************