1 /**********************************************************************
3 * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful but, except
10 * as otherwise stated in writing, without any warranty; without even the
11 * implied warranty of merchantability or fitness for a particular purpose.
12 * See the GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * Imagination Technologies Ltd. <gpl-support@imgtec.com>
23 * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK
25 ******************************************************************************/
27 #ifndef __SGXINFOKM_H__
28 #define __SGXINFOKM_H__
30 #include <linux/workqueue.h>
33 #include "sysconfig.h"
34 #include "sgxscript.h"
38 #define SGX_HOSTPORT_PRESENT 0x00000001UL
40 #define PVRSRV_USSE_EDM_POWMAN_IDLE_COMPLETE (1UL << 2)
41 #define PVRSRV_USSE_EDM_POWMAN_POWEROFF_COMPLETE (1UL << 3)
42 #define PVRSRV_USSE_EDM_POWMAN_POWEROFF_RESTART_IMMEDIATE (1UL << 4)
43 #define PVRSRV_USSE_EDM_POWMAN_NO_WORK (1UL << 5)
45 #define PVRSRV_USSE_EDM_INTERRUPT_HWR (1UL << 0)
46 #define PVRSRV_USSE_EDM_INTERRUPT_ACTIVE_POWER (1UL << 1)
48 #define PVRSRV_USSE_EDM_RESMAN_CLEANUP_RT_REQUEST 0x01UL
49 #define PVRSRV_USSE_EDM_RESMAN_CLEANUP_RC_REQUEST 0x02UL
50 #define PVRSRV_USSE_EDM_RESMAN_CLEANUP_TC_REQUEST 0x04UL
51 #define PVRSRV_USSE_EDM_RESMAN_CLEANUP_2DC_REQUEST 0x08UL
52 #define PVRSRV_USSE_EDM_RESMAN_CLEANUP_SHAREDPBDESC 0x10UL
53 #define PVRSRV_USSE_EDM_RESMAN_CLEANUP_INVALPD 0x20UL
54 #define PVRSRV_USSE_EDM_RESMAN_CLEANUP_INVALPT 0x40UL
55 #define PVRSRV_USSE_EDM_RESMAN_CLEANUP_COMPLETE 0x80UL
57 #define PVRSRV_USSE_MISCINFO_READY 0x1UL
59 struct PVRSRV_SGX_CCB_INFO;
61 struct PVRSRV_SGXDEV_INFO {
62 enum PVRSRV_DEVICE_TYPE eDeviceType;
63 enum PVRSRV_DEVICE_CLASS eDeviceClass;
70 void __iomem *pvRegsBaseKM;
74 struct IMG_SYS_PHYADDR sRegsPhysBase;
78 u32 ui32CoreClockSpeed;
79 u32 ui32uKernelTimerClock;
81 void *psStubPBDescListKM;
83 struct IMG_DEV_PHYADDR sKernelPDDevPAddr;
85 void *pvDeviceMemoryHeap;
86 struct PVRSRV_KERNEL_MEM_INFO *psKernelCCBMemInfo;
87 struct PVRSRV_SGX_KERNEL_CCB *psKernelCCB;
88 struct PVRSRV_SGX_CCB_INFO *psKernelCCBInfo;
89 struct PVRSRV_KERNEL_MEM_INFO *psKernelCCBCtlMemInfo;
90 struct PVRSRV_SGX_CCB_CTL *psKernelCCBCtl;
91 struct PVRSRV_KERNEL_MEM_INFO *psKernelCCBEventKickerMemInfo;
92 u32 *pui32KernelCCBEventKicker;
93 struct PVRSRV_KERNEL_MEM_INFO *psKernelSGXMiscMemInfo;
94 u32 ui32HostKickAddress;
95 u32 ui32GetMiscInfoAddress;
96 u32 ui32KickTACounter;
97 u32 ui32KickTARenderCounter;
98 struct PVRSRV_KERNEL_MEM_INFO *psKernelHWPerfCBMemInfo;
99 struct PVRSRV_SGXDEV_DIFF_INFO sDiffInfo;
100 u32 ui32HWGroupRequested;
103 /*!< Meminfo for EDM status buffer */
104 struct PVRSRV_KERNEL_MEM_INFO *psKernelEDMStatusBufferMemInfo;
106 u32 ui32ClientRefCount;
108 u32 ui32CacheControl;
110 void *pvMMUContextList;
112 IMG_BOOL bForcePTOff;
117 u32 ui32ClkGateStatusReg;
118 u32 ui32ClkGateStatusMask;
119 struct SGX_INIT_SCRIPTS sScripts;
121 void *hBIFResetPDOSMemHandle;
122 struct IMG_DEV_PHYADDR sBIFResetPDDevPAddr;
123 struct IMG_DEV_PHYADDR sBIFResetPTDevPAddr;
124 struct IMG_DEV_PHYADDR sBIFResetPageDevPAddr;
125 u32 *pui32BIFResetPD;
126 u32 *pui32BIFResetPT;
132 unsigned long long last_idle;
133 unsigned long long burst_start;
136 int power_down_delay;
138 struct PVRSRV_KERNEL_MEM_INFO *psKernelSGXHostCtlMemInfo;
139 struct SGXMKIF_HOST_CTL __iomem *psSGXHostCtl;
141 struct PVRSRV_KERNEL_MEM_INFO *psKernelSGXTA3DCtlMemInfo;
146 struct PVRSRV_SGX_PDUMP_CONTEXT sPDContext;
150 u32 asSGXDevData[SGX_MAX_DEV_DATA];
155 struct SGX_TIMING_INFORMATION {
156 u32 ui32CoreClockSpeed;
157 u32 ui32HWRecoveryFreq;
158 u32 ui32ActivePowManLatencyms;
162 struct SGX_DEVICE_MAP {
165 struct IMG_SYS_PHYADDR sRegsSysPBase;
166 struct IMG_CPU_PHYADDR sRegsCpuPBase;
167 void __iomem *pvRegsCpuVBase;
170 struct IMG_SYS_PHYADDR sLocalMemSysPBase;
171 struct IMG_DEV_PHYADDR sLocalMemDevPBase;
172 struct IMG_CPU_PHYADDR sLocalMemCpuPBase;
173 u32 ui32LocalMemSize;
178 struct PVRSRV_STUB_PBDESC;
179 struct PVRSRV_STUB_PBDESC {
182 struct PVRSRV_KERNEL_MEM_INFO *psSharedPBDescKernelMemInfo;
183 struct PVRSRV_KERNEL_MEM_INFO *psHWPBDescKernelMemInfo;
184 struct PVRSRV_KERNEL_MEM_INFO **ppsSubKernelMemInfos;
185 u32 ui32SubKernelMemInfosCount;
187 struct PVRSRV_KERNEL_MEM_INFO *psBlockKernelMemInfo;
188 struct PVRSRV_STUB_PBDESC *psNext;
191 struct PVRSRV_SGX_CCB_INFO {
192 struct PVRSRV_KERNEL_MEM_INFO *psCCBMemInfo;
193 struct PVRSRV_KERNEL_MEM_INFO *psCCBCtlMemInfo;
194 struct SGXMKIF_COMMAND *psCommands;
195 u32 *pui32WriteOffset;
196 volatile u32 *pui32ReadOffset;
202 struct timer_work_data {
203 struct PVRSRV_DEVICE_NODE *psDeviceNode;
204 struct delayed_work work;
205 struct workqueue_struct *work_queue;
206 unsigned int interval;
210 enum PVRSRV_ERROR SGXRegisterDevice(struct PVRSRV_DEVICE_NODE *psDeviceNode);
211 enum PVRSRV_ERROR SGXOSTimerEnable(struct timer_work_data *data);
212 enum PVRSRV_ERROR SGXOSTimerCancel(struct timer_work_data *data);
213 struct timer_work_data *
214 SGXOSTimerInit(struct PVRSRV_DEVICE_NODE *psDeviceNode);
215 void SGXOSTimerDeInit(struct timer_work_data *data);
217 void HWRecoveryResetSGX(struct PVRSRV_DEVICE_NODE *psDeviceNode,
219 void SGXReset(struct PVRSRV_SGXDEV_INFO *psDevInfo, u32 ui32PDUMPFlags);
221 enum PVRSRV_ERROR SGXInitialise(struct PVRSRV_SGXDEV_INFO *psDevInfo,
222 IMG_BOOL bHardwareRecovery);
223 enum PVRSRV_ERROR SGXDeinitialise(void *hDevCookie);
225 void sgx_mark_new_command(struct PVRSRV_DEVICE_NODE *node);
226 void sgx_mark_power_down(struct PVRSRV_DEVICE_NODE *node);
228 void SGXStartTimer(struct PVRSRV_SGXDEV_INFO *psDevInfo,
229 IMG_BOOL bStartOSTimer);
231 enum PVRSRV_ERROR SGXPrePowerStateExt(void *hDevHandle,
232 enum PVR_POWER_STATE eNewPowerState,
233 enum PVR_POWER_STATE eCurrentPowerState);
235 enum PVRSRV_ERROR SGXPostPowerStateExt(void *hDevHandle,
236 enum PVR_POWER_STATE eNewPowerState,
237 enum PVR_POWER_STATE eCurrentPowerState);
239 enum PVRSRV_ERROR SGXPreClockSpeedChange(void *hDevHandle,
240 IMG_BOOL bIdleDevice,
244 enum PVRSRV_ERROR SGXPostClockSpeedChange(void *hDevHandle,
245 IMG_BOOL bIdleDevice,
249 enum PVRSRV_ERROR SGXDevInitCompatCheck(struct PVRSRV_DEVICE_NODE
252 void SysGetSGXTimingInformation(struct SGX_TIMING_INFORMATION *psSGXTimingInfo);
254 #if defined(NO_HARDWARE)
255 static inline void NoHardwareGenerateEvent(struct PVRSRV_SGXDEV_INFO *psDevInfo,
256 u32 ui32StatusRegister,
262 ui32RegVal = OSReadHWReg(psDevInfo->pvRegsBaseKM, ui32StatusRegister);
264 ui32RegVal &= ~ui32StatusMask;
265 ui32RegVal |= (ui32StatusValue & ui32StatusMask);
267 OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32StatusRegister, ui32RegVal);