remove unneeded code

clock lookups based on sys_clkin, IVA setup, repeated SoC detection,
some conditional code.

diff --git a/board/pandora/pandora.c b/board/pandora/pandora.c
index 040a783..3711155 100644 (file)
--- a/board/pandora/pandora.c
+++ b/board/pandora/pandora.c
@@ -41,27 +41,6 @@
 #include <fat.h>
 #include <i2c.h>
 
 #include <fat.h>
 #include <i2c.h>
 

-/* params for 37XX */
-#define CORE_DPLL_PARAM_M2     0x09
-#define CORE_DPLL_PARAM_M      0x360
-#define CORE_DPLL_PARAM_N      0xC
-
-/* Used to index into DPLL parameter tables */
-struct dpll_param {
-       unsigned int m;
-       unsigned int n;
-       unsigned int fsel;
-       unsigned int m2;
-};
-
-typedef struct dpll_param dpll_param;
-
-/* Following functions are exported from lowlevel_init.S */
-extern dpll_param *get_mpu_dpll_param(void);
-extern dpll_param *get_iva_dpll_param(void);
-extern dpll_param *get_core_dpll_param(void);
-extern dpll_param *get_per_dpll_param(void);
-

 #define __raw_readl(a)         (*(volatile unsigned int *)(a))
 #define __raw_writel(v, a)     (*(volatile unsigned int *)(a) = (v))
 #define __raw_readw(a)         (*(volatile unsigned short *)(a))
 #define __raw_readl(a)         (*(volatile unsigned int *)(a))
 #define __raw_writel(v, a)     (*(volatile unsigned int *)(a) = (v))
 #define __raw_readw(a)         (*(volatile unsigned short *)(a))


@@ -210,7 +189,7 @@ static int strncmp(const char *s1, const char *s2, int n)
 /*********************************************************************
  * config_sdram_ddr() - Init DDR SDRAM
  *********************************************************************/
 /*********************************************************************
  * config_sdram_ddr() - Init DDR SDRAM
  *********************************************************************/

-static void config_sdram_ddr(void)
+static void config_sdram_ddr(u32 cpu_family)

 {
        unsigned char buf[64];
        int ram_type = MICRON_128MB_166MHZ;
 {
        unsigned char buf[64];
        int ram_type = MICRON_128MB_166MHZ;


@@ -242,7 +221,7 @@ static void config_sdram_ddr(void)
                __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_1);
        }
 
                __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_1);
        }
 

-       if (get_cpu_family() == CPU_OMAP36XX && ram_type == MICRON_256MB_200MHZ) {
+       if (cpu_family == CPU_OMAP36XX && ram_type == MICRON_256MB_200MHZ) {

                __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_0);
                __raw_writel(MICRON_V_ACTIMB_200_2, SDRC_ACTIM_CTRLB_0);
                __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_1);
                __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_0);
                __raw_writel(MICRON_V_ACTIMB_200_2, SDRC_ACTIM_CTRLB_0);
                __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_1);


@@ -343,11 +322,10 @@ u32 get_osc_clk_speed(void)
  * prcm_init() - inits clocks for PRCM as defined in clocks.h
  *   -- called from SRAM, or Flash (using temp SRAM stack).
  *****************************************************************************/
  * prcm_init() - inits clocks for PRCM as defined in clocks.h
  *   -- called from SRAM, or Flash (using temp SRAM stack).
  *****************************************************************************/

-void prcm_init(void)
+void prcm_init_(u32 cpu_family)

 {
 {

-       u32 osc_clk = 0, sys_clkin_sel;
-       dpll_param *dpll_param_p;
-       u32 clk_index, sil_index;
+       u32 osc_clk, sys_clkin_sel;
+       u32 m;

 
        /* Gauge the input clock speed and find out the sys_clkin_sel
         * value corresponding to the input clock.
 
        /* Gauge the input clock speed and find out the sys_clkin_sel
         * value corresponding to the input clock.


@@ -358,109 +336,58 @@ void prcm_init(void)
        sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel);  /* set input crystal speed */
 
        /* If the input clock is greater than 19.2M always divide/2 */
        sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel);  /* set input crystal speed */
 
        /* If the input clock is greater than 19.2M always divide/2 */

-       if (sys_clkin_sel > 2) {
-               sr32(PRM_CLKSRC_CTRL, 6, 2, 2); /* input clock divider */
-               clk_index = sys_clkin_sel / 2;
-       } else {
-               sr32(PRM_CLKSRC_CTRL, 6, 2, 1); /* input clock divider */
-               clk_index = sys_clkin_sel;
-       }
+       m = (sys_clkin_sel > 2) ? 2 : 1;
+       sr32(PRM_CLKSRC_CTRL, 6, 2, m); /* input clock divider */

 
        sr32(PRM_CLKSRC_CTRL, 0, 2, 0);/* Bypass mode: T2 inputs a square clock */
 
 
        sr32(PRM_CLKSRC_CTRL, 0, 2, 0);/* Bypass mode: T2 inputs a square clock */
 

-       /* The DPLL tables are defined according to sysclk value and
-        * silicon revision. The clk_index value will be used to get
-        * the values for that input sysclk from the DPLL param table
-        * and sil_index will get the values for that SysClk for the
-        * appropriate silicon rev.
-        */
-       sil_index = !(get_cpu_rev() == CPU_3XX_ES10);
-

        /* Unlock MPU DPLL (slows things down, and needed later) */
        sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);
        wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY);
 
        /* Unlock MPU DPLL (slows things down, and needed later) */
        sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);
        wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY);
 

-       /* Getting the base address of Core DPLL param table */
-       dpll_param_p = (dpll_param *) get_core_dpll_param();
-       /* Moving it to the right sysclk and ES rev base */
-       dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;

        /* CORE DPLL */
        /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */
        sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
        wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
 
        /* CORE DPLL */
        /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */
        sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
        wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
 

-        /* For 3430 ES1.0 Errata 1.50, default value directly doesnt
-       work. write another value and then default value. */
-       sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1);     /* m3x2 */
+       /* *_13 because of 'input clock divider' above */

        sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */
        sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */

-       sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2);  /* Set M2 */
-       sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m);  /* Set M */
-       sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n);    /* Set N */
+       sr32(CM_CLKSEL1_PLL, 27, 2, M2_13);     /* Set M2 */
+       sr32(CM_CLKSEL1_PLL, 16, 11, M_13);     /* Set M */
+       sr32(CM_CLKSEL1_PLL, 8, 7, N_13);       /* Set N */

        sr32(CM_CLKSEL1_PLL, 6, 1, 0);  /* 96M Src */
        sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV);       /* ssi */
        sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV);      /* fsusb */
        sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV);        /* l4 */
        sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV);        /* l3 */
        sr32(CM_CLKSEL1_PLL, 6, 1, 0);  /* 96M Src */
        sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV);       /* ssi */
        sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV);      /* fsusb */
        sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV);        /* l4 */
        sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV);        /* l3 */

-       sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV);     /* gfx */

        sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM);   /* reset mgr */
        sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM);   /* reset mgr */

-       sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel);   /* FREQSEL */
+       sr32(CM_CLKEN_PLL, 4, 4, FSEL_13);      /* FREQSEL */

        sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK);     /* lock mode */
        wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
 
        sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK);     /* lock mode */
        wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
 

-       /* Getting the base address to PER  DPLL param table */
-       dpll_param_p = (dpll_param *) get_per_dpll_param();
-       /* Moving it to the right sysclk base */
-       dpll_param_p = dpll_param_p + clk_index;

        /* PER DPLL */
        /* PER DPLL */

+       m = (cpu_family == CPU_OMAP36XX) ? 0x360 : 0x1B0;

        sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP);
        wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY);
        sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2);  /* set M6 */
        sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2);    /* set M5 */
        sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2);    /* set M4 */
        sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2);    /* set M3 */
        sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP);
        wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY);
        sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2);  /* set M6 */
        sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2);    /* set M5 */
        sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2);    /* set M4 */
        sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2);    /* set M3 */

-
-       if (get_cpu_family() == CPU_OMAP36XX) {
-               sr32(CM_CLKSEL3_PLL, 0, 5, CORE_DPLL_PARAM_M2);   /* set M2 */
-               sr32(CM_CLKSEL2_PLL, 8, 11, CORE_DPLL_PARAM_M);   /* set m */
-               sr32(CM_CLKSEL2_PLL, 0, 7, CORE_DPLL_PARAM_N);    /* set n */
-       } else {
-               sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2);   /* set M2 */
-               sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m);   /* set m */
-               sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n);    /* set n */
-       }
-
-       sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel);  /* FREQSEL */
+       sr32(CM_CLKSEL3_PLL, 0, 5, 0x09);       /* set M2 */
+       sr32(CM_CLKSEL2_PLL, 8, 11, m);         /* set m */
+       sr32(CM_CLKSEL2_PLL, 0, 7, 0x0C);       /* set n */
+       sr32(CM_CLKEN_PLL, 20, 4, 0x03);        /* FREQSEL */

        sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK);    /* lock mode */
        wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);
 
        sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK);    /* lock mode */
        wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);
 

-       /* Getting the base address to MPU DPLL param table */
-       dpll_param_p = (dpll_param *) get_mpu_dpll_param();
-
-       /* Moving it to the right sysclk and ES rev base */
-       dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
-

        /* MPU DPLL (unlocked already) */
        /* MPU DPLL (unlocked already) */

-       sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2);       /* Set M2 */
-       sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m);       /* Set M */
-       sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n);        /* Set N */
-       sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel);       /* FREQSEL */
+       sr32(CM_CLKSEL2_PLL_MPU, 0, 5, 0x01);   /* Set M2 */
+       sr32(CM_CLKSEL1_PLL_MPU, 8, 11, 500);   /* Set M */
+       sr32(CM_CLKSEL1_PLL_MPU, 0, 7, 0x0C);   /* Set N */
+       sr32(CM_CLKEN_PLL_MPU, 4, 4, 0x03);     /* FREQSEL */

        sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */
        wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY);
 
        sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */
        wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY);
 

-       /* Getting the base address to IVA DPLL param table */
-       dpll_param_p = (dpll_param *) get_iva_dpll_param();
-       /* Moving it to the right sysclk and ES rev base */
-       dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
-       /* IVA DPLL (set to 12*20=240MHz) */
-       sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP);
-       wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY);
-       sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2);      /* set M2 */
-       sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m);      /* set M */
-       sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n);       /* set N */
-       sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel);      /* FREQSEL */
-       sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK);        /* lock mode */
-       wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY);
-

        /* Set up GPTimers to sys_clk source only */
        sr32(CM_CLKSEL_PER, 0, 8, 0xff);
        sr32(CM_CLKSEL_WKUP, 0, 1, 1);
        /* Set up GPTimers to sys_clk source only */
        sr32(CM_CLKSEL_PER, 0, 8, 0xff);
        sr32(CM_CLKSEL_WKUP, 0, 1, 1);


@@ -476,13 +403,17 @@ void prcm_init(void)
 
 void s_init(void)
 {
 
 void s_init(void)
 {

+       u32 cpu_family;
+

        watchdog_init();
        try_unlock_memory();
        set_muxconf_regs();
        delay(100);
        per_clocks_enable();
        watchdog_init();
        try_unlock_memory();
        set_muxconf_regs();
        delay(100);
        per_clocks_enable();

-       prcm_init();
-       config_sdram_ddr();
+
+       cpu_family = get_cpu_family();
+       prcm_init_(cpu_family);
+       config_sdram_ddr(cpu_family);

 }
 
 /*******************************************************
 }
 
 /*******************************************************

diff --git a/board/pandora/platform.S b/board/pandora/platform.S
index 7b1fa7b..89cf77e 100644 (file)
--- a/board/pandora/platform.S
+++ b/board/pandora/platform.S
@@ -184,176 +184,5 @@ lowlevel_init:
        /* the literal pools origin */
        .ltorg
 
        /* the literal pools origin */
        .ltorg
 

-REG_CONTROL_STATUS:
-       .word CONTROL_STATUS

 SRAM_STACK:
        .word LOW_LEVEL_SRAM_STACK
 SRAM_STACK:
        .word LOW_LEVEL_SRAM_STACK

-
-/* DPLL(1-4) PARAM TABLES */
-/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal
- * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c).
- * The values are defined for all possible sysclk and for ES1 and ES2.
- */
-
-mpu_dpll_param:
-/* 12MHz */
-/* ES1 */
-.word 0x0FE,0x07,0x05,0x01
-/* ES2 */
-.word 0x0FA,0x05,0x07,0x01
-/* 3410 */
-.word 0x085,0x05,0x07,0x01
-
-/* 13MHz */
-/* ES1 */
-.word 0x17D,0x0C,0x03,0x01
-/* ES2 */
-.word 0x1F4,0x0C,0x03,0x01
-/* 3410 */
-.word 0x10A,0x0C,0x03,0x01
-
-/* 19.2MHz */
-/* ES1 */
-.word 0x179,0x12,0x04,0x01
-/* ES2 */
-.word 0x271,0x17,0x03,0x01
-/* 3410 */
-.word 0x14C,0x17,0x03,0x01
-
-/* 26MHz */
-/* ES1 */
-.word 0x17D,0x19,0x03,0x01
-/* ES2 */
-.word 0x0FA,0x0C,0x07,0x01
-/* 3410 */
-.word 0x085,0x0C,0x07,0x01
-
-/* 38.4MHz */
-/* ES1 */
-.word 0x1FA,0x32,0x03,0x01
-/* ES2 */
-.word 0x271,0x2F,0x03,0x01
-/* 3410 */
-.word 0x14C,0x2F,0x03,0x01
-
-
-.globl get_mpu_dpll_param
-get_mpu_dpll_param:
-       adr r0, mpu_dpll_param
-       mov pc, lr
-
-iva_dpll_param:
-/* 12MHz */
-/* ES1 */
-.word 0x07D,0x05,0x07,0x01
-/* ES2 */
-.word 0x0B4,0x05,0x07,0x01
-/* 3410 */
-.word 0x085,0x05,0x07,0x01
-
-/* 13MHz */
-/* ES1 */
-.word 0x0FA,0x0C,0x03,0x01
-/* ES2 */
-.word 0x168,0x0C,0x03,0x01
-/* 3410 */
-.word 0x10A,0x0C,0x03,0x01
-
-/* 19.2MHz */
-/* ES1 */
-.word 0x082,0x09,0x07,0x01
-/* ES2 */
-.word 0x0E1,0x0B,0x06,0x01
-/* 3410 */
-.word 0x14C,0x17,0x03,0x01
-
-/* 26MHz */
-/* ES1 */
-.word 0x07D,0x0C,0x07,0x01
-/* ES2 */
-.word 0x0B4,0x0C,0x07,0x01
-/* 3410 */
-.word 0x085,0x0C,0x07,0x01
-
-/* 38.4MHz */
-/* ES1 */
-.word 0x13F,0x30,0x03,0x01
-/* ES2 */
-.word 0x0E1,0x17,0x06,0x01
-/* 3410 */
-.word 0x14C,0x2F,0x03,0x01
-
-
-.globl get_iva_dpll_param
-get_iva_dpll_param:
-       adr r0, iva_dpll_param
-       mov pc, lr
-
-/* Core DPLL targets for L3 at 166 & L133 */
-core_dpll_param:
-/* 12MHz */
-/* ES1 */
-.word M_12_ES1,M_12_ES1,FSL_12_ES1,M2_12_ES1
-/* ES2 */
-.word M_12,N_12,FSEL_12,M2_12
-/* 3410 */
-.word M_12,N_12,FSEL_12,M2_12
-
-/* 13MHz */
-/* ES1 */
-.word M_13_ES1,N_13_ES1,FSL_13_ES1,M2_13_ES1
-/* ES2 */
-.word M_13,N_13,FSEL_13,M2_13
-/* 3410 */
-.word M_13,N_13,FSEL_13,M2_13
-
-/* 19.2MHz */
-/* ES1 */
-.word M_19p2_ES1,N_19p2_ES1,FSL_19p2_ES1,M2_19p2_ES1
-/* ES2 */
-.word M_19p2,N_19p2,FSEL_19p2,M2_19p2
-/* 3410 */
-.word M_19p2,N_19p2,FSEL_19p2,M2_19p2
-
-/* 26MHz */
-/* ES1 */
-.word M_26_ES1,N_26_ES1,FSL_26_ES1,M2_26_ES1
-/* ES2 */
-.word M_26,N_26,FSEL_26,M2_26
-/* 3410 */
-.word M_26,N_26,FSEL_26,M2_26
-
-/* 38.4MHz */
-/* ES1 */
-.word M_38p4_ES1,N_38p4_ES1,FSL_38p4_ES1,M2_38p4_ES1
-/* ES2 */
-.word M_38p4,N_38p4,FSEL_38p4,M2_38p4
-/* 3410 */
-.word M_38p4,N_38p4,FSEL_38p4,M2_38p4
-
-.globl get_core_dpll_param
-get_core_dpll_param:
-       adr r0, core_dpll_param
-       mov pc, lr
-
-/* PER DPLL values are same for both ES1 and ES2 */
-per_dpll_param:
-/* 12MHz */
-.word 0xD8,0x05,0x07,0x09
-
-/* 13MHz */
-.word 0x1B0,0x0C,0x03,0x09
-
-/* 19.2MHz */
-.word 0xE1,0x09,0x07,0x09
-
-/* 26MHz */
-.word 0xD8,0x0C,0x07,0x09
-
-/* 38.4MHz */
-.word 0xE1,0x13,0x07,0x09
-
-.globl get_per_dpll_param
-get_per_dpll_param:
-       adr r0, per_dpll_param
-       mov pc, lr